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11. 发明申请

US20130139119A1 PARTITIONING AND SCHEDULING UNIFORM OPERATOR LOGIC TREES FOR HARDWARE ACCELERATORS 失效
标题翻译：硬件加速器的分区和调度统一运算符逻辑条
公开(公告)号：US20130139119A1
公开(公告)日：2013-05-30
申请号：US13305156
申请日：2011-11-28
申请人： Zoltan T. Hidvegi , Michael D. Moffitt , Mátyás A. Sustik
发明人： Zoltan T. Hidvegi , Michael D. Moffitt , Mátyás A. Sustik
IPC分类号： G06F17/50
CPC分类号： G06F17/5027 , G06F2217/04
摘要： A circuit design is compiled for hardware-accelerated functional verification by removing internal gates of a uniform operator tree (e.g., an assertion tree) while retaining node information, and partitioning the circuit to optimize connectivity without being constrained by the uniform operator tree. After partitioning, sub-trees are constructed for the partitions, and aggregated to form a master tree. The sub-trees can have leaf nodes at varying depths based on ranks of the leaf nodes, and the master tree can similarly provide inputs from the sub-trees at varying depths based on simulation depths for the sub-trees. The resynthesized master tree is structurally distinct from the original uniform operator tree but, since the inputs are commutative (e.g., OR gates), the functional equivalence of the model is preserved.
摘要翻译：通过在保留节点信息的同时移除统一运算符树（例如，断言树）的内部门来编译用于硬件加速功能验证的电路设计，并且划分电路以优化连接性而不受统一运算符树的约束。分区后，为分区构建子树，并聚合形成主树。子树可以基于叶节点的等级具有不同深度的叶节点，并且主树可以基于子树的模拟深度类似地提供来自不同深度的子树的输入。重新合成的主树在结构上与原始统一运算符树不同，但是由于输入是可交换的（例如，或门），所以保留了模型的功能等同性。

12. 发明授权

US08108818B2 Method and system for point-to-point fast delay estimation for VLSI circuits 有权
标题翻译：用于VLSI电路的点对点快速延迟估计的方法和系统
公开(公告)号：US08108818B2
公开(公告)日：2012-01-31
申请号：US12363340
申请日：2009-01-30
申请人： Chin Ngai Sze , Charles J. Alpert , Michael D. Moffitt , Zhuo Li
发明人： Chin Ngai Sze , Charles J. Alpert , Michael D. Moffitt , Zhuo Li
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： The present disclosure is directed to a method for estimating an interconnect delay for a source-to-sink path of a net within a Very Large Scale Integration (VLSI) circuit, the source-to-sink path connecting a source and a sink in the net. The method may comprise estimating a total wire capacitance; calculating a delay contribution based on delay of the source-to-sink path and delay of a plurality of off-path sinks; and estimating the interconnect delay for the source-to-sink path based on the delay contribution.
摘要翻译：本公开涉及一种用于估计在超大规模集成（VLSI）电路内的网络的源到汇路径的互连延迟的方法，所述源到宿路径连接源和汇中的源净。该方法可以包括估计总线电容; 基于多个非路径汇的源到汇路径和延迟的延迟来计算延迟贡献; 以及基于延迟贡献来估计源到汇路径的互连延迟。

13. 发明申请

US20100199243A1 METHOD AND SYSTEM FOR POINT-TO-POINT FAST DELAY ESTIMATION FOR VLSI CIRCUITS 有权
标题翻译：用于VLSI电路的点到点快速延迟估计的方法和系统
公开(公告)号：US20100199243A1
公开(公告)日：2010-08-05
申请号：US12363340
申请日：2009-01-30
申请人： Chin Ngai Sze , Charles J. Alpert , Michael D. Moffitt , Zhuo Li
发明人： Chin Ngai Sze , Charles J. Alpert , Michael D. Moffitt , Zhuo Li
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： The present disclosure is directed to a method for estimating an interconnect delay for a source-to-sink path of a net within a Very Large Scale Integration (VLSI) circuit, the source-to-sink path connecting a source and a sink in the net. The method may comprise estimating a total wire capacitance; calculating a delay contribution based on delay of the source-to-sink path and delay of a plurality of off-path sinks; and estimating the interconnect delay for the source-to-sink path based on the delay contribution.
摘要翻译：本公开涉及一种用于估计在超大规模集成（VLSI）电路内的网络的源到汇路径的互连延迟的方法，所述源到宿路径连接源和汇中的源净。该方法可以包括估计总线电容; 基于多个非路径汇的源到汇路径和延迟的延迟来计算延迟贡献; 以及基于延迟贡献来估计源到汇路径的互连延迟。

14. 发明授权

US07707530B2 Incremental timing-driven, physical-synthesis using discrete optimization 有权
标题翻译：使用离散优化的增量式时序驱动，物理合成
公开(公告)号：US07707530B2
公开(公告)日：2010-04-27
申请号：US11941105
申请日：2007-11-16
申请人： Charles J. Alpert , Zhuo Li , Michael D. Moffitt , David A. Papa
发明人： Charles J. Alpert , Zhuo Li , Michael D. Moffitt , David A. Papa
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5072 , G06F2217/84
摘要： A method, data processing system and computer program product for optimizing the placement of logic gates of a subcircuit in a physical synthesis flow. A Path Smoothing utility identifies one or more movable gates based on at least one selection criteria. A set of legalized candidate locations corresponding to one or more identified movable gates is generated. A disjunctive timing graph based on the generated set of legalized candidate locations is then generated. An optimal location of one or more movable gate(s) is determined using a recursive branch-and-bound search and stored in the computing device.
摘要翻译：一种用于优化物理合成流中子电路的逻辑门的布置的方法，数据处理系统和计算机程序产品。路径平滑实用程序基于至少一个选择标准识别一个或多个可移动门。生成与一个或多个识别的可移动门对应的一组合法化候选位置。然后生成基于生成的合法化候选位置集合的分离时序图。一个或多个可移动门的最佳位置使用递归分支搜索并被存储在计算设备中来确定。

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