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11. 发明授权

US4624004A Buried channel MESFET with backside source contact 失效
标题翻译：埋地通道MESFET与背面源接触
公开(公告)号：US4624004A
公开(公告)日：1986-11-18
申请号：US755534
申请日：1985-07-15
申请人： Joseph A. Calviello
发明人： Joseph A. Calviello
IPC分类号： H01L29/417 , H01L29/80 , H01L29/06 , H01L29/20
CPC分类号： H01L29/4175
摘要： The fabrication of high performance and reliable Buried Channel Field Effect Transistor (BCFET) using Schottky gate junction and heavily doped N layers for the source and drain electrode is described. The BCFET is composed of a semi-insulating substrate in which two N layers for the drain electrodes and one N layer for the source electrode are formed in one of the semi-insulating surface. The N source electrode is centrally located between the two N drain electrodes and all three lie in the same plane. The source and drain electrodes are separated by a thin semi-insulating layer, the length of which can range from 0.5 micron to several micron range, depending on the desired voltage breakdown. A Schottky gate is defined in an active N layer directly above the source N layer. The ohmic contacts for the source and drain N layers are defined several microns away from the Schottky junction, resulting in a considerable improvement in device reliability. Reliability is further enhanced by the fact that the resulting device is buried within the material where it is insulated from the ambient.
摘要翻译：描述了使用肖特基栅极结和用于源极和漏极的重掺杂N层的高性能和可靠的埋地沟道场效应晶体管（BCFET）的制造。 BCFET由半绝缘基板构成，其中在半绝缘表面之一上形成有用于漏电极的两个N层和用于源电极的一个N层。 N源电极位于两个N个漏极之间的中心，所有三个位于同一平面。根据所需的电压击穿，源极和漏极由薄的半绝缘层分隔开，半绝缘层的长度可以在0.5微米到几微米的范围内。在源N层正上方的有源N层中定义肖特基门。用于源极和漏极N层的欧姆接触距离肖特基结约几微米，导致器件可靠性的显着提高。通过将所得到的装置埋在材料中与绝缘材料绝缘的事实进一步增强了可靠性。

12. 发明授权

US4549194A Light sensitive detector 失效
标题翻译：光敏探测器
公开(公告)号：US4549194A
公开(公告)日：1985-10-22
申请号：US365352
申请日：1982-03-29
申请人： Joseph A. Calviello
发明人： Joseph A. Calviello
IPC分类号： H01L31/0352 , H01L31/101 , H01L31/00
CPC分类号： H01L31/101 , H01L31/03529 , Y02E10/50
摘要： A tunnel diode having a generally rectangular junction area in the 10.sup.-10 to 10.sup.-11 cm.sup.2 range formed in a quasi-planar structure of a first metal, an oxide of the first metal and a second metal. The first metal may be tantalum or other similarly slow oxidizable metals. The second metal may be selected from a group also including tantalum. For a symmetrical junction, the first and second metals are the same, however, for an asymmetrical junction the first and second metals are different. To reduce the diode series electrical and thermal resistance, a gold layer is deposited over the first and second metals. The gold layer over the first metal is deposited everywhere except at or within a few microns of the junction. The device provides a small junction area and also negligible parasitic shunt capacitance which are necessary for efficient room temperature operation at frequencies in the submillimeter to optical region. Direct and heterodyne detection in the 10 microns region has been successfully achieved with these devices.
摘要翻译：形成在第一金属，第一金属的氧化物和第二金属的准平面结构中的10-10至10-11cm 2范围内的大致矩形结面积的隧道二极管。第一种金属可以是钽或其它类似的缓慢的可氧化金属。第二金属可以选自也包括钽的组。对于对称结，第一和第二金属是相同的，然而，对于非对称结，第一和第二金属是不同的。为了降低二极管串联电阻和热阻，金层沉积在第一和第二金属上。第一金属上的金层沉积在除了在该结的几微米处或其附近的任何地方。该器件提供小的接合面积以及可忽略的寄生并联电容，这是在亚毫米至光学区域的频率下有效的室温运行所必需的。这些器件已经成功地实现了10微米区域的直接和外差检测。

13. 发明授权

US4310570A Field-effect transistors with micron and submicron gate lengths 失效
标题翻译：具有微米和亚微米栅极长度的场效应晶体管
公开(公告)号：US4310570A
公开(公告)日：1982-01-12
申请号：US145625
申请日：1980-05-01
申请人： Joseph A. Calviello
发明人： Joseph A. Calviello
IPC分类号： H01L21/24 , H01L21/285 , H01L21/338 , H01L29/45 , H01L29/78 , H01L29/80 , H01L29/812 , H01L21/283
CPC分类号： H01L29/66856 , H01L21/242 , H01L21/28575 , H01L29/452 , H01L29/7839 , H01L29/806 , H01L29/812 , Y10S148/084
摘要： A method for forming ohmic contacts of gold and germanium gold on a gallium arsenide substrate in which a layer of silicon dioxide is placed over the gold in the contact area prior to sinter alloying to improve wetting and reduce contact resistance.
摘要翻译：在砷化镓衬底上形成金和锗金的欧姆接触的方法，其中在烧结合金化之前，将二氧化硅层置于接触区域中的金上，以改善润湿性并降低接触电阻。

14. 发明授权

US5341114A Integrated limiter and amplifying devices 失效
标题翻译：集成限幅器和放大器件
公开(公告)号：US5341114A
公开(公告)日：1994-08-23
申请号：US608219
申请日：1990-11-02
申请人： Joseph A. Calviello , John A. Pierro
发明人： Joseph A. Calviello , John A. Pierro
IPC分类号： H01L27/06 , H03G11/02 , H03G11/04 , H01P1/22 , H03F3/14 , H03G3/20
CPC分类号： H01L27/0605 , H03G11/025
摘要： Integrated circuit structure and processing is provided for a high power limiter including at least a first anti-parallel array of monolithically integrated Schottky diodes. In a further embodiment, integrated circuit structure and processing is provided for an MMIC, microwave and millimeter wave monolithic integrated circuit, including an amplifier and a high power limiter monolithically integrated on the same substrate.
摘要翻译：提供了集成电路结构和处理，用于包括至少第一反并联阵列的单片集成肖特基二极管的高功率限制器。在另一个实施例中，为MMIC，微波和毫米波单片集成电路提供集成电路结构和处理，其包括单片集成在同一衬底上的放大器和高功率限幅器。

15. 发明授权

US4935789A Buried channel FET with lateral growth over amorphous region 失效
标题翻译：在非晶区域侧向生长的掩埋通道FET
公开(公告)号：US4935789A
公开(公告)日：1990-06-19
申请号：US306706
申请日：1989-02-03
申请人： Joseph A. Calviello
发明人： Joseph A. Calviello
IPC分类号： H01L21/768 , H01L23/48 , H01L29/08 , H01L29/417 , H01L29/812
CPC分类号： H01L21/76898 , H01L23/481 , H01L29/0891 , H01L29/4175 , H01L29/812 , H01L2924/0002
摘要： A buried channel field effect transistor is provided by in situ growth of all epitaxial layers growing laterally towards each other along central amorphous semi-insulating humps (1222, 1224) and merging (1232) above the humps to epitaxially grow in single crystalline form to provide the active N layer (1232).
摘要翻译：掩埋沟道场效应晶体管通过沿着中心非晶半绝缘隆起（1222,1224）横向朝向彼此生长的所有外延层的原位生长提供，并且在凸起之上的合并（1232）以单晶形式外延生长以提供活性N层（1232）。

16. 发明授权

US4837175A Making a buried channel FET with lateral growth over amorphous region 失效
标题翻译：在非晶区域上制造具有横向生长的掩埋通道FET
公开(公告)号：US4837175A
公开(公告)日：1989-06-06
申请号：US194532
申请日：1988-05-16
申请人： Joseph A. Calviello
发明人： Joseph A. Calviello
IPC分类号： H01L21/768 , H01L23/48 , H01L29/08 , H01L29/812
CPC分类号： H01L21/76898 , H01L23/481 , H01L29/0891 , H01L29/812 , H01L2924/0002
摘要： A buried channel field effect transistor is provided by in situ growth of all epitaxial layers growing laterally towards each other along central amorphous semi-insulating humps (1222, 1224) and merging (1232) above the humps to epitaxially grow in single crystalline form to provide the active N layer (1232).
摘要翻译：掩埋沟道场效应晶体管通过沿着中心非晶半绝缘隆起（1222,1224）横向朝向彼此生长的所有外延层的原位生长提供，并且在凸起之上的合并（1232）以单晶形式外延生长以提供活性N层（1232）。

17. 发明授权

US4312113A Method of making field-effect transistors with micron and submicron gate lengths 失效
公开(公告)号：US4312113A
公开(公告)日：1982-01-26
申请号：US98802
申请日：1979-11-29
申请人： Joseph A. Calviello
发明人： Joseph A. Calviello
IPC分类号： H01L21/336 , H01L29/47 , H01L29/78 , H01L29/80 , H01L29/812 , H01L21/285
CPC分类号： H01L29/66522 , H01L29/475 , H01L29/7839 , H01L29/806 , H01L29/812 , Y10S148/084
摘要： Field-effect transistors using Schottky junctions formed of tantalum on N-doped gallium arsenide with tantalum oxide and native oxide passivations.

18. 发明授权

US4312112A Method of making field-effect transistors with micron and submicron gate lengths 失效
标题翻译：制造具有微米和亚微米栅极长度的场效应晶体管的方法
公开(公告)号：US4312112A
公开(公告)日：1982-01-26
申请号：US98710
申请日：1979-11-29
申请人： Joseph A. Calviello
发明人： Joseph A. Calviello
IPC分类号： H01L21/338 , H01L29/47 , H01L29/78 , H01L29/80 , H01L29/812 , H01L21/285
CPC分类号： H01L29/66863 , H01L29/475 , H01L29/7839 , H01L29/806 , H01L29/812
摘要： Field-effect transistors using Schottky junctions formed of tantalum on N-doped gallium arsenide with tantalum oxide and native oxide passivations.
摘要翻译：使用由钽形成的肖特基结的N型掺杂砷化镓与氧化钽和天然氧化物钝化物的场效应晶体管。

19. 发明授权

US4301233A Beam lead Schottky barrier diode for operation at millimeter and submillimeter wave frequencies 失效
标题翻译：波导肖特基势垒二极管，用于毫米波和亚毫米波频率的工作
公开(公告)号：US4301233A
公开(公告)日：1981-11-17
申请号：US156223
申请日：1980-06-03
申请人： Joseph A. Calviello
发明人： Joseph A. Calviello
IPC分类号： H01L21/285 , H01L21/329 , H01L21/60 , H01L23/482 , H01L29/47 , H01L29/872 , H01L29/48
CPC分类号： H01L29/66212 , H01L21/28581 , H01L21/28587 , H01L23/4822 , H01L24/11 , H01L29/475 , H01L29/872 , H01L2224/13099 , H01L2924/01005 , H01L2924/01006 , H01L2924/01011 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/01024 , H01L2924/01032 , H01L2924/01033 , H01L2924/01042 , H01L2924/01073 , H01L2924/01079 , H01L2924/01082 , H01L2924/10329 , H01L2924/12032 , H01L2924/12043 , H01L2924/30105 , H01L2924/3025 , Y10S148/10 , Y10S148/105
摘要： A beam lead gallium arsenide diode having a rectangular junction perimeter conforming to that the beam lead, recovers ninety-five percent of the junction current and provides an almost perfect ideality factor of 1.07. This device is formed on a semi-insulating substrate to provide for isolation from adjacent devices on the same substrate and for confining the current to a direct path from the junction to an immediately adjacent ohmic contact. An extremely small junction area necessary for operation at millimeter wave frequencies is formed by special processing which includes the use of dry etching and the fabrication of the junction prior to passivation.
摘要翻译：具有符合光束引线的矩形连接周边的光束引线砷化镓二极管恢复了结电流的百分之九十五，并提供了1.07的几乎完美的理想因子。该器件形成在半绝缘衬底上以提供与同一衬底上的相邻器件的隔离，并将电流限制在从结到直接相邻的欧姆接触的直接路径。通过特殊处理形成了以毫米波频率操作所需的非常小的接合面积，其包括使用干蚀刻和钝化前的结的制造。

20. 发明授权

US5030579A Method of making an FET by ion implantation through a partially opaque implant mask 失效
标题翻译：通过部分不透明植入掩模通过离子注入制造FET的方法
公开(公告)号：US5030579A
公开(公告)日：1991-07-09
申请号：US333140
申请日：1989-04-04
申请人： Joseph A. Calviello
发明人： Joseph A. Calviello
IPC分类号： H01L21/266 , H01L21/338
CPC分类号： H01L29/66871 , H01L21/266
摘要： Semiconductor processing techniques and devices are provided using a partially opaque ion implantation mask to control the profile of active layers in microwave and millimeter wave monolithic integrated circuits. An N+ layer can be implanted before or after active layer formation. Selection of mask thickness enables control of active channel depth. Adjustment of gate to drain separation in MMIC FETs is also enabled, to control gate to drain voltage. Source to gate series resistance is also controlled. Multiple dielectric layers afford variable mask thicknesses to enable simultaneous formation of differing power level devices monolithically in the same substrate, including low noise high speed devices and power devices. The process and device structure provides enhanced yield, performance, uniformity and reliability.
摘要翻译：使用部分不透明的离子注入掩模提供半导体处理技术和器件，以控制微波和毫米波单片集成电路中的有源层的轮廓。可以在活性层形成之前或之后植入N +层。选择掩模厚度可以控制有源通道深度。也可以调整MMIC FET中的栅极到漏极分离，以控制栅极到漏极电压。源极栅极串联电阻也受到控制。多个电介质层提供可变的掩模厚度以使得能够在同一衬底中同时形成不同功率电平器件，包括低噪声高速器件和功率器件。该工艺和器件结构提高了产量，性能，均匀性和可靠性。

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