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11. 发明申请

US20050118753A1 Low cost fabrication method for high voltage, high drain current MOS transistor 有权
标题翻译：低成本高漏极电流MOS晶体管制造方法
公开(公告)号：US20050118753A1
公开(公告)日：2005-06-02
申请号：US10725642
申请日：2003-12-02
申请人： Taylor Efland , Jozef Mitros , Imran Khan
发明人： Taylor Efland , Jozef Mitros , Imran Khan
IPC分类号： H01L21/336 , H01L21/8234 , H01L29/08 , H01L29/10 , H01L29/423 , H01L29/78
CPC分类号： H01L29/0847 , H01L29/0878 , H01L29/1083 , H01L29/1087 , H01L29/42368 , H01L29/66659 , H01L29/7835
摘要： A method for reducing the drain resistance of a drain-extended MOS transistor in a semiconductor wafer, while maintaining a high transistor breakdown voltage. The method provides a first well (502) of a first conductivity type, operable as the extension of the transistor drain (501) of the first conductivity type; portions of the well are covered by a first insulator (503) having a first thickness. A second well (504) of the opposite conductivity type is intended to contain the transistor source (506) of the first conductivity type; portions of the second well are covered by a second insulator (507) thinner than the first insulator. The first and second wells form a junction (505) that terminates at the second insulator (530a, 530b). The method deposits a photoresist layer (510) over the wafer, which is patterned by opening a window (510a) that extends from the drain to the junction termination. Next, ions (540) of the first conductivity type are implanted through the window into the first well; these said ions have an energy to limit the penetration depth (541) to the first insulator thickness, and a dose to create a well region (560) of high doping concentration adjacent to the junction termination (530a).
摘要翻译：一种在保持高晶体管击穿电压的同时降低半导体晶片中的漏极扩展MOS晶体管的漏极电阻的方法。该方法提供第一导电类型的第一阱（502），其可操作为第一导电类型的晶体管漏极（501）的延伸; 阱的一部分被具有第一厚度的第一绝缘体（503）覆盖。相反导电类型的第二阱（504）旨在包含第一导电类型的晶体管源（506）; 第二阱的部分被比第一绝缘体薄的第二绝缘体（507）覆盖。第一和第二阱形成终止于第二绝缘体（530a，530b）的结（505）。该方法将光致抗蚀剂层（510）沉积在晶片之上，其通过打开从漏极延伸到结终端的窗口（510a）而被图案化。接下来，通过窗口将第一导电类型的离子（540）注入到第一阱中; 这些所述离子具有将穿透深度（541）限制到第一绝缘体厚度的能量，以及用于产生邻近连接终端（530a）的高掺杂浓度的阱区（560）的剂量。

12. 发明授权

US06432791B1 Integrated circuit capacitor and method 有权
标题翻译：集成电路电容及方法
公开(公告)号：US06432791B1
公开(公告)日：2002-08-13
申请号：US09548061
申请日：2000-04-12
申请人： Louis N. Hutter , Peter S. Ying , Imran Khan
发明人： Louis N. Hutter , Peter S. Ying , Imran Khan
IPC分类号： H01L218242
CPC分类号： H01L27/0629
摘要： Capacitors for integrated circuits with a common polysilicon layer for both MOS gates (274, 276, 278) and capacitor (270) lower plates but with implanted doping for the gates and masked diffusive doping for the capacitor plates.
摘要翻译：用于集成电路的电容器具有用于两个MOS栅极（274,276,278）和电容器（270）的公共多晶硅层，但具有用于栅极的注入掺杂和用于电容器板的掩蔽扩散掺杂。

13. 发明申请

US20220147706A1 OPTIMIZED MACHINE LEARNING MARKETPLACE ASSISTANT 有权
公开(公告)号：US20220147706A1
公开(公告)日：2022-05-12
申请号：US17587732
申请日：2022-01-28
申请人： USMAN RANA , Imran Khan
发明人： USMAN RANA , Imran Khan
IPC分类号： G06F40/205 , G06F40/279 , G06F40/40 , G06Q30/06
摘要： A method for implementing an automated assistant on one or more computing devices with a processor, a memory, and systems to receive an input at a computing device and parsing that input using a pragmatic natural language processor. A score is assigned to the input and a user intent is determined based on the assigned score. A user may search for a service or item and the system may generate a ranking of the item based on a number of attributes.

14. 发明授权

US08873367B2 Generic packet filtering 有权
标题翻译：通用包过滤
公开(公告)号：US08873367B2
公开(公告)日：2014-10-28
申请号：US13411146
申请日：2012-03-02
申请人： Michelle Perras , Juan Carlos Zuniga , Alexander Reznik , Reeteshkumar Varshney , Imran Khan
发明人： Michelle Perras , Juan Carlos Zuniga , Alexander Reznik , Reeteshkumar Varshney , Imran Khan
IPC分类号： H04W4/00 , H04L29/06 , H04W28/06
CPC分类号： H04L69/22 , H04L69/14 , H04W28/06
摘要： Embodiments contemplate one or more techniques for packet filtering. One or more embodiments may apply specific routing and/or forwarding rules on some or each packet when a device has one or more, or multiple, interfaces. Contemplated filtering techniques may be implemented in a module and/or without modifying an IP stack. The contemplated packet filtering techniques may apply to a terminal in uplink and/or downlink as well as to any network node. An incoming packet table may be created using 5-tuple, 6-tuple, and/or tags, among other mechanisms, to support incoming and/or outgoing packet filtering.
摘要翻译：实施例考虑了一种或多种用于分组过滤的技术。一个或多个实施例可以在设备具有一个或多个或多个接口时在一些或每个分组上应用特定路由和/或转发规则。考虑过滤技术可以在模块中实现和/或不修改IP堆栈。预期的分组过滤技术可以应用于上行链路和/或下行链路中的终端以及任何网络节点。可以使用5元组，6元组和/或标签以及其他机制来创建输入分组表，以支持传入和/或传出分组过滤。

15. 发明申请

US20120032694A1 IN-PROCESS ELECTRICAL CONNECTOR 有权
标题翻译：进程电气连接器
公开(公告)号：US20120032694A1
公开(公告)日：2012-02-09
申请号：US13198256
申请日：2011-08-04
申请人： James Hinkle , Imran Khan , Modesto Sanchez , Thomas Truman
发明人： James Hinkle , Imran Khan , Modesto Sanchez , Thomas Truman
IPC分类号： G01R31/26 , H01L31/18
CPC分类号： H02S50/10 , G01R1/07342
摘要： Characteristics of partially assembled photovoltaic modules can be determined using electrical connection apparatuses and methods.
摘要翻译：可以使用电连接装置和方法来确定部分组装的光伏模块的特性。

16. 发明授权

US08110857B2 Low noise JFET 有权
标题翻译：低噪声JFET
公开(公告)号：US08110857B2
公开(公告)日：2012-02-07
申请号：US12713866
申请日：2010-02-26
申请人： Pinghai Hao , Imran Khan , Joe Trogolo
发明人： Pinghai Hao , Imran Khan , Joe Trogolo
IPC分类号： H01L29/66
CPC分类号： H01L29/8086 , H01L29/66901 , H01L29/808
摘要： A low noise (1/f) junction field effect transistor (JFET) is disclosed, wherein multiple implants push a conduction path of the transistor away from the surface of a layer upon which the transistor is formed. In this manner, current flow in the conduction path is less likely to be disturbed by defects that may exist at the surface of the layer, thereby mitigating (1/f) noise.
摘要翻译：公开了一种低噪声（1 / f）结场效应晶体管（JFET），其中多个种植体推动晶体管的导电路径离开形成晶体管的层的表面。以这种方式，导电路径中的电流不太可能受到可能存在于层的表面处的缺陷的干扰，从而减轻（1 / f）噪声。

17. 发明授权

US08040738B2 Method and apparatus for performing semiconductor memory operations 有权
标题翻译：用于执行半导体存储器操作的方法和装置
公开(公告)号：US08040738B2
公开(公告)日：2011-10-18
申请号：US12346699
申请日：2008-12-30
申请人： Hagop Nazarian , Imran Khan , Chieu-Yin Chia
发明人： Hagop Nazarian , Imran Khan , Chieu-Yin Chia
IPC分类号： G11C11/34
CPC分类号： G11C16/24 , G11C16/26 , G11C16/3454
摘要： A semiconductor memory device and a method for performing a memory operation in the semiconductor memory device are provided. The semiconductor memory device includes a plurality of predetermined memory arrays, a bitline decoder, and a controller. The controller provides the memory operation signal to the bitline decoder and, after precharging bitlines of the plurality of predetermined memory arrays, performs the memory operation on selected memory cells in the one or more of the plurality of predetermined memory arrays in accordance with the memory operation signal. The bitline decoder includes a plurality of sector select transistors and determines selected ones of the plurality of predetermined memory arrays and selected rows and unselected rows within the selected ones of the plurality of predetermined memory arrays in response to the memory operation signal. The bitline decoder also precharges the bitlines of the plurality of predetermined memory arrays to a first voltage potential then shuts off the sector select transistors of unselected ones of the plurality of predetermined memory arrays and the unselected rows of the selected ones of the plurality of predetermined memory arrays while maintaining the sector select transistors of the selected rows of the selected ones of the plurality of predetermined memory arrays at the first voltage potential prior to the controller performing the memory operation.
摘要翻译：提供半导体存储器件和用于在半导体存储器件中执行存储器操作的方法。半导体存储器件包括多个预定存储器阵列，位线解码器和控制器。控制器向位线解码器提供存储器操作信号，并且在预充电多个预定存储器阵列的位线之后，根据存储器操作对多个预定存储器阵列中的一个或多个存储器单元中的选定存储单元执行存储器操作信号。位线解码器包括多个扇区选择晶体管，并且响应于存储器操作信号确定多个预定存储器阵列中的选定的行以及多个预定存储器阵列中的选定行中的选定行和未选择的行。位线解码器还将多个预定存储器阵列的位线预先充电到第一电压电位，然后关闭多个预定存储器阵列中未选择的存储器阵列的扇区选择晶体管和多个预定存储器中的所选择的存储器的未选择的行阵列，同时在所述控制器执行所述存储器操作之前，将所述多个预定存储器阵列中的选定行的选定行的扇区选择晶体管保持在所述第一电压电位。

18. 发明授权

US07939440B2 Junction leakage suppression in memory devices 有权
标题翻译：存储器件中的结漏电抑制
公开(公告)号：US07939440B2
公开(公告)日：2011-05-10
申请号：US11152375
申请日：2005-06-15
申请人： Shibly S. Ahmed , Jun Kang , Hsiao-Han Thio , Imran Khan , Dong-Hyuk Ju , Chuan Lin
发明人： Shibly S. Ahmed , Jun Kang , Hsiao-Han Thio , Imran Khan , Dong-Hyuk Ju , Chuan Lin
IPC分类号： H01L21/425 , H01L21/44
CPC分类号： H01L29/66833 , H01L27/11521 , H01L27/11568 , H01L29/7885 , H01L29/792
摘要： A memory device includes a substrate and source and drain regions formed in the substrate. The source and drain regions include both phosphorous and arsenic and the phosphorous may be implanted prior to the arsenic. The memory device also includes a first dielectric layer formed over the substrate and a charge storage element formed over the first dielectric layer. The memory device may further include a second dielectric layer formed over the charge storage element and a control gate formed over the second dielectric layer.
摘要翻译：存储器件包括衬底和形成在衬底中的源区和漏区。源极和漏极区域包括磷和砷，并且磷可以在砷之前被植入。存储器件还包括形成在衬底上的第一电介质层和形成在第一介电层上的电荷存储元件。存储器件还可以包括形成在电荷存储元件上的第二电介质层和形成在第二介电层上的控制栅极。

19. 发明授权

US07084458B1 Semiconductor device having triple LDD structure and lower gate resistance formed with a single implant process 有权
标题翻译：半导体器件具有三重LDD结构和较低的栅极电阻，由单一的注入工艺形成
公开(公告)号：US07084458B1
公开(公告)日：2006-08-01
申请号：US11120690
申请日：2005-05-02
申请人： Imran Khan , Jianshi Wang , Yue-Song He , Jun Kang
发明人： Imran Khan , Jianshi Wang , Yue-Song He , Jun Kang
IPC分类号： H01L29/76
CPC分类号： H01L29/665 , H01L29/66598
摘要： A method of fabricating a semiconductor device having a triple LDD (lateral diffused dopants) structure is disclosed. This fabrication method requires a single implant process, leading to reduction in fabrication costs and fabrication time. Moreover, this fabrication method increases the surface area of the gate structure of the semiconductor device that is available for silicide to be formed, leading to lower gate resistance.
摘要翻译：公开了一种制造具有三重LDD（横向漫射掺杂剂）结构的半导体器件的方法。这种制造方法需要单个注入工艺，导致制造成本和制造时间的降低。此外，该制造方法增加可用于要形成的硅化物的半导体器件的栅极结构的表面积，导致较低的栅极电阻。

20. 发明授权

US06939770B1 Method of fabricating semiconductor device having triple LDD structure and lower gate resistance formed with a single implant process 失效
标题翻译：制造具有三重LDD结构的半导体器件的方法和用单个注入工艺形成的较低的栅极电阻
公开(公告)号：US06939770B1
公开(公告)日：2005-09-06
申请号：US10618514
申请日：2003-07-11
申请人： Imran Khan , Jianshi Wang , Yue-Song He , Jun Kang
发明人： Imran Khan , Jianshi Wang , Yue-Song He , Jun Kang
IPC分类号： H01L21/336
CPC分类号： H01L29/665 , H01L29/66598
摘要： A method of fabricating a semiconductor device having a triple LDD (lateral diffused dopants) structure is disclosed. This fabrication method requires a single implant process, leading to reduction in fabrication costs and fabrication time. Moreover, this fabrication method increases the surface area of the gate structure of the semiconductor device that is available for silicide to be formed, leading to lower gate resistance.
摘要翻译：公开了一种制造具有三重LDD（横向漫射掺杂剂）结构的半导体器件的方法。这种制造方法需要单个注入工艺，导致制造成本和制造时间的降低。此外，该制造方法增加可用于要形成的硅化物的半导体器件的栅极结构的表面积，导致较低的栅极电阻。

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