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    • 11. 发明授权
    • Method for high voltage power feed on differential cable pairs from a network attached power sourcing device
    • 用于从网络连接的电源装置的差分电缆对上进行高压电力馈送的方法
    • US07685452B2
    • 2010-03-23
    • US11287408
    • 2005-11-23
    • John R. CamagnaPhilip CrawleySajol Ghoshal
    • John R. CamagnaPhilip CrawleySajol Ghoshal
    • G06F1/00G06F11/30
    • H04L12/10
    • Embodiments of the present invention provide a power feed circuit operable to supply an Ethernet power signal to a coupled Ethernet network. This power feed circuit includes a number of input nodes, differential transistor pairs, active control circuits and output nodes. The input nodes receive a first power signal such as that provided by an isolated 48 volt power supply. Each transistor of the differential transistor pairs couples to one input node. These differential transistor pairs produce a second power signal which may be supplied to the Ethernet network. The active control circuits sense the second power signal passed by each transistor and are operable to apply a feedback signal to the differential transistor pairs based on the sensed power signal. At least one twisted pair couples to each differential transistor pair's output node and is operable to pass the Ethernet power signal.
    • 本发明的实施例提供了可操作以将以太网功率信号提供给耦合以太网的供电电路。 该馈电电路包括多个输入节点,差分晶体管对,有源控制电路和输出节点。 输入节点接收第一功率信号,例如由隔离的48伏特电源提供的功率信号。 差分晶体管对的每个晶体管耦合到一个输入节点。 这些差分晶体管对产生可以提供给以太网的第二功率信号。 主动控制电路感测由每个晶体管通过的第二功率信号,并且可操作以基于感测到的功率信号将反馈信号施加到差分晶体管对。 至少一对双绞线耦合到每个差分晶体管对的输出节点,并且可操作地传递以太网功率信号。
    • 12. 发明授权
    • Systems and methods operable to allow loop powering of networked devices
    • 系统和方法可操作以允许网络设备的环路供电
    • US07620825B2
    • 2009-11-17
    • US11207601
    • 2005-08-19
    • John R. CamagnaSajol GhoshalFrancois Crepin
    • John R. CamagnaSajol GhoshalFrancois Crepin
    • G06F1/26
    • G06F1/266
    • Embodiments of the present invention provide a network device operable to receive a network signal that may include both power and data from a coupled network. This network device includes a network connector and an integrated circuit. The network connector physically couples the network device to the network. An optional protection circuit may provide surge protection or incoming network signals received by the network device through the network connector. An optional switching/rectifying circuit sees the output of the protection circuit and is operable to rectify a power signal when contained within the network signal. The integrated circuit further includes a power feed circuit conductively coupled to the protection circuit and the rectifying circuit. This power feed circuit is operable to separate and pass the received data signal to a network physical layer and separate and pass the received power signal to a power management module. The power management module electrically couples to the integrated circuit but is not necessarily part of the integrated circuit. The power management module is operable to at least partially power the network device for specific circuits within the network device from the received power signal.
    • 本发明的实施例提供一种网络设备,其可操作以接收可以包括来自耦合网络的功率和数据的网络信号。 该网络设备包括网络连接器和集成电路。 网络连接器将网络设备物理耦合到网络。 可选的保护电路可以通过网络连接器提供由网络设备接收的浪涌保护或输入网络信号。 可选择的开关/整流电路看到保护电路的输出,并且可用于在包含在网络信号内时对功率信号进行整流。 集成电路还包括导电耦合到保护电路和整流电路的馈电电路。 该供电电路可操作以将接收到的数据信号分离并传递到网络物理层,并将接收到的功率信号分离并传递到电源管理模块。 电源管理模块电耦合到集成电路,但不一定是集成电路的一部分。 电源管理模块可操作以从接收的功率信号至少部分地为网络设备内的特定电路供电网络设备内的特定电路。
    • 15. 发明授权
    • Apparatus and method for performing timing recovery
    • 用于执行定时恢复的装置和方法
    • US06249557B1
    • 2001-06-19
    • US09033769
    • 1998-03-03
    • Hiroshi TakatoriStanley K. LingAmit GattaniJohn R. Camagna
    • Hiroshi TakatoriStanley K. LingAmit GattaniJohn R. Camagna
    • H04L700
    • H04L7/0058H04L7/0062H04L7/0083
    • A timing recovery circuit is disclosed that prevents phase error over-compensation. The timing recovery circuit includes a phase scanner for determining when phase error over-compensation has occurred and generating a signal for preventing dual phase compensation in response thereto thereby providing an accurate recovered clock signal. The timing recovery circuit also includes a feed-forward equalizer having a plurality of taps providing coefficients for filtering and adapting the input timing recovery circuit to an input signal. The phase scanner compares the tap coefficients to generate signal for preventing phase over-compensation by the feed-forward equalizer. A phase detector is provided for sampling coefficients from the feed-forward equalizer, error signals and output data and generating a phase signal used to generating the recovered clock signal. The signal for preventing phase over-compensation is mixed with the phase signal to generate the recovered clock signal.
    • 公开了一种防止相位误差过度补偿的定时恢复电路。 定时恢复电路包括用于确定何时发生相位误差过补偿的相位扫描器,并且响应于此产生用于防止双相补偿的信号,从而提供精确的恢复时钟信号。 定时恢复电路还包括具有多个抽头的前馈均衡器,其提供用于滤波和适配输入定时恢复电路到输入信号的系数。 相位扫描器比较抽头系数以产生用于防止前馈均衡器的相位过补偿的信号。 提供相位检测器用于从前馈均衡器,误差信号和输出数据中采样系数,并产生用于产生恢复的时钟信号的相位信号。 用于防止相位过度补偿的信号与相位信号混合以产生恢复的时钟信号。
    • 16. 发明授权
    • Method and apparatus for efficient implementation of a multirate LMS
filter
    • 用于有效实施多速率LMS滤波器的方法和装置
    • US6134570A
    • 2000-10-17
    • US75641
    • 1998-05-11
    • John R. CamagnaHiroshi TakatoriPing An
    • John R. CamagnaHiroshi TakatoriPing An
    • H03H21/00G06F17/10
    • H03H21/0012
    • An efficient implementation of a multirate filter with delayed error feedback prevents an instruction processing rate requirement from increasing by performing interpolation and decimation in a LMS filter element at the same time. The multirate filter calculates an ith coefficient value, wherein i is a set of consecutive integers, by obtaining an (i-1)th error value, obtaining an (i-1)th data value, multiplying the (i-1)th error value and the (i-1)th data value to obtain an ith coefficient product, obtaining Mth coefficient value from a coefficient register, wherein M is a predetermined integer, adding the Mth coefficient value to the ith coefficient product to obtain an ith coefficient value calculating an ith data value by multiplying the (i-1)th data value and the Mth coefficient value to produce ith convolution product, and adding an (i-1)th convolution sum to the ith convolution product to produce an ith convolution sum. Obtaining of the Mth coefficient value decimates the convolution product by M and interpolates the error value by M. Obtaining of the (i-1)th data value further includes incrementing a data register by one when new data is not written into the data register.
    • 具有延迟误差反馈的多速率滤波器的有效实现通过在LMS滤波器元件中同时执行插值和抽取来防止指令处理速率要求增加。 多速率滤波器通过获得第(i-1)个误差值来计算第i个系数值,其中i是一组连续整数,获得第(i-1)个数据值,乘以第(i-1)个误差 值和第(i-1)个数据值以获得第i个系数乘积,从系数寄存器获得Mth系数值,其中M是预定整数,将第M个系数值与第i个系数乘积相加以获得第i个系数值 通过将第(i-1)个数据值和第M个系数值相乘以产生第i个卷积积来计算第i个数据值,并将第(i-1)个卷积和加到第i个卷积乘积以产生第i个卷积和。 获取第M个系数值将卷积乘除M,并将误差值内插。(i-1)数据值的获取还包括当新数据未写入数据寄存器时将数据寄存器递增1。
    • 19. 发明授权
    • Apparatus for recovering timing of a digital signal for a transceiver
    • 用于恢复收发器的数字信号定时的装置
    • US06707868B1
    • 2004-03-16
    • US09291136
    • 1999-04-12
    • John R. CamagnaJames Ward Girardeau, Jr.Stanley K. LingHiroshi Takatori
    • John R. CamagnaJames Ward Girardeau, Jr.Stanley K. LingHiroshi Takatori
    • H04L700
    • H04L7/0058H04L25/0202H04L2025/03471
    • A digital timing recovery system wherein the rate conversion is independent of the sampling rate, and which may be set in a network mode or a remote mode. The invention includes a transceiver core for processing transmit and receive data at a predetermined baud rate, an analog front end for transmitting and receiving analog signals over a network, a phase detector for generating a phase error estimate and a timing controller for receiving the phase error estimate signal and generating a receive and transmit phase control signal for controlling timing of the analog front end. A selector is provided for selecting a remote mode of operation or a network mode of operation. The analog front end further includes a transmit converter for converting the transmit data at the baud rate to a digital output at a transmit rate and a digital to analog converter for converting the digital output to an analog signal, and an analog to digital converter for converting the analog receive signal to a digital receive signal and a receive converter for converting the digital receive signal at a receive rate to the baud rate. The phase detector includes a channel estimator for generating a coefficient error signal and the timing controller includes a loop filter for producing a control signal for a numerically controlled oscillator that produces a baud interrupt signal and the phase control signals.
    • 数字定时恢复系统,其中速率转换独立于采样速率,并且其可以被设置在网络模式或远程模式中。 本发明包括用于以预定波特率处理发送和接收数据的收发机核心,用于通过网络发送和接收模拟信号的模拟前端,用于产生相位误差估计的相位检测器和用于接收相位误差的定时控制器 估计信号并产生用于控制模拟前端的定时的接收和发送相位控制信号。 提供选择器用于选择远程操作模式或网络操作模式。 模拟前端还包括发送转换器,用于将波特率的发送数据以发送速率转换为数字输出,以及用于将数字输出转换为模拟信号的数模转换器,以及用于转换的模数转换器 到数字接收信号的模拟接收信号和用于以接收速率将数字接收信号转换成波特率的接收转换器。 相位检测器包括用于产生系数误差信号的信道估计器,并且定时控制器包括用于产生用于产生波特率中断信号和相位控制信号的数控振荡器的控制信号的环路滤波器。