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11. 发明授权

US06052328A High-speed synchronous write control scheme 失效
标题翻译：高速同步写控制方案
公开(公告)号：US06052328A
公开(公告)日：2000-04-18
申请号：US995379
申请日：1997-12-22
申请人： Luigi Ternullo, Jr. , Michael C. Stephens, Jr.
发明人： Luigi Ternullo, Jr. , Michael C. Stephens, Jr.
IPC分类号： G11C8/00 , G11C11/401
CPC分类号： G11C7/1048 , G11C11/4076 , G11C11/4091 , G11C11/4096 , G11C7/1066 , G11C7/1069 , G11C7/1072 , G11C7/1093 , G11C7/1096 , G11C7/222
摘要： The present invention provides a method and apparatus that accomplishes a high performance, random read/write SDRAM design by synchronizing the read and write operations at the data line sense amplifier. This enables the design to perform random read and write operations without varying cycle time issues or unbalanced margin issues. The data lines are used as bi-directional lines to accomplish high performance reads and writes with minimal additional wiring overhead required. During a read operation, read data is transferred from the memory cells of the device across a series of consecutive pairs of data lines to an input/output port of the memory device. The first pair of data lines is coupled to a data line sense amplifier. The additional pairs of data lines are coupled to additional amplifiers. During a read operation, data is transferred across the consecutive pairs of data lines according to the timing cycles of the respective amplifiers. In order to quickly drive the data signals during a write operation up the series of consecutive pairs of data lines, the timing signals for each of the pairs of data lines except the first pair of data lines are disabled so that the data lines are allowed to float, and then the data lines are overdriven with the write data so that the write data quickly transitions up the series of data lines to the selected data line sense amplifier, where it arrives at approximately the same time that read data normally arrives during the timing cycle for the data line sense amplifier.
摘要翻译：本发明提供一种通过使数据线读出放大器的读和写操作同步来实现高性能随机读/写SDRAM设计的方法和装置。这使得设计能够执行随机读取和写入操作，而不会改变周期时间问题或不平衡边际问题。数据线用作双向线路，以最少的附加线路开销实现高性能读写。在读取操作期间，将读取数据从设备的存储器单元跨越一系列连续的数据线对传送到存储器件的输入/输出端口。第一对数据线耦合到数据线读出放大器。附加的数据线对耦合到附加的放大器。在读取操作期间，根据相应放大器的定时周期，在连续的数据线对之间传送数据。为了在写入操作期间快速驱动数据信号，连续的一连串数据线对，除了第一对数据线之外的每对数据线的定时信号被禁用，使得数据线被允许浮动，然后数据线与写入数据过载，使得写入数据快速地将数据线系列快速转换到所选择的数据线读出放大器，其中它大约在读取数据在定时期间正常到达的时间到达周期为数据线读出放大器。

12. 发明授权

US5973895A Method and circuit for disabling a two-phase charge pump 失效
标题翻译：禁止两相电荷泵的方法和电路
公开(公告)号：US5973895A
公开(公告)日：1999-10-26
申请号：US56546
申请日：1998-04-07
申请人： Luigi Ternullo, Jr. , Jeffrey S. Earl
发明人： Luigi Ternullo, Jr. , Jeffrey S. Earl
IPC分类号： G11C5/14 , G11C8/08 , H02M3/07 , H02H7/00 , H02M3/18
CPC分类号： H02M3/07 , G11C5/145 , G11C8/08
摘要： A circuit for disabling a two-phase charge pump includes a pump select circuit and a disable control circuit. The pump select circuit is configured to select one control signal from a plurality of control signals in response to at least one select signal. The selected signal is in effect provided to the disable control circuit, which also receives a pump disable signal. A voltage sensing circuit asserts the pump disable signal when the pumped voltage reaches a predetermined maximum level. While the pump disable signal is de-asserted, the disable control circuit in effect provides the selected signal to the two-phase charge pump as a pump control signal. However, when the pump disable signal is asserted, the disable control signal latches the current logic level of the pump control signal so that the pump control signal does not transition while the pump disable signal is asserted. As a result, the two-phase charge pump is prevented from performing an extra pump cycle that would cause the pumped voltage to exceed the predetermined maximum level.
摘要翻译：用于禁用两相电荷泵的电路包括泵选择电路和禁用控制电路。泵选择电路被配置为响应于至少一个选择信号从多个控制信号中选择一个控制信号。选择的信号实际上提供给禁用控制电路，其也接收泵禁止信号。当泵浦电压达到预定的最大电平时，电压感测电路确定泵禁止信号。当泵禁用信号被取消断言时，禁用控制电路实际上将选择的信号提供给两相电荷泵作为泵控制信号。然而，当泵禁止信号被确认时，禁用控制信号锁存泵控制信号的当前逻辑电平，使得泵控制信号在泵禁能信号被断言时不转换。结果，防止两相电荷泵执行额外的泵浦循环，这将使泵送的电压超过预定的最大电平。

13. 发明授权

US5796665A Semiconductor memory device with improved read signal generation of data lines and assisted precharge to mid-level 失效
标题翻译：半导体存储器件具有改进的数据线读信号生成和辅助预充电到中级
公开(公告)号：US5796665A
公开(公告)日：1998-08-18
申请号：US958205
申请日：1997-10-17
申请人： Luigi Ternullo, Jr. , Michael C. Stephens, Jr.
发明人： Luigi Ternullo, Jr. , Michael C. Stephens, Jr.
IPC分类号： G11C7/10 , G11C13/00
CPC分类号： G11C7/1078 , G11C7/1006 , G11C7/1048 , G11C7/1051
摘要： A semiconductor memory device with a pair of data lines for reading and writing data signals to and from a matrix of memory cells and an accelerator circuit for accelerating the generation of a data signal on at least one of the data lines is disclosed. Slow signal generation on the data lines is due to the characteristics of NFET pass gates passing high signals, or PFET pass gates passing low signals. In an implementation using NFET pass gates, the accelerator circuit includes a pair of cross-coupled PFET transistors, one of which is activated by the low signal on the opposing data line. The drains of the cross-coupled PFET transistors are coupled to the data lines, such that when the low signal on the opposing data line activates one of the PFETs, it supplies additional current to the data line receiving the high signal, so as to accelerate the generation of the high signal on the data line. Faster signal generation allows for the data line latches of the circuit to be set earlier, thus allowing the read cycle of the memory device to be faster. An additional result of the increased signal generation on the data line that is receiving a high signal is that at the end of the cycle when the two data lines are coupled together, their average voltage due to charge sharing tends to be closer to a desired midlevel voltage such that less power is required to bring the two data lines to the desired mid-level voltage at the end of the signal cycle.
摘要翻译：公开了一种半导体存储器件，其具有用于将数据信号读入和写入存储器单元矩阵的一对数据线，以及用于加速至少一条数据线上的数据信号的产生的加速器电路。数据线上的慢信号产生是由于NFET通过栅极通过高信号的特性，或PFET通过门通过低信号。在使用NFET通过门的实现中，加速器电路包括一对交叉耦合的PFET晶体管，其中之一由相对数据线上的低信号激活。交叉耦合PFET晶体管的漏极耦合到数据线，使得当相对数据线上的低信号激活PFET之一时，它向接收高信号的数据线提供附加电流，以便加速在数据线上产生高信号。更快的信号产生允许更早地设置电路的数据线锁存器，从而允许存储器件的读取周期更快。在接收高信号的数据线上增加的信号产生的附加结果是在两个数据线耦合在一起的周期结束时，由于电荷共享而导致的它们的平均电压倾向于更接近于期望的中间级电压，使得在信号周期结束时需要更少的功率来使两条数据线达到期望的中间电平电压。

14. 发明授权

US5771242A Memory array built-in self-test circuit having a programmable pattern generator for allowing unique read/write operations to adjacent memory cells, and method therefor 失效
标题翻译：具有可编程模式发生器的内存自检电路的存储器阵列，用于允许对相邻存储单元的唯一的读/写操作及其方法
公开(公告)号：US5771242A
公开(公告)日：1998-06-23
申请号：US721601
申请日：1996-09-25
申请人： Robert Dean Adams , John Connor , Garrett Stephen Koch , Luigi Ternullo, Jr.
发明人： Robert Dean Adams , John Connor , Garrett Stephen Koch , Luigi Ternullo, Jr.
IPC分类号： G11C29/12 , G11C29/10 , G11C29/36 , G01R31/28
CPC分类号： G11C29/36
摘要： An ABIST circuit for testing a memory array has a blanket write subcycle (WC), an RC.sub.3 subcycle, and an RC.sub.4 subcycle. The ABIST circuit includes a programmable pattern generator that provides eight programmable data bits, eight programmable read/write bits, and two programmable address frequency bits to determine the specific test patterns applied to the memory array. The address frequency bits determine how many memory cycles will be performed on each cell of the memory array. In X1 mode, only one memory cycle is performed on each cell during any given subcycle. In X2 mode, two memory cycles are performed on each cell, allowing a cell to be written, then subsequently read in the same subcycle, In X4 mode, four memory cycles are performed on each cell, and in Xg mode, all eight bits of read/write and data are used on each cell, resulting in eight memory cycles for each cell within the memory array.
摘要翻译：用于测试存储器阵列的ABIST电路具有毯子写入子周期（WC），RC3子周期和RC4子周期。 ABIST电路包括一个可编程模式发生器，提供八个可编程数据位，八个可编程读/写位和两个可编程地址频率位，以确定应用于存储器阵列的特定测试模式。地址频率位决定在存储器阵列的每个单元上执行多少个内存周期。在X1模式下，在任何给定的子周期内，每个单元只执行一个存储周期。在X2模式下，对每个单元执行两个存储周期，允许单元被写入，然后在相同的子周期中读取。在X4模式下，对每个单元执行四个存储周期，而在Xg模式下，所有8位在每个单元上使用读/写和数据，从而为存储器阵列内的每个单元产生8个存储周期。

15. 发明授权

US5761213A Method and apparatus to determine erroneous value in memory cells using data compression 失效
标题翻译：使用数据压缩来确定存储器单元中的错误值的方法和装置
公开(公告)号：US5761213A
公开(公告)日：1998-06-02
申请号：US603963
申请日：1996-02-20
申请人： Robert Dean Adams , John Connor , Garrett Stephen Koch , Luigi Ternullo, Jr.
发明人： Robert Dean Adams , John Connor , Garrett Stephen Koch , Luigi Ternullo, Jr.
IPC分类号： G01R31/26 , G01R31/28 , G01R31/3185 , G06F7/02 , G11C29/00 , G11C29/12 , G11C29/26 , G11C29/40 , G11C29/56 , H01L21/66
CPC分类号： G11C29/26 , G01R31/318527 , G06F7/02 , G11C29/40
摘要： A method and circuit are provided to detect if any bit stored in a given location in a memory is different from the data expected. The circuit includes logic to read each of the bits stored in the cells at given locations from memory and to generate a fail signal based on the data expected to be stored if the stored data is different from the expected data. The circuit also preferably includes logic to compare the True data and expect data read from each cell and generating the fail signal if they are the same. Additional logic circuitry is also preferably provided which determines if a node of the circuit remains in a precharged condition.
摘要翻译：提供了一种方法和电路来检测存储在存储器中的给定位置中的任何位是否与预期的数据不同。该电路包括从存储器中的给定位置读取存储在单元中的每个位的逻辑，并且如果存储的数据与预期数据不同，则基于预期存储的数据生成失败信号。该电路还优选地包括用于比较True数据并期望从每个单元读取的数据的逻辑，并且如果它们相同则产生失败信号。还优选地提供额外的逻辑电路，其确定电路的节点是否保持在预充电状态。

16. 发明授权

US5535164A BIST tester for multiple memories 失效
标题翻译： BIST测试仪用于多个存储器
公开(公告)号：US5535164A
公开(公告)日：1996-07-09
申请号：US398468
申请日：1995-03-03
申请人： Robert D. Adams , John Connor , Garrett S. Koch , Stuart D. Rapoport , Luigi Ternullo, Jr.
发明人： Robert D. Adams , John Connor , Garrett S. Koch , Stuart D. Rapoport , Luigi Ternullo, Jr.
IPC分类号： G01R31/26 , G01R31/28 , G01R31/3185 , G06F7/02 , G11C29/00 , G11C29/12 , G11C29/26 , G11C29/40 , G11C29/56 , H01L21/66 , G11C7/00
CPC分类号： G11C29/26 , G01R31/318527 , G06F7/02 , G11C29/40
摘要： The present invention, provides a single BIST which can test various memories of different sizes, types and characteristics by using a state machine to select and generate all patterns required for testing all of the memories on the chip, and impressing all of the data, including expected data, and address information on all of the memories simultaneously. The BIST also generates unique (separate) control signals for the various memories and impresses these control signals on the various memories. The BIST selectively asserts the various control signals so as to apply (write) the data and to read and capture (load result) failure information only to/from those memories whose unique controls are asserted. Selective assertion of a memory's write enable signal prevents multiple writes to a location which can potentially mask cell write and leakage defects while selective assertion of a memory's load result signal is performed only when valid memory output data is expected so as not to capture false error information. The control signals instruct those memories that do not use a particular sequence of inputs or any portion of a given sequence of inputs to "ignore" such signals, thereby generating the necessary signals to form the test patterns for each and every memory, the data and address information for those patterns, the control signals to write and read each memory, and capture error information for that particular memory. Hence, a single BIST can be used to test a multiplicity of memories of different sizes and different types.
摘要翻译：本发明提供了一种可以通过使用状态机来选择和产生测试芯片上所有存储器所需的所有模式并且打印所有数据的不同尺寸，类型和特性的各种存储器，包括预期数据和所有存储器的地址信息。 BIST还为各种存储器生成独特的（单独的）控制信号，并将这些控制信号印在各种存储器上。 BIST选择性地断言各种控制信号，以便仅对从其唯一控制被断言的那些存储器应用（写入）数据和仅读取和捕获（加载结果）故障信息。存储器的写入使能信号的选择性断言防止对可能潜在地屏蔽单元写入和泄露缺陷的位置的多次写入，而只有在预期有效的存储器输出数据时执行存储器的负载结果信号的选择性断言，以便不捕获虚假错误信息。控制信号指示不使用特定输入序列或给定输入序列的任何部分的那些存储器“忽略”这样的信号，由此产生必要的信号以形成每个存储器的测试图案，数据和这些模式的地址信息，用于写入和读取每个存储器的控制信号，以及捕获该特定存储器的错误信息。因此，可以使用单个BIST来测试不同大小和不同类型的多个存储器。

17. 发明授权

US07102421B1 Dynamically adjustable on-chip supply voltage generation 失效
标题翻译：动态可调片上电源电压产生
公开(公告)号：US07102421B1
公开(公告)日：2006-09-05
申请号：US09064884
申请日：1998-04-20
申请人： Luigi Ternullo, Jr. , Michael C. Stephens, Jr.
发明人： Luigi Ternullo, Jr. , Michael C. Stephens, Jr.
IPC分类号： G05F1/10
CPC分类号： G11C5/147 , G01R31/30 , G01R31/31701 , G11C29/12 , G11C29/12005
摘要： A voltage regulation scheme for an on-chip voltage generator includes a voltage sensing circuit (VSC) and a configurable buffer circuit (CBC) to regulate the on-chip voltage generator. The CBC generates an output signal that is received by the on-chip voltage generator to activate and de-activate the voltage generator. The VSC generates a voltage level detection (VLD) signal having a voltage level that is a function of the level of the on-chip generated voltage. The CBC receives a control signal that is used to dynamically configure the chip into an operational mode, as well as the VLD signal. In response to the control signal, the switch threshold of the CBC is configured to a predetermined level corresponding to the selected operational mode. The predetermined trip point causes the CBC to appropriately activate and de-activate the on-chip voltage generator to regulate the on-chip generated voltage at the level required by the configured operational mode. One embodiment of the CBC uses a configurable pull-up circuit to alter its switch threshold or trip point. The configurable pull-up circuit is used to pull-up the voltage at an intermediate node that is buffered and propagated to the on-chip voltage generator to activate and de-activate the voltage generator. The configurable pull-up circuit more strongly pulls up this voltage in one operational mode compared to another operational mode to alter the switch threshold.
摘要翻译：用于片上电压发生器的电压调节方案包括用于调节片上电压发生器的电压感测电路（VSC）和可配置缓冲电路（CBC）。 CBC产生由片上电压发生器接收的输出信号以激活和去激活电压发生器。 VSC产生电压电平检测（VLD）信号，其具有作为片上产生电压的电平的函数的电压电平。 CBC接收用于将芯片动态地配置为操作模式的控制信号以及VLD信号。响应于控制信号，CBC的开关阈值被配置为与所选择的操作模式对应的预定电平。预定的跳闸点使得CBC适当地激活和去激活片上电压发生器，以将片上产生的电压调节在所配置的操作模式所要求的水平。 CBC的一个实施例使用可配置的上拉电路来改变其开关阈值或跳变点。可配置的上拉电路用于将缓冲并传播到片上电压发生器的中间节点处的电压上拉以激活和去激活电压发生器。与其他操作模式相比，可配置上拉电路在一个操作模式下更强大地拉高电压，以改变开关阈值。

18. 发明授权

US06353903B1 Method and apparatus for testing differential signals 失效
标题翻译：用于测试差分信号的方法和装置
公开(公告)号：US06353903B1
公开(公告)日：2002-03-05
申请号：US08330768
申请日：1994-10-28
申请人： Robert Dean Adams , John Connor , Donald Albert Evans , Luigi Ternullo, Jr.
发明人： Robert Dean Adams , John Connor , Donald Albert Evans , Luigi Ternullo, Jr.
IPC分类号： G01R3128
CPC分类号： G01R31/31926
摘要： True and complement data signals are provided to a multiplexer, which selects one of them based on a selection signal for capture by a single scannable latch in response to a clock signal. The scannable latch then provides the captured signal for testing by testing logic.
摘要翻译：真和补补数据信号被提供给多路复用器，其根据选择信号选择它们中的一个，以响应于时钟信号由单个可扫描锁存器捕获。可扫描锁存器然后提供捕获的信号，以便通过测试逻辑进行测试。

19. 发明授权

US06327215B1 Local bit switch decode circuit and method 有权
标题翻译：本地位开关解码电路及方法
公开(公告)号：US06327215B1
公开(公告)日：2001-12-04
申请号：US09670405
申请日：2000-09-28
申请人： Luigi Ternullo, Jr. , Howard C. Kirsch
发明人： Luigi Ternullo, Jr. , Howard C. Kirsch
IPC分类号： G11C800
CPC分类号： G11C7/12 , G11C7/18 , G11C11/4094 , G11C11/4097
摘要： A local bit switch selecting circuit and method for systems having a first number of banks of sense amplifiers with a second number of sense amplifiers in each sense amplifier bank. The bit switch selecting circuit and method use a single N channel field effect transistor in each sense amplifier bank. This provides bit switch selecting capability while significantly reducing the number of devices and chip area required.
摘要翻译：一种用于具有在每个读出放大器组中具有第二数量的读出放大器的第一数量的读出放大器组的系统的本地位开关选择电路和方法。位开关选择电路和方法在每个读出放大器组中使用单个N沟道场效应晶体管。这提供了位开关选择能力，同时显着减少了所需的器件数量和芯片面积。

20. 发明授权

US06133748A Crow-bar current reduction circuit 失效
标题翻译：撬棒电流降低电路
公开(公告)号：US06133748A
公开(公告)日：2000-10-17
申请号：US36726
申请日：1998-03-06
申请人： Luigi Ternullo, Jr.
发明人： Luigi Ternullo, Jr.
IPC分类号： H03K19/00 , H03K19/003 , H03K19/02
CPC分类号： H03K19/0013
摘要： A crow-bar current reduction circuit for use with a NMOS output circuit a gate voltage control circuit (GVC). The GVC receives a data signal and an output enable signal and generates control signals to drive the gates of the output transistors of the output circuit. When enabled, the GVC delays the rising edges of the gate control signals so as to help ensure that during a transition of the output signal generated by the output circuit, the NFET that was conductive before the transition is "turned off" to become non-conductive before the NFET that was non-conductive before the transition is "turned on" to become conductive. When adapted for a CMOS output circuit, the GVC delays the rising edge of the gate control signal provided to the NMOS pull-down transistor and delays the falling edge of gate control signal provided to the PMOS pull-up transistor.
摘要翻译：一种与NMOS输出电路（栅极电压控制电路（GVC））一起使用的扼流电流减小电路。 GVC接收数据信号和输出使能信号，并产生控制信号以驱动输出电路的输出晶体管的栅极。当使能时，GVC延迟栅极控制信号的上升沿，以帮助确保在输出电路产生的输出信号的转变期间，在转换之前导通的NFET被“截止” 在NFET之前导通，在转换“导通”之前导通，导通。当适用于CMOS输出电路时，GVC延迟提供给NMOS下拉晶体管的栅极控制信号的上升沿，并延迟提供给PMOS上拉晶体管的栅极控制信号的下降沿。

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