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11. 发明授权

US07552318B2 Branch lookahead prefetch for microprocessors 失效
标题翻译：用于微处理器的分支前瞻预取
公开(公告)号：US07552318B2
公开(公告)日：2009-06-23
申请号：US11016200
申请日：2004-12-17
申请人： Richard James Eickemeyer , Hung Qui Le , Dung Quoc Nguyen , Benjamin Walter Stolt , Brian William Thompto
发明人： Richard James Eickemeyer , Hung Qui Le , Dung Quoc Nguyen , Benjamin Walter Stolt , Brian William Thompto
IPC分类号： G06F9/00
CPC分类号： G06F9/3842 , G06F9/3861
摘要： A method of handling program instructions in a microprocessor which reduces delays associated with mispredicted branch instructions, by detecting the occurrence of a stall condition during execution of the program instructions, speculatively executing one or more pending instructions which include at least one branch instruction during the stall condition, and determining the validity of data utilized by the speculative execution. Dispatch logic determines the validity of the data by marking one or more registers of an instruction dispatch unit to indicate which results of the pending instructions are invalid. The speculative execution of instructions can occur across multiple pipeline stages of the microprocessor, and the validity of the data is tracked during their execution in the multiple pipeline stages while monitoring a dependency of the speculatively executed instructions relative to one another during their execution in the multiple pipeline stages.
摘要翻译：一种处理微处理器中的程序指令的方法，其通过在执行程序指令期间检测到失速状态的发生来减少与错误预测的分支指令相关联的延迟，推测性地执行一个或多个未决指令，其中包括在失速期间包括至少一个分支指令条件，并确定投机执行使用的数据的有效性。调度逻辑通过标记指令调度单元的一个或多个寄存器来指示待处理指令的哪些结果无效来确定数据的有效性。指令的推测执行可以在微处理器的多个流水线阶段发生，并且在多个流水线阶段的执行期间跟踪数据的有效性，同时在多个流水线阶段的执行期间监视推测性执行的指令相对于彼此的依赖性流水线阶段

12. 发明授权

US6061710A Multithreaded processor incorporating a thread latch register for interrupt service new pending threads 失效
标题翻译：多线程处理器并入线程锁存寄存器，用于中断服务新的挂起线程
公开(公告)号：US6061710A
公开(公告)日：2000-05-09
申请号：US960744
申请日：1997-10-29
申请人： Richard James Eickemeyer , Harold F. Kossman
发明人： Richard James Eickemeyer , Harold F. Kossman
IPC分类号： G06F9/38 , G06F9/46 , G06F9/48
CPC分类号： G06F9/4812 , G06F9/3851 , G06F9/3885 , G06F9/461
摘要： A method of using multithreading resources for improving handling instructions is operated by an improved multithreaded processor which includes a context select logic unit being arranged and configured for receiving and responding an interrupt including: a first controller for setting a pending thread latch when a hardware context is not available for executing a new thread for servicing the interrupt.
摘要翻译：一种使用多线程资源来改善处理指令的方法由改进的多线程处理器来操作，该处理器包括配置和配置用于接收和响应中断的上下文选择逻辑单元，包括：第一控制器，用于当硬件上下文为不可用于执行中断服务的新线程。

13. 发明授权

US5940877A Cache address generation with and without carry-in 失效
标题翻译：具有和不带有进位的缓存地址生成
公开(公告)号：US5940877A
公开(公告)日：1999-08-17
申请号：US873783
申请日：1997-06-12
申请人： Richard James Eickemeyer , Thomas Leo Jeremiah
发明人： Richard James Eickemeyer , Thomas Leo Jeremiah
IPC分类号： G06F12/08 , G06F12/10 , G06F13/00
CPC分类号： G06F12/0864 , G06F12/1054 , G06F2212/6082
摘要： A cache system provides for accessing set associative caches with no increase in critical path delay, for reducing the latency penalty for cache accesses, for reducing snoop busy time, and for responding to MRU misses and cache misses. The cache array is accessed by multiplexing two most-recently-used (MRU) arrays which are addressed and accessed substantially in parallel with effective address generation, the outputs of which MRU arrays are generated, one by assuming a carryin of zero, and the other by assuming a carryin of one to the least significant bit of the portion of the effective addressed used to access the MRU arrays. The hit rate in the MRU array is improved by hashing within an adder the adder's input operands with predetermined additional operand bits.
摘要翻译：缓存系统提供访问集合关联缓存，而不增加关键路径延迟，以减少高速缓存访问的延迟损失，减少侦听占线时间，以及响应MRU未命中和高速缓存未命中。通过复用两个最近使用的（MRU）阵列来访问高速缓存阵列，其基本上与生成有效地址的MRU阵列的输出相平行地寻址和访问，其中一个通过假定为零，另一个通过假设一个进位到用于访问MRU阵列的有效寻址部分的最低有效位。 MRU阵列中的命中率通过加法器中的加法器的加法器的输入操作数与预定的附加操作数位进行散列得到改善。

14. 发明授权

US08140829B2 Multithreaded processor and method for switching threads by swapping instructions between buffers while pausing execution 失效
标题翻译：多线程处理器和通过在暂停执行时在缓冲器之间交换指令来切换线程的方法
公开(公告)号：US08140829B2
公开(公告)日：2012-03-20
申请号：US10717747
申请日：2003-11-20
申请人： Richard James Eickemeyer , David Arnold Luick
发明人： Richard James Eickemeyer , David Arnold Luick
IPC分类号： G06F9/30 , G06F9/40 , G06F7/38 , G06F9/00 , G06F9/44
CPC分类号： G06F9/4843 , G06F9/3851
摘要： A processor includes primary threads of execution that may simultaneously issue instructions, and one or more backup threads. When a primary thread stalls, the contents of its instruction buffer may be switched with the instruction buffer for a backup thread, thereby allowing the backup thread to begin execution. This design allows two primary threads to issue simultaneously, which allows for overlap of instruction pipeline latencies. This design further allows a fast switch to a backup thread when a primary thread stalls, thereby providing significantly improved throughput in executing instructions by the processor.
摘要翻译：处理器包括可以同时发出指令的主执行线程以及一个或多个备用线程。当主线程停顿时，其指令缓冲器的内容可以用备用线程的指令缓冲器切换，从而允许备份线程开始执行。此设计允许两个主线程同时发出，这允许指令管线延迟的重叠。该设计还允许在主线程停止时快速切换到备用线程，从而在由处理器执行指令时提供显着提高的吞吐量。

15. 发明申请

US20090249349A1 Power-Efficient Thread Priority Enablement 有权
标题翻译：高效的线程优先级启用
公开(公告)号：US20090249349A1
公开(公告)日：2009-10-01
申请号：US12059576
申请日：2008-03-31
申请人： Pradip Bose , Alper Buyuktosunoglu , Richard James Eickemeyer , Susan Elizabeth Eisen , Michael Stephen Floyd , Hans Mikael Jacobson , Jeffrey R. Summers
发明人： Pradip Bose , Alper Buyuktosunoglu , Richard James Eickemeyer , Susan Elizabeth Eisen , Michael Stephen Floyd , Hans Mikael Jacobson , Jeffrey R. Summers
IPC分类号： G06F9/46
CPC分类号： G06F9/4893 , Y02D10/24
摘要： A mechanism for controlling instruction fetch and dispatch thread priority settings in a thread switch control register for reducing the occurrence of balance flushes and dispatch flushes for increased power performance of a simultaneous multi-threading data processing system. To achieve a target power efficiency mode of a processor, the illustrative embodiments receive an instruction or command from a higher-level system control to set a current power consumption of the processor. The illustrative embodiments determine a target power efficiency mode for the processor. Once the target power mode is determined, the illustrative embodiments update thread priority settings in a thread switch control register for an executing thread to control balance flush speculation and dispatch flush speculation to achieve the target power efficiency mode.
摘要翻译：一种用于控制在线程切换控制寄存器中的指令获取和调度线程优先级设置的机制，用于减少平衡刷新的发生和调度刷新以提高同时多线程数据处理系统的功率性能。为了实现处理器的目标功率效率模式，说明性实施例从较高级系统控制器接收指令或命令以设置处理器的当前功耗。说明性实施例确定了处理器的目标功率效率模式。一旦确定了目标功率模式，则说明性实施例更新用于执行线程的线程切换控制寄存器中的线程优先级设置，以控制平衡冲突推测和调度冲销推测以实现目标功率效率模式。

16. 发明授权

US07594096B2 Load lookahead prefetch for microprocessors 有权
标题翻译：加载微处理器的前瞻预取
公开(公告)号：US07594096B2
公开(公告)日：2009-09-22
申请号：US11950495
申请日：2007-12-05
申请人： Richard James Eickemeyer , Hung Qui Le , Dung Quoc Nguyen , Benjamin Walter Stolt , Brian William Thompto
发明人： Richard James Eickemeyer , Hung Qui Le , Dung Quoc Nguyen , Benjamin Walter Stolt , Brian William Thompto
IPC分类号： G06F9/30 , G06F9/40 , G06F15/00
CPC分类号： G06F9/3842 , G06F9/3804 , G06F9/383 , G06F9/3838 , G06F9/3851
摘要： The present invention allows a microprocessor to identify and speculatively execute future load instructions during a stall condition. This allows forward progress to be made through the instruction stream during the stall condition which would otherwise cause the microprocessor or thread of execution to be idle. The data for such future load instructions can be prefetched from a distant cache or main memory such that when the load instruction is re-executed (non speculative executed) after the stall condition expires, its data will reside either in the L1 cache, or will be enroute to the processor, resulting in a reduced execution latency. When an extended stall condition is detected, load lookahead prefetch is started allowing speculative execution of instructions that would normally have been stalled. In this speculative mode, instruction operands may be invalid due to source loads that miss the L1 cache, facilities not available in speculative execution mode, or due to speculative instruction results that are not available via forwarding and are not written to the architected registers. A set of status bits are used to dynamically keep track of the dependencies between instructions in the pipeline and a bit vector tracks invalid architected facilities with respect to the speculative instruction stream. Both sources of information are used to identify load instructions with valid operands for calculating the load address. If the operands are valid, then a load prefetch operation is started to retrieve data from the cache ahead of time such that it can be available for the load instruction when it is non-speculatively executed.
摘要翻译：本发明允许微处理器在失速状态期间识别并推测性地执行未来的加载指令。这允许在停顿条件期间通过指令流进行正向进展，否则将导致微处理器或执行线程空闲。可以从远程高速缓存或主存储器预取这样的未来加载指令的数据，使得当停止条件到期之后，当加载指令被重新执行（不推测执行）时，其数据将驻留在L1高速缓存中，或者将进入处理器，导致执行时间缩短。当检测到扩展失速条件时，启动加载前瞻预取，允许推测执行通常已经停止的指令。在这种推测模式中，由于缺少L1高速缓存的源负载，设备在推测执行模式下不可用的设备，或由于不能通过转发而不能使用并且未写入到架构化寄存器的推测性指令结果，指令操作数可能无效。一组状态位用于动态地跟踪流水线中的指令之间的依赖关系，并且位向量相对于推测性指令流跟踪无效的架构设施。两个信息来源用于识别加载指令，其中包含用于计算加载地址的有效操作数。如果操作数有效，则启动加载预取操作以提前从高速缓存中检索数据，使得当非推测性地执行加载指令时，可以对加载指令可用。

17. 发明授权

US07444498B2 Load lookahead prefetch for microprocessors 失效
标题翻译：加载微处理器的前瞻预取
公开(公告)号：US07444498B2
公开(公告)日：2008-10-28
申请号：US11016236
申请日：2004-12-17
申请人： Richard James Eickemeyer , Hung Qui Le , Dung Quoc Nguyen , Benjamin Walter Stolt , Brian William Thompto
发明人： Richard James Eickemeyer , Hung Qui Le , Dung Quoc Nguyen , Benjamin Walter Stolt , Brian William Thompto
IPC分类号： G06F9/30 , G06F9/40 , G06F15/00 , G06F7/38 , G06F9/00 , G06F9/44 , G06F7/00
CPC分类号： G06F9/3842 , G06F9/3804 , G06F9/383 , G06F9/3838 , G06F9/3851
摘要： The present invention allows a microprocessor to identify and speculatively execute future load instructions during a stall condition. This allows forward progress to be made through the instruction stream during the stall condition which would otherwise cause the microprocessor or thread of execution to be idle. The data for such future load instructions can be prefetched from a distant cache or main memory such that when the load instruction is re-executed (non speculative executed) after the stall condition expires, its data will reside either in the L1 cache, or will be enroute to the processor, resulting in a reduced execution latency. When an extended stall condition is detected, load lookahead prefetch is started allowing speculative execution of instructions that would normally have been stalled. In this speculative mode, instruction operands may be invalid due to source loads that miss the L1 cache, facilities not available in speculative execution mode, or due to speculative instruction results that are not available via forwarding and are not written to the architected registers. A set of status bits are used to dynamically keep track of the dependencies between instructions in the pipeline and a bit vector tracks invalid architected facilities with respect to the speculative instruction stream. Both sources of information are used to identify load instructions with valid operands for calculating the load address. If the operands are valid, then a load prefetch operation is started to retrieve data from the cache ahead of time such that it can be available for the load instruction when it is non-speculatively executed.
摘要翻译：本发明允许微处理器在失速状态期间识别并推测性地执行未来的加载指令。这允许在停顿条件期间通过指令流进行正向进展，否则将导致微处理器或执行线程空闲。可以从远程高速缓存或主存储器预取这样的未来加载指令的数据，使得当停止条件到期之后，当加载指令被重新执行（不推测执行）时，其数据将驻留在L1高速缓存中，或者将进入处理器，导致执行时间缩短。当检测到扩展失速条件时，启动加载前瞻预取，允许推测执行通常已经停止的指令。在这种推测模式中，由于缺少L1高速缓存的源负载，设备在推测执行模式下不可用的设备，或由于不能通过转发而不能使用并且未写入到架构化寄存器的推测性指令结果，指令操作数可能无效。一组状态位用于动态地跟踪流水线中的指令之间的依赖关系，并且位向量相对于推测性指令流跟踪无效的架构设施。两个信息来源用于识别加载指令，其中包含用于计算加载地址的有效操作数。如果操作数有效，则启动加载预取操作以提前从高速缓存中检索数据，使得当非推测性地执行加载指令时，可以对加载指令可用。

18. 发明申请

US20080250230A1 Using a Modified Value GPR to Enhance Lookahead Prefetch 失效
标题翻译：使用修改值GPR来增强前瞻预取
公开(公告)号：US20080250230A1
公开(公告)日：2008-10-09
申请号：US12061290
申请日：2008-04-02
申请人： Richard James Eickemeyer , Hung Qui Le , Dung Quoc Nguyen , Benjamin Walter Stolt , Brian William Thompto
发明人： Richard James Eickemeyer , Hung Qui Le , Dung Quoc Nguyen , Benjamin Walter Stolt , Brian William Thompto
IPC分类号： G06F9/30
CPC分类号： G06F9/3842 , G06F9/3804 , G06F9/383 , G06F9/3838
摘要： The present invention allows a microprocessor to identify and speculatively execute future instructions during a stall condition. This allows forward progress to be made through the instruction stream during the stall condition which would otherwise cause the microprocessor or thread of execution to be idle. The execution of such future instructions can initiate a prefetch of data or instructions from a distant cache or main memory, or otherwise make forward progress through the instruction stream. In this manner, when the instructions are re-executed (non speculatively executed) after the stall condition expires, they will execute with a reduced execution latency; e.g. by accessing data prefetched into the L1 cache, or enroute to the processor, or by executing the target instructions following a speculatively resolved mispredicted branch. In speculative mode, instruction operands may be invalid due to source loads that miss the L1 cache, facilities not available in speculative execution mode, or due to speculative instruction results that are not available. Dependency and dirty (i.e. invalid result) bits are tracked and used to determine which speculative instructions are valid for execution. A modified value register storage and bit vector are used to improve the availability of speculative results that would otherwise be discarded once they leave the execution pipeline because they cannot be written to the architected registers. The modified general purpose registers are used to store speculative results when the corresponding instruction reaches writeback and the modified bit vector tracks the results that have been stored there. Younger speculative instructions that do not bypass directly from older instructions will then use this modified data when the corresponding bit in the modified bit vector indicates the data has been modified. Otherwise, data from the architected registers will be used.
摘要翻译：本发明允许微处理器在失速状态期间识别和推测地执行未来的指令。这允许在停顿条件期间通过指令流进行正向进展，否则将导致微处理器或执行线程空闲。这样的未来指令的执行可以启动来自远程高速缓存或主存储器的数据或指令的预取，或以其他方式通过指令流进行进展。以这种方式，当在停止条件到期之后重新执行（不推测地执行）指令时，它们将以降低的执行延迟执行; 例如通过访问预取到L1高速缓存中的数据，或者进入处理器，或通过在推测性地解决的误预测分支之后执行目标指令。在推测模式中，由于缺少L1缓存的源加载，在推测执行模式下不可用的设备，或由于不可用的推测指令结果，指令操作数可能无效。跟踪依赖关系和脏（即无效结果）位，并用于确定哪些推测指令对执行有效。改进的值寄存器存储和位向量被用于提高推测结果的可用性，否则，由于不能将其写入到架构化的寄存器，否则将抛弃执行流水线。修改后的通用寄存器用于在对应指令到达回写时存储推测结果，修改后的位向量跟踪存储在其中的结果。当修改的位向量中的相应位指示数据已被修改时，不直接从旧指令旁路的较小的推测指令将使用该修改的数据。否则，将使用来自架构化寄存器的数据。

19. 发明授权

US06988186B2 Shared resource queue for simultaneous multithreading processing wherein entries allocated to different threads are capable of being interspersed among each other and a head pointer for one thread is capable of wrapping around its own tail in order to access a free entry 失效
标题翻译：用于同时多线程处理的共享资源队列，其中分配给不同线程的条目能够彼此散布，并且用于一个线程的头指针能够围绕其自己的尾部包围以访问空闲条目
公开(公告)号：US06988186B2
公开(公告)日：2006-01-17
申请号：US09894260
申请日：2001-06-28
申请人： Richard James Eickemeyer , Steven R. Kunkel , Hung Q Le
发明人： Richard James Eickemeyer , Steven R. Kunkel , Hung Q Le
IPC分类号： G06F15/167
CPC分类号： G06F9/3814 , G06F9/3802 , G06F9/3851
摘要： A queue, such as a first-in first-out queue, is incorporated into a processing device, such as a multithreaded pipeline processor. The queue may store the resources of more than one thread in the processing device such that the entries of one thread may be interspersed among the entries of another thread. The entries of each thread may be identified by a thread identification, a valid marker to indicate if the resources within the entry are valid, and a bank number. For a particular thread, the bank number tracks the number of times a head pointer pertaining to the first entry has passed a tail pointer. In this fashion, empty entries may be used and the resources may be efficiently allocated. In a preferred embodiment, the shared resource queue may be implemented into an in-order multithreaded pipelined processor as a queue storing resources to be dispatched for execution of instructions. The shared resource queue may also be implemented into a branch information queue or into any queue where more than one thread may require dynamic registers.
摘要翻译：诸如先进先出队列的队列被并入处理设备中，诸如多线程流水线处理器。队列可以将多个线程的资源存储在处理设备中，使得一个线程的条目可以分散在另一线程的条目中。每个线程的条目可以通过线程标识，用于指示条目中的资源是否有效的有效标记以及一个银行号码来标识。对于特定线程，存储体号跟踪与第一条目有关的头指针已经通过尾指针的次数。以这种方式，可以使用空条目并且可以有效地分配资源。在优选实施例中，共享资源队列可以被实现为按顺序的多线程流水线处理器作为存储要被分派用于执行指令的资源的队列。共享资源队列也可以被实现到分支信息队列或任何队列中，其中多于一个线程可能需要动态寄存器。

20. 发明授权

US5652774A Method and apparatus for decreasing the cycle times of a data processing system 失效
标题翻译：减少数据处理系统的循环时间的方法和装置
公开(公告)号：US5652774A
公开(公告)日：1997-07-29
申请号：US676747
申请日：1996-07-08
申请人： Richard James Eickemeyer , Nadeem Malik , Avijit Saha , Charles Gorham Ward
发明人： Richard James Eickemeyer , Nadeem Malik , Avijit Saha , Charles Gorham Ward
IPC分类号： G06F9/312 , G06F9/38 , G09G3/02
CPC分类号： G06F9/30043 , G06F9/3824 , G06F9/384
摘要： A method and apparatus for reducing the number of cycles required to implement load instructions in a data processing system having a Central Processing Unit (CPU). The CPU includes a rename register file that can be used in whole or in part for retaining cache lines from previously executed load instructions. The rename register file is then used by subsequent instructions (e.g. load instructions) requiring the data previously loaded therein. Thus, reducing the cycles normally associated with retrieving the data from the cache for the subsequent instructions.
摘要翻译：一种用于减少在具有中央处理单元（CPU）的数据处理系统中实现加载指令所需的周期数的方法和装置。 CPU包括重命名寄存器文件，可以全部或部分地用于从先前执行的加载指令中保留高速缓存行。重命名寄存器文件然后由后续指令（例如加载指令）用于需要先前加载的数据。因此，减少通常与随后的指令从高速缓存检索数据相关联的周期。

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