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11. 发明授权

US07091763B1 Clock generation 有权
标题翻译：时钟生成
公开(公告)号：US07091763B1
公开(公告)日：2006-08-15
申请号：US10701005
申请日：2003-11-03
申请人： Phillip Johnson , William Andrews , Fulong Zhang , Gary Powell
发明人： Phillip Johnson , William Andrews , Fulong Zhang , Gary Powell
IPC分类号： H03K3/17
CPC分类号： H03K5/1565 , G06F1/10 , H03L7/07
摘要： Clock generation techniques are disclosed to provide clock generation with duty cycle replication. The clock generation techniques may further compensate for clock insertion delays and minimize distortion due to clock distribution networks.
摘要翻译：时钟生成技术被公开以提供占空比复制的时钟生成。时钟产生技术可以进一步补偿时钟插入延迟并且最小化由于时钟分配网络引起的失真。

12. 发明授权

US06903574B2 Memory access via serial memory interface 有权
标题翻译：通过串行存储器接口进行存储器访问
公开(公告)号：US06903574B2
公开(公告)日：2005-06-07
申请号：US10629512
申请日：2003-07-29
申请人： Zheng (Jeff) Chen , Fulong Zhang , Harold Scholz
发明人： Zheng (Jeff) Chen , Fulong Zhang , Harold Scholz
IPC分类号： G11C5/06 , H03K19/177
CPC分类号： H03K19/17756 , G11C5/066 , H03K19/1776
摘要： Systems and methods are disclosed herein to provide access to memory cells within a programmable logic device. For example, in accordance with an embodiment of the present invention, a serial memory interface is associated with each special functional block within a programmable logic device to provide access to configuration memory cells of the special functional block.
摘要翻译：本文公开的系统和方法提供对可编程逻辑器件内的存储器单元的访问。例如，根据本发明的实施例，串行存储器接口与可编程逻辑器件内的每个特殊功能块相关联，以提供对特殊功能块的配置存储器单元的访问。

13. 发明授权

US08912933B1 Serializer with multiple stages 有权
标题翻译：具有多个阶段的串行器
公开(公告)号：US08912933B1
公开(公告)日：2014-12-16
申请号：US13616173
申请日：2012-09-14
申请人： Fulong Zhang , Ling Wang , John Schadt
发明人： Fulong Zhang , Ling Wang , John Schadt
IPC分类号： H03M9/00
CPC分类号： H03M9/00
摘要： In certain embodiments of the invention, a serializer has a transfer stage that transfers N-bit parallel data from a relatively slow timing domain to a relatively fast timing domain and a serializing stage that converts the parallel data into serialized data. Between the transfer stage and the serializing stage is an update stage that buffers the data and can be used to toggle the serializer between an N−1 operating mode and an N+1 operating mode.
摘要翻译：在本发明的某些实施例中，串行器具有将N位并行数据从相对较慢的定时域传送到相对较快的定时域的传送级，以及将并行数据转换成串行数据的串行级。在传送级和序列化级之间是缓存数据并可用于在N-1操作模式和N + 1操作模式之间切换串行器的更新阶段。

14. 发明授权

US07573770B1 Distributed front-end FIFO for source-synchronized interfaces with non-continuous clocks 有权
标题翻译：分布式前端FIFO，用于具有非连续时钟的源同步接口
公开(公告)号：US07573770B1
公开(公告)日：2009-08-11
申请号：US11778457
申请日：2007-07-16
申请人： Fulong Zhang , Harold Scholz , Larry Fenstermaker , John Schadt
发明人： Fulong Zhang , Harold Scholz , Larry Fenstermaker , John Schadt
IPC分类号： G11C7/00
CPC分类号： G06F5/06
摘要： In one embodiment of the invention, an integrated circuit, such as an FPGA, comprises a distributed FIFO architecture that supports data transfer from an external device, such as an SDRAM, via an interface that receives a non-continuous, asynchronous strobe clock and a data lane having a plurality of bit lines from the external device. The distributed FIFO architecture comprise a FIFO for each bit line and a FIFO controller. Under control of the FIFO controller, data is written into each FIFO using a FIFO write clock based on the strobe clock, while data is read out from each FIFO using a FIFO read clock based on a local reference clock of the integrated circuit. The distributed FIFO architecture is designed to handle a range of possible phase differences between the FIFO write and read clocks to safely convert from the asynchronous, non-continuous strobe domain to a local continuous clock domain.
摘要翻译：在本发明的一个实施例中，诸如FPGA的集成电路包括分布式FIFO架构，其支持诸如SDRAM的外部设备的数据传输，所述接口接收非连续异步选通时钟和数据通道具有来自外部设备的多个位线。分布式FIFO架构包括用于每个位线的FIFO和FIFO控制器。在FIFO控制器的控制下，使用基于选通时钟的FIFO写时钟将数据写入每个FIFO，而使用基于集成电路的本地参考时钟的FIFO读时钟从每个FIFO读出数据。分布式FIFO架构旨在处理FIFO写入和读取时钟之间可能的相位差范围，以安全地将异步非连续选通域转换为本地连续时钟域。

15. 发明申请

US20070136619A1 Jitter tolerant delay-locked loop circuit 有权
标题翻译：抖动容限延迟锁定环路
公开(公告)号：US20070136619A1
公开(公告)日：2007-06-14
申请号：US11302097
申请日：2005-12-13
申请人： Zheng (Jeff) Chen , Phillip Johnson , Fulong Zhang
发明人： Zheng (Jeff) Chen , Phillip Johnson , Fulong Zhang
IPC分类号： G06F1/00
CPC分类号： G06F1/04 , G06F1/12
摘要： Systems and methods are disclosed herein to provide improved jitter tolerant delay-locked loop circuitry. For example, in accordance with an embodiment of the present invention, an integrated circuit includes a plurality of delay cells each having a plurality of programmable delay taps. Each delay cell is adapted to provide a delayed clock signal delayed by a selected number of the delay taps. A phase detector is adapted to compare a first clock signal with a selected one of the delayed clock signals to obtain a comparison result and provide a plurality of control signals in response to the comparison result. An arithmetic logic unit (ALU) is adapted to vary the selected number of delay taps in response to the control signals provided by the phase detector.
摘要翻译：本文公开了系统和方法以提供改进的抖动容限延迟锁定环路。例如，根据本发明的实施例，集成电路包括多个延迟单元，每个延迟单元具有多个可编程延迟抽头。每个延迟单元适于提供延迟选定数量的延迟抽头的延迟时钟信号。相位检测器适于将第一时钟信号与所选延迟时钟信号中的一个进行比较，以获得比较结果，并响应于比较结果提供多个控制信号。算术逻辑单元（ALU）适于响应于由相位检测器提供的控制信号来改变选定数量的延迟抽头。

16. 发明申请

US20050024085A1 Memory access via serial memory interface 有权
公开(公告)号：US20050024085A1
公开(公告)日：2005-02-03
申请号：US10629512
申请日：2003-07-29
申请人： Zheng (Jeff) Chen , Fulong Zhang , Harold Scholz
发明人： Zheng (Jeff) Chen , Fulong Zhang , Harold Scholz
IPC分类号： G11C5/06 , H03K19/177
CPC分类号： H03K19/17756 , G11C5/066 , H03K19/1776
摘要： Systems and methods are disclosed herein to provide access to memory cells within a programmable logic device. For example, in accordance with an embodiment of the present invention, a serial memory interface is associated with each special functional block within a programmable logic device to provide access to configuration memory cells of the special functional block.

17. 发明授权

US07620839B2 Jitter tolerant delay-locked loop circuit 有权
标题翻译：抖动容限延迟锁定环路
公开(公告)号：US07620839B2
公开(公告)日：2009-11-17
申请号：US11302097
申请日：2005-12-13
申请人： Zheng (Jeff) Chen , Phillip Johnson , Fulong Zhang
发明人： Zheng (Jeff) Chen , Phillip Johnson , Fulong Zhang
IPC分类号： G06F1/04
CPC分类号： G06F1/04 , G06F1/12
摘要： Systems and methods are disclosed herein to provide improved jitter tolerant delay-locked loop circuitry. For example, in accordance with an embodiment of the present invention, an integrated circuit includes a plurality of delay cells each having a plurality of programmable delay taps. Each delay cell is adapted to provide a delayed clock signal delayed by a selected number of the delay taps. A phase detector is adapted to compare a first clock signal with a selected one of the delayed clock signals to obtain a comparison result and provide a plurality of control signals in response to the comparison result. An arithmetic logic unit (ALU) is adapted to vary the selected number of delay taps in response to the control signals provided by the phase detector.
摘要翻译：本文公开了系统和方法以提供改进的抖动容限延迟锁定环路。例如，根据本发明的实施例，集成电路包括多个延迟单元，每个延迟单元具有多个可编程延迟抽头。每个延迟单元适于提供延迟选定数量的延迟抽头的延迟时钟信号。相位检测器适于将第一时钟信号与所选延迟时钟信号中的一个进行比较，以获得比较结果，并响应于比较结果提供多个控制信号。算术逻辑单元（ALU）适于响应于由相位检测器提供的控制信号来改变选定数量的延迟抽头。

18. 发明申请

US20070109880A1 Digital I/O timing control 有权
标题翻译：数字I / O定时控制
公开(公告)号：US20070109880A1
公开(公告)日：2007-05-17
申请号：US11281651
申请日：2005-11-17
申请人： Fulong Zhang , Harold Scholz
发明人： Fulong Zhang , Harold Scholz
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G11C7/222
摘要： When certain digital circuit devices receive data bus signals, I/O interfaces need to sample the data signals during a time when these signals are both valid and stable. Typically, the data signals are sampled at a time corresponding to a point halfway between rising and falling edges of a reference clock signal associated with the data bus, which sampling time corresponds to a 90-degree phase shift of the reference clock signal. In one embodiment of the invention, a delay count generator determines a delay value corresponding to a quarter cycle (i.e., 90 degrees) of the reference clock signal. In making this determination, a counter counts the number of clock cycles of an internally generated, relatively high-frequency clock signal, where the number corresponds to a specified portion (e.g., one half) of a period of a divided-down version of the reference clock signal. That number can then be used to generate the 90-degree delay value.
摘要翻译：当某些数字电路设备接收数据总线信号时，I / O接口需要在这些信号有效和稳定的时间内采样数据信号。通常，数据信号在对应于与数据总线相关联的参考时钟信号的上升沿和下降沿之间的点相对应的时间被采样，该采样时间对应于参考时钟信号的90度相移。在本发明的一个实施例中，延迟计数发生器确定对应于参考时钟信号的四分之一周期（即，90度）的延迟值。在进行该确定时，计数器对内部产生的相对高频时钟信号的时钟周期数进行计数，其中数字对应于分割版本的时间段的指定部分（例如，一半）参考时钟信号。然后可以使用该数字来产生90度延迟值。

19. 发明授权

US08274412B1 Serializer with odd gearing ratio 有权
标题翻译：具有奇数传动比的串行器
公开(公告)号：US08274412B1
公开(公告)日：2012-09-25
申请号：US12987393
申请日：2011-01-10
申请人： Fulong Zhang , Ling Wang , John Schadt
发明人： Fulong Zhang , Ling Wang , John Schadt
IPC分类号： H03M9/00
CPC分类号： H03M9/00
摘要： In certain embodiments of the invention, a serializer has (a) an initial, transfer stage that transfers incoming parallel data from a relatively slow timing domain to a relatively fast timing domain and (b) a final, serializing stage that converts the parallel data into serialized data. Between the transfer stage and the serializing stage is an update stage that (i) buffers data between the initial and final stages and (ii) can be used to toggle the serializer between an N−1 operating mode (that serializes (N−1) bits of parallel data) and an N+1 operating mode (that serializes (N+1) bits of parallel data) to achieve a net N:1 gearing ratio where N is an odd integer. The serializer can be configurable to support other gearing ratios as well.
摘要翻译：在本发明的某些实施例中，串行器具有（a）初始传送级，其将输入的并行数据从相对较慢的定时域传送到相对较快的定时域，以及（b）将并行数据转换成序列化数据。在转移阶段和序列化阶段之间是更新阶段，（i）缓冲初始阶段和最后阶段之间的数据，（ii）可用于在N-1操作模式（序列化（N-1）并行数据的位）和N + 1工作模式（串行化并行数据的（N + 1）位），以实现净N：1的传动比，其中N是奇整数。串行器可以配置为支持其他传动比。

20. 发明授权

US07863931B1 Flexible delay cell architecture 有权
标题翻译：灵活的延迟单元架构
公开(公告)号：US07863931B1
公开(公告)日：2011-01-04
申请号：US11939787
申请日：2007-11-14
申请人： Fulong Zhang , Zhen Chen , William Andrews , Barry Britton
发明人： Fulong Zhang , Zhen Chen , William Andrews , Barry Britton
IPC分类号： H03K19/177 , H03K19/00
CPC分类号： H03K19/17744
摘要： A flexible delay cell architecture and related methods are provided that may be used, for example, with input/output (I/O) blocks of a programmable logic device (PLD). In one implementation, a PLD includes a delay cell comprising a plurality of delay elements. The delay elements are adapted to delay an input signal to provide an output signal according to a delay setting corresponding to a number of the delay elements. The PLD also includes a register adapted to store the delay setting. The PLD further includes an edge monitor adapted to signal whether an edge transition of the output signal has occurred during a time window. In addition, the PLD includes logic adapted to adjust the delay setting stored by the register in response to the edge monitor signaling the edge transition.
摘要翻译：提供了可用于例如可编程逻辑器件（PLD）的输入/输出（I / O）块的灵活的延迟单元架构和相关方法。在一个实现中，PLD包括包括多个延迟元件的延迟单元。延迟元件适于延迟输入信号以根据对应于多个延迟元件的延迟设置提供输出信号。 PLD还包括适用于存储延迟设置的寄存器。 PLD还包括边缘监视器，适用于在时间窗口内发出信号是否发生了输出信号的边沿转换。此外，PLD包括适于调整由寄存器存储的延迟设置的逻辑，响应于边缘监视器发出边沿转换信号。

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