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11. 发明申请

US20080153278A1 Doped Single Crystal Silicon Silicided eFuse 有权
标题翻译：掺杂单晶硅硅胶eFuse
公开(公告)号：US20080153278A1
公开(公告)日：2008-06-26
申请号：US12043226
申请日：2008-03-06
申请人： Edward J. Nowak , Jed H. Rankin , William R. Tonti , Richard Q. Williams
发明人： Edward J. Nowak , Jed H. Rankin , William R. Tonti , Richard Q. Williams
IPC分类号： H01L21/84
CPC分类号： H01L27/10 , H01L23/5256 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An eFuse begins with a single crystal silicon-on-insulator (SOI) structure that has a single crystal silicon layer on a first insulator layer. The single crystal silicon layer is patterned into a strip. Before or after the patterning, the single crystal silicon layer is doped with one or more impurities. At least an upper portion of the single crystal silicon layer is then silicided to form a silicided strip. In one embodiment the entire single crystal silicon strip is silicided to create a silicide strip. Second insulator(s) is/are formed on the silicide strip, so as to isolate the silicided strip from surrounding structures. Before or after forming the second insulators, the method forms electrical contacts through the second insulators to ends of the silicided strip. By utilizing a single crystal silicon strip, any form of semiconductor, such as a diode, conductor, insulator, transistor, etc. can form the underlying portion of the fuse structure. The overlying silicide material allows the fuse to act as a conductor in its unprogrammed state. However, contrary to metal or polysilicon based eFuses which only comprise an insulator in the programmed state, when the inventive eFuse is programmed (and the silicide is moved or broken) the underlying semiconductor structure operates as an active semiconductor device.
摘要翻译： eFuse从在第一绝缘体层上具有单晶硅层的单晶硅绝缘体（SOI）结构开始。将单晶硅层图案化成条带。在构图之前或之后，单晶硅层掺杂有一种或多种杂质。至少单晶硅层的上部然后被硅化以形成硅化带。在一个实施例中，整个单晶硅带被硅化以产生硅化物条。在硅化物条上形成第二绝缘体，从而将硅化物带与周围结构隔离。在形成第二绝缘体之前或之后，该方法通过第二绝缘体形成与硅化带的端部的电接触。通过使用单晶硅条，任何形式的半导体，例如二极管，导体，绝缘体，晶体管等都可以形成熔丝结构的下面部分。上覆的硅化物材料允许熔丝作为未编程状态的导体。然而，与仅编程状态的仅包含绝缘体的金属或多晶硅基eFuse相反，当本发明的eFuse被编程（并且硅化物被移动或断开）时，下面的半导体结构作为有源半导体器件工作。

12. 发明授权

US07382036B2 Doped single crystal silicon silicided eFuse 有权
标题翻译：掺杂单晶硅硅片eFuse
公开(公告)号：US07382036B2
公开(公告)日：2008-06-03
申请号：US11161320
申请日：2005-07-29
申请人： Edward J. Nowak , Jed H. Rankin , William R. Tonti , Richard Q. Williams
发明人： Edward J. Nowak , Jed H. Rankin , William R. Tonti , Richard Q. Williams
IPC分类号： H01L27/148
CPC分类号： H01L27/10 , H01L23/5256 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An eFuse begins with a single crystal silicon-on-insulator (SOI) structure that has a single crystal silicon layer on a first insulator layer. The single crystal silicon layer is patterned into a strip. Before or after the patterning, the single crystal silicon layer is doped with one or more impurities. At least an upper portion of the single crystal silicon layer is then silicided to form a silicided strip. In one embodiment the entire single crystal silicon strip is silicided to create a silicide strip. Second insulator(s) is/are formed on the silicide strip, so as to isolate the silicided strip from surrounding structures. Before or after forming the second insulators, the method forms electrical contacts through the second insulators to ends of the silicided strip. By utilizing a single crystal silicon strip, any form of semiconductor, such as a diode, conductor, insulator, transistor, etc. can form the underlying portion of the fuse structure. The overlying silicide material allows the fuse to act as a conductor in its unprogrammed state. However, contrary to metal or polysilicon based eFuses which only comprise an insulator in the programmed state, when the inventive eFuse is programmed (and the silicide is moved or broken) the underlying semiconductor structure operates as an active semiconductor device.
摘要翻译： eFuse从在第一绝缘体层上具有单晶硅层的单晶硅绝缘体（SOI）结构开始。将单晶硅层图案化成条带。在构图之前或之后，单晶硅层掺杂有一种或多种杂质。至少单晶硅层的上部然后被硅化以形成硅化带。在一个实施例中，整个单晶硅带被硅化以产生硅化物条。在硅化物条上形成第二绝缘体，从而将硅化物带与周围结构隔离。在形成第二绝缘体之前或之后，该方法通过第二绝缘体形成与硅化带的端部的电接触。通过使用单晶硅条，任何形式的半导体，例如二极管，导体，绝缘体，晶体管等都可以形成熔丝结构的下面部分。上覆的硅化物材料允许熔丝作为未编程状态的导体。然而，与仅编程状态的仅包含绝缘体的金属或多晶硅基eFuse相反，当本发明的eFuse被编程（并且硅化物被移动或断开）时，下面的半导体结构作为有源半导体器件工作。

13. 发明申请

US20080185644A1 FETS WITH SELF-ALIGNED BODIES AND BACKGATE HOLES 有权
标题翻译：具有自对准体和背部孔的FET
公开(公告)号：US20080185644A1
公开(公告)日：2008-08-07
申请号：US11539288
申请日：2006-10-06
申请人： Brent A. Anderson , Andres Bryant , Edward J. Nowak , Richard Q. Williams
发明人： Brent A. Anderson , Andres Bryant , Edward J. Nowak , Richard Q. Williams
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/78612 , H01L29/66772 , H01L29/78621 , H01L29/78648
摘要： A FET has a shallow source/drain region, a deep channel region, a gate stack and a back gate that is surrounded by dielectric. The FET structure also includes halo or pocket implants that extend through the entire depth of the channel region. Because a portion of the halo and well doping of the channel is deeper than the source/drain depth, better threshold voltage and process control is achieved. A back-gated FET structure is also provided having a first dielectric layer in this structure that runs under the shallow source/drain region between the channel region and the back gate. This first dielectric layer extends from under the source/drain regions on either side of the back gate and is in contact with a second dielectric such that the back gate is bounded on each side or isolated by dielectric.
摘要翻译： FET具有浅电源/漏极区域，深沟道区域，栅极堆叠和被电介质包围的背栅极。 FET结构还包括延伸通过通道区域的整个深度的晕或凹坑植入物。因为沟道的一部分光晕和阱掺杂比源极/漏极深度更深，所以实现了更好的阈值电压和过程控制。还提供了后栅化FET结构，其具有在该结构中的第一介电层，其在沟道区域和后栅极之间的浅源极/漏极区域下方延伸。该第一电介质层从背栅的两侧的源极/漏极区下方延伸并与第二电介质接触，使得后栅极在每一侧上界定或通过电介质隔离。

14. 发明授权

US07345334B2 Integrated circuit (IC) with high-Q on-chip discrete capacitors 失效
标题翻译：集成电路（IC）与高Q片上分立电容
公开(公告)号：US07345334B2
公开(公告)日：2008-03-18
申请号：US10908081
申请日：2005-04-27
申请人： Edward J. Nowak , Richard Q. Williams
发明人： Edward J. Nowak , Richard Q. Williams
IPC分类号： H01L29/72
CPC分类号： H01L27/1203 , H01L27/0805 , H01L29/94
摘要： A semiconductor structure that may be a discrete capacitor, a Silicon On Insulator (SOI) Integrated Circuit (IC) including circuits with discrete such capacitors and/or decoupled by such discrete capacitors and an on-chip decoupling capacitor (decap). One capacitor plate may be a well (N-well or P-well) in a silicon bulk layer or a thickened portion of a surface silicon layer. The other capacitor plate may be doped polysilicon and separated from the first capacitor plate by capacitor dielectric, e.g., CVD or thermal oxide. Contacts to each of the capacitor plates directly connect and extend from the respective plates, such that direct contact is available from both plates.
摘要翻译：可以是分立电容器的半导体结构，包括具有离散这种电容器的电路和/或由这种分立电容器去耦合的片上绝缘体（SOI）集成电路（IC）和片上去耦电容器（decap））。一个电容器板可以是硅本体层中的阱（N阱或P阱）或表面硅层的增厚部分。另一个电容器板可以是掺杂多晶硅并且通过电容器电介质例如CVD或热氧化物与第一电容器板分离。与每个电容器板的接触件从相应的板直接连接和延伸，使得从两个板可以直接接触。

15. 发明授权

US06256184B1 Method and apparatus for providing electrostatic discharge protection 有权
标题翻译：提供静电放电保护的方法和装置
公开(公告)号：US06256184B1
公开(公告)日：2001-07-03
申请号：US09334088
申请日：1999-06-16
申请人： Robert J. Gauthier Jr. , Edward J. Nowak , Steven H. Voldman , Richard Q. Williams
发明人： Robert J. Gauthier Jr. , Edward J. Nowak , Steven H. Voldman , Richard Q. Williams
IPC分类号： H02H322
CPC分类号： H01L27/0251 , H01L27/0266
摘要： An ESD protection method and apparatus are provided for an IC chip having an I/O pad and I/O circuitry coupled to the I/O pad. A low threshold voltage FET is coupled to the I/O pad in parallel with the I/O circuitry for protecting the IC chip from an ESD event on the I/O pad. The FET also is coupled to a first voltage terminal of the I/O circuitry for providing a shunting path for the ESD event, thereby effectuating the protecting of the IC chip from the ESD event on the I/O pad. A first control circuit is coupled to a gate of the FET for maintaining the gate at a voltage level below a threshold voltage of the FET, thereby maintaining the FET in an off state during normal operation of the IC chip. Preferably a second control circuit is coupled between the FET and the first voltage terminal and operates in conjunction with the first control circuit for maintaining the FET in an off state during normal operation of the IC chip. The first control circuit preferably comprises a short circuit between the gate of the FET and the first voltage terminal, an inverter coupled between the gate of the FET and a second voltage terminal or a negative bias generator coupled to the gate of the FET. The second control circuit preferably comprises a short circuit between the FET and the first voltage terminal or a diode coupled between the FET and the first voltage terminal.
摘要翻译：为具有耦合到I / O焊盘的I / O焊盘和I / O电路的IC芯片提供ESD保护方法和装置。低阈值电压FET与I / O电路并联耦合到I / O焊盘，以保护IC芯片免受I / O焊盘上的ESD事件。 FET还耦合到I / O电路的第一电压端子，用于为ESD事件提供分流路径，从而实现IC芯片免受I / O焊盘上的ESD事件的保护。第一控制电路耦合到FET的栅极，用于将栅极保持在低于FET阈值电压的电压电平，从而在IC芯片正常工作期间保持FET处于截止状态。优选地，第二控制电路耦合在FET和第一电压端子之间，并且与第一控制电路一起操作，以在IC芯片的正常操作期间将FET保持在截止状态。第一控制电路优选地包括在FET的栅极和第一电压端子之间的短路，耦合在FET的栅极和耦合到FET的栅极的第二电压端子或负偏压发生器之间的反相器。第二控制电路优选地包括FET和第一电压端子之间的短路或耦合在FET和第一电压端子之间的二极管。

16. 发明申请

US20120235233A1 FIELD EFFECT TRANSISTOR STRUCTURE AND METHOD OF FORMING SAME 有权
标题翻译：场效应晶体管结构及其形成方法
公开(公告)号：US20120235233A1
公开(公告)日：2012-09-20
申请号：US13046902
申请日：2011-03-14
申请人： Edward J. Nowak , Richard Q. Williams
发明人： Edward J. Nowak , Richard Q. Williams
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/785 , H01L21/823431 , H01L29/66795 , H01L29/66818
摘要： The disclosure relates generally to a metal-oxide-semiconductor field effect transistor (MOSFET) structures and methods of forming the same. The MOSFET structure includes at least one semiconductor body on a substrate; a dielectric cap on a top surface of the at least one semiconductor body, wherein a width of the at least one semiconductor body is less than a width of the dielectric cap; a gate dielectric layer conformally coating the at least one semiconductor body; and at least one electrically conductive gate on the gate dielectric layer.
摘要翻译：本公开一般涉及金属氧化物半导体场效应晶体管（MOSFET）结构及其形成方法。 MOSFET结构在衬底上包括至少一个半导体本体; 在所述至少一个半导体主体的顶表面上的电介质盖，其中所述至少一个半导体本体的宽度小于所述电介质盖的宽度; 保护地涂覆所述至少一个半导体主体的栅介质层; 以及栅极电介质层上的至少一个导电栅极。

17. 发明授权

US07709313B2 High performance capacitors in planar back gates CMOS 失效
标题翻译：平面后门CMOS中的高性能电容器
公开(公告)号：US07709313B2
公开(公告)日：2010-05-04
申请号：US11160999
申请日：2005-07-19
申请人： Andres Bryant , Edward J. Nowak , Richard Q. Williams
发明人： Andres Bryant , Edward J. Nowak , Richard Q. Williams
IPC分类号： H01L21/8238
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/0811 , H01L28/40 , H01L29/78648 , Y10T436/235 , Y10T436/25125 , Y10T436/2525 , Y10T436/25375
摘要： A method of manufacture and device for a dual-gate CMOS structure. The structure includes a first plate in an insulating layer and a second plate above the insulating layer electrically corresponding to the first plate. An isolation structure is between the first plate and the second plate.
摘要翻译：一种双栅极CMOS结构的制造方法和器件。该结构包括绝缘层中的第一板和与第一板电对应的绝缘层之上的第二板。隔离结构在第一板和第二板之间。

18. 发明授权

US07681628B2 Dynamic control of back gate bias in a FinFET SRAM cell 失效
标题翻译： FinFET SRAM单元中背栅极偏置的动态控制
公开(公告)号：US07681628B2
公开(公告)日：2010-03-23
申请号：US11402400
申请日：2006-04-12
申请人： Rajiv V. Joshi , Keunwoo Kim , Edward J. Nowak , Richard Q. Williams
发明人： Rajiv V. Joshi , Keunwoo Kim , Edward J. Nowak , Richard Q. Williams
IPC分类号： G11C11/00
CPC分类号： G11C11/412
摘要： The present invention provides dynamic control of back gate bias on pull-up pFETs in a FinFET SRAM cell. A method according to the present invention includes providing a bias voltage to a back gate of at least one transistor in the SRAM cell, and dynamically controlling the bias voltage based on an operational mode (e.g., Read, Half-Select, Write, Standby) of the SRAM cell.
摘要翻译：本发明提供对FinFET SRAM单元中的上拉pFET的背栅极偏置的动态控制。根据本发明的方法包括向SRAM单元中的至少一个晶体管的背栅提供偏置电压，并且基于操作模式（例如，读取，半选择，写入，待机）动态地控制偏置电压，的SRAM单元。

19. 发明授权

US07375000B2 Discrete on-chip SOI resistors 有权
标题翻译：分立片上SOI电阻
公开(公告)号：US07375000B2
公开(公告)日：2008-05-20
申请号：US11161911
申请日：2005-08-22
申请人： Edward J. Nowak , Richard Q. Williams
发明人： Edward J. Nowak , Richard Q. Williams
IPC分类号： H01L21/20
CPC分类号： H01L29/8605 , H01L27/016 , H01L27/0802 , H01L29/66166
摘要： A semiconductor resistor, method of making the resistor and method of making an IC including resistors. Buried wells are formed in the silicon substrate of a silicon on insulator (SOI) wafer. At least one trench is formed in the buried wells. Resistors are formed along the sidewalls of the trench and, where multiple trenches form pillars, in the pillars between the trenches by doping the sidewalls with an angled implant. Resistor contacts are formed to the buried well at opposite ends of the trenches and pillars, if any.
摘要翻译：半导体电阻器，制造电阻器的方法和制造包括电阻器的IC的方法。掩埋阱形成在绝缘体上硅（SOI）晶片的硅衬底中。在埋井中形成至少一个沟槽。电阻器沿着沟槽的侧壁形成，并且在多个沟槽形成支柱的情况下，通过用成角度的植入物掺杂侧壁，在沟槽之间的支柱中形成电阻器。如果有的话，在沟槽和支柱的相对两端形成电阻触点到掩埋井。

20. 发明授权

US07265005B2 Structure and method for dual-gate FET with SOI substrate 失效
标题翻译：具有SOI衬底的双栅极FET的结构和方法
公开(公告)号：US07265005B2
公开(公告)日：2007-09-04
申请号：US11265464
申请日：2005-11-02
申请人： Edward J. Nowak , Richard Q. Williams
发明人： Edward J. Nowak , Richard Q. Williams
IPC分类号： H01L21/338
CPC分类号： H01L29/785 , H01L29/41791 , H01L29/42384 , H01L29/66795 , H01L2029/7858
摘要： A method of forming a dual gate fin-type field effect transistor (FinFET) structure patterns silicon fins over an insulator and patterns a gate conductor at an angle to the fins. The gate conductor is formed laterally adjacent to and over center portions of the fins. The gate conductor is planarized such that the gate conductor is separated into distinct gate conductor portions that are separated by the fins. These gate conductor portions include front gates and back gates. The front gates and the back gates alternate along the structure, such that each fin has a front gate on one side and a back gate on the opposite side. Then front gate wiring is formed to the front gates and back gate wiring is formed to the back gates.
摘要翻译：形成双栅极鳍型场效应晶体管（FinFET）结构的方法在绝缘体上形成硅散热片，并以与鳍片成角度的方式形成栅极导体。栅极导体横向地形成在鳍片的中心部分附近并且越过其中心部分。栅极导体被平坦化，使得栅极导体分离成由鳍分开的不同的栅极导体部分。这些栅极导体部分包括前门和后门。前门和后门沿着结构交替，使得每个鳍具有一侧的前门和相对侧上的后门。然后，前栅极布线形成于前栅极，并且后栅极布线形成于后栅极。

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