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11. 发明授权

US07129748B1 Non-volatile look-up table for an FPGA 有权
标题翻译： FPGA的非易失性查找表
公开(公告)号：US07129748B1
公开(公告)日：2006-10-31
申请号：US11026336
申请日：2004-12-29
申请人： John McCollum , Gregory Bakker , Jonathan Greene
发明人： John McCollum , Gregory Bakker , Jonathan Greene
IPC分类号： H03K19/177
CPC分类号： H03K19/17728
摘要： A non-volatile-memory-transistor based lookup table for an FPGA includes a n:1 multiplexer. A non-volatile memory transistor is coupled to each of the n inputs of the multiplexer. The multiplexer has x address inputs wherein 2x=n as is known in the art. The output of the multiplexer is coupled to VCC through a pullup transistor. The gate of the pullup transistor is coupled to the output of an address transition detector circuit that has inputs coupled to the address inputs of the multiplexer. A sense amplifier is coupled to the output of the multiplexer.
摘要翻译：用于FPGA的基于非易失性存储器晶体管的查找表包括n：1多路复用器。非易失性存储晶体管耦合到多路复用器的n个输入端中的每一个。如本领域已知的那样，多路复用器具有x地址输入，其中2 = n。多路复用器的输出通过上拉晶体管耦合到V CC。上拉晶体管的栅极耦合到具有耦合到多路复用器的地址输入的输入的地址转换检测器电路的输出。读出放大器耦合到多路复用器的输出端。

12. 发明申请

US20050102342A1 Methods and apparatus for fast fourier transforms 审中-公开
标题翻译：快速傅里叶变换的方法和装置
公开(公告)号：US20050102342A1
公开(公告)日：2005-05-12
申请号：US10643164
申请日：2003-08-18
申请人： Jonathan Greene
发明人： Jonathan Greene
IPC分类号： G06F17/14 , G06F15/00
CPC分类号： G06F17/142
摘要： A system for calculating fast Fourier transforms includes a non-final stage calculating element for repetitively performing in-place butterfly calculations for n−1 stages as well as a final stage calculating element for performing a final stage of butterfly calculations. The final stage calculation includes a first loop and a second loop. The first loop performs a portion of the final stage butterfly calculations and includes control logic to perform groups of butterfly calculations and to store the butterfly calculation outputs in a shuffled order in place of the inputs to result in a correct ordering of transform outputs. The second loop performs a remaining portion of the final stage butterfly calculations and includes control logic to perform butterfly calculations and to store the butterfly calculation outputs in a shuffled order in place of the inputs to result in a correct ordering of transform outputs.
摘要翻译：用于计算快速傅里叶变换的系统包括用于重复执行n-1级的就地蝶形计算的非最终级计算元件以及用于执行蝴蝶计算的最后级的最终级计算元件。最后阶段计算包括第一循环和第二循环。第一个循环执行最后阶段蝴蝶计算的一部分，并且包括控制逻辑以执行蝶形计算组并以混洗顺序存储蝴蝶计算输出来代替输入以产生变换输出的正确排序。第二循环执行最后阶段蝴蝶计算的剩余部分，并且包括执行蝶形计算的控制逻辑，并且以混洗顺序存储蝴蝶计算输出来代替输入以产生变换输出的正确排序。

13. 发明申请

US20130111119A1 RAM BLOCK DESIGNED FOR EFFICIENT GANGING 有权
标题翻译： RAM块被设计用于高效率
公开(公告)号：US20130111119A1
公开(公告)日：2013-05-02
申请号：US13285210
申请日：2011-10-31
申请人： Volker Hecht , Jonathan Greene
发明人： Volker Hecht , Jonathan Greene
IPC分类号： G06F12/00
CPC分类号： G06F12/00 , H03K19/17768 , H03K19/17796
摘要： A random-access memory block for a field programmable gate array includes a random-access memory array having address inputs, a data input, a data output and including a plurality of storage locations. At least two programmably invertible enable inputs are provided. Hardwired decoding logic is coupled to the at least two programmably invertible enable inputs to selectively enable the random-access memory array. A gate is coupled to the output of the random-access memory array and is configured to pass the output of the random-access memory array only if the random-access memory is enabled for a read operation, and otherwise generate a preselected logic state.
摘要翻译：用于现场可编程门阵列的随机存取存储器块包括具有地址输入，数据输入，数据输出并且包括多个存储位置的随机存取存储器阵列。提供至少两个可编程的可逆可用输入。硬连线解码逻辑被耦合到至少两个可编程的可逆可用使能输入以选择性地启用随机存取存储器阵列。门被耦合到随机存取存储器阵列的输出，并且被配置为仅当对读操作启用随机存取存储器时才传递随机存取存储器阵列的输出，否则生成预选逻辑状态。

14. 发明授权

US08269204B2 Back to back resistive random access memory cells 有权
标题翻译：背靠背电阻随机存取存储单元
公开(公告)号：US08269204B2
公开(公告)日：2012-09-18
申请号：US12829305
申请日：2010-07-01
申请人： Jonathan Greene , Frank W. Hawley , John McCollum
发明人： Jonathan Greene , Frank W. Hawley , John McCollum
IPC分类号： H01L29/02
CPC分类号： H03K19/1776 , H01L27/2436 , H01L27/2463 , H01L45/085 , H01L45/122 , H01L45/1233 , H01L45/1253 , H01L45/1266 , H01L45/141 , H01L45/142 , H01L45/149 , H01L45/1616 , H01L45/1625 , H01L45/1675 , H03K19/17724 , Y10S438/90
摘要： A resistive random access memory device formed on a semiconductor substrate comprises an interlayer dielectric having a via formed therethrough. A chemical-mechanical-polishing stop layer is formed over the interlayer dielectric. A barrier metal liner lines walls of the via. A conductive plug is formed in the via. A first barrier metal layer is formed over the chemical-mechanical-polishing stop layer and in electrical contact with the conductive plug. A dielectric layer is formed over the first barrier metal layer. An ion source layer is formed over the dielectric layer. A dielectric barrier layer is formed over the ion source layer, and includes a via formed therethrough communicating with the ion source layer. A second barrier metal layer is formed over the dielectric barrier layer and in electrical contact with the ion source layer. A metal interconnect layer is formed over the barrier metal layer.
摘要翻译：形成在半导体衬底上的电阻性随机存取存储器件包括具有穿过其中形成的通孔的层间电介质。在层间电介质上形成化学机械抛光停止层。屏障金属衬垫线路通孔的墙壁。在通孔中形成导电塞。第一阻挡金属层形成在化学机械抛光停止层上并与导电塞电接触。在第一阻挡金属层上形成电介质层。在电介质层上形成离子源层。介电阻挡层形成在离子源层上，并且包括与离子源层连通的通孔。第二阻挡金属层形成在电介质阻挡层上并与离子源层电接触。金属互连层形成在阻挡金属层的上方。

15. 发明授权

US07581117B1 Method for secure delivery of configuration data for a programmable logic device 有权
标题翻译：用于可编程逻辑器件的配置数据的安全传送的方法
公开(公告)号：US07581117B1
公开(公告)日：2009-08-25
申请号：US11185427
申请日：2005-07-19
申请人： Kenneth Irving , Jonathan Greene
发明人： Kenneth Irving , Jonathan Greene
IPC分类号： H04L9/32
CPC分类号： G06F21/14
摘要： Secure delivery of configuration data of an intellectual property (IP) core includes the steps of loading configuration data for the IP core into IP core space by an IP core provider, masking portions of the IP core space not loaded with configuration data in the loading configuration data step with the value 0 or 1 by the IP core provider, encrypting data in the IP core space by the IP core provider, loading configuration data for system design other than for the IP core into a remainder space and any unused portions of the IP core space by a system designer, masking portions of the IP core space loaded in the loading configuration data step with the value 0 or 1 used by the IP core provider in the masking portions of the IP core space not loaded step, and encrypting data in a configuration space by the system designer.
摘要翻译：知识产权（IP）核心的安全交付配置数据包括以下步骤：由IP核心提供商将IP内核的配置数据加载到IP核心空间中，掩盖在加载配置中未加载配置数据的IP核空间部分 IP核心提供商的值为0或1的数据步骤，由IP核心提供商加密IP核心空间中的数据，将用于系统设计的配置数据加载到IP核以外的剩余空间和IP的任何未使用部分通过系统设计者对IP核心空间的加载配置数据步骤中的IP核心空间的部分进行掩蔽，IP核心提供商在IP核心空间未加载步骤的掩蔽部分中使用的值为0或1的值，系统设计者的一个配置空间。

16. 发明申请

US20080007292A1 NON-VOLATILE LOOK-UP TABLE FOR AN FPGA 有权
标题翻译： FPGA的非易失性查看表
公开(公告)号：US20080007292A1
公开(公告)日：2008-01-10
申请号：US11858330
申请日：2007-09-20
申请人： John McCollum , Gregory Bakker , Jonathan Greene
发明人： John McCollum , Gregory Bakker , Jonathan Greene
IPC分类号： H03K19/177
CPC分类号： H03K19/17728
摘要： A non-volatile-memory-transistor based lookup table for an FPGA includes a n:1 multiplexer. A non-volatile memory transistor is coupled to each of the n inputs of the multiplexer. The multiplexer has x address inputs wherein 2x=n as is known in the art. The output of the multiplexer is coupled to Vcc through a pullup transistor. The gate of the pullup transistor is coupled to the output of an address transition detector circuit that has inputs coupled to the address inputs of the multiplexer. A sense amplifier is coupled to the output of the multiplexer.
摘要翻译：用于FPGA的基于非易失性存储器晶体管的查找表包括n：1多路复用器。非易失性存储晶体管耦合到多路复用器的n个输入端中的每一个。如本领域已知的那样，多路复用器具有x地址输入，其中2 = n。多路复用器的输出通过上拉晶体管耦合到V cc。上拉晶体管的栅极耦合到具有耦合到多路复用器的地址输入的输入的地址转换检测器电路的输出。读出放大器耦合到多路复用器的输出端。

17. 发明申请

US20130221316A1 FRONT TO BACK RESISTIVE RANDOM ACCESS MEMORY CELLS 有权
标题翻译：前端电阻随机存取存储器
公开(公告)号：US20130221316A1
公开(公告)日：2013-08-29
申请号：US13840815
申请日：2013-03-15
申请人： Jonathan Greene , Frank W. Hawley , John McCollum
发明人： Jonathan Greene , Frank W. Hawley , John McCollum
IPC分类号： H01L45/00
CPC分类号： H03K19/1776 , H01L27/2436 , H01L27/2463 , H01L45/085 , H01L45/122 , H01L45/1233 , H01L45/1253 , H01L45/1266 , H01L45/141 , H01L45/142 , H01L45/149 , H01L45/1616 , H01L45/1625 , H01L45/1675 , H03K19/17724 , Y10S438/90
摘要： A resistive random access memory device formed on a semiconductor substrate comprises an interlayer dielectric having a via formed therethrough. A chemical-mechanical-polishing stop layer is formed over the interlayer dielectric. A barrier metal liner lines walls of the via. A conductive plug is formed in the via. A first barrier metal layer is formed over the chemical-mechanical-polishing stop layer and in electrical contact with the conductive plug. A dielectric layer is formed over the first barrier metal layer. An ion source layer is formed over the dielectric layer. A dielectric barrier layer is formed over the ion source layer, and includes a via formed therethrough communicating with the ion source layer. A second barrier metal layer is formed over the dielectric barrier layer and in electrical contact with the ion source layer. A metal interconnect layer is formed over the barrier metal layer.
摘要翻译：形成在半导体衬底上的电阻性随机存取存储器件包括具有穿过其中形成的通孔的层间电介质。在层间电介质上方形成化学机械抛光停止层。屏障金属衬垫线路通孔的墙壁。在通孔中形成导电塞。第一阻挡金属层形成在化学机械抛光停止层上并与导电塞电接触。在第一阻挡金属层上形成电介质层。在电介质层上形成离子源层。介电阻挡层形成在离子源层上，并且包括与离子源层连通的通孔。第二阻挡金属层形成在电介质阻挡层上并与离子源层电接触。金属互连层形成在阻挡金属层的上方。

18. 发明授权

US08415650B2 Front to back resistive random access memory cells 有权
标题翻译：从前到后的电阻随机存取存储单元
公开(公告)号：US08415650B2
公开(公告)日：2013-04-09
申请号：US12829311
申请日：2010-07-01
申请人： Jonathan Greene , Frank W. Hawley , John McCollum
发明人： Jonathan Greene , Frank W. Hawley , John McCollum
IPC分类号： H01L29/02
CPC分类号： H03K19/1776 , H01L27/2436 , H01L27/2463 , H01L45/085 , H01L45/122 , H01L45/1233 , H01L45/1253 , H01L45/1266 , H01L45/141 , H01L45/142 , H01L45/149 , H01L45/1616 , H01L45/1625 , H01L45/1675 , H03K19/17724 , Y10S438/90
摘要： A resistive random access memory cell is formed on a semiconductor substrate. First and second diffused regions are disposed in the semiconductor substrate. A polysilicon gate is disposed above the first and second diffused regions. A first contact connects the first diffused region with a region of a first metal layer. A first interlayer dielectric layer is formed over the first metal layer and includes first and second vias, each including conductive plugs connected to the region of the first metal layer. First and second resistive random access memory devices formed over the first interlayer dielectric layer have first and second terminals, and include a dielectric layer and an ion source layer. The first terminals of the first and second resistive random access memory devices are coupled to the first metal layer by the first and second conductive plugs.
摘要翻译：电阻性随机存取存储单元形成在半导体衬底上。第一和第二扩散区域设置在半导体衬底中。多晶硅栅极设置在第一和第二扩散区域上方。第一接触将第一扩散区域与第一金属层的区域连接。第一层间电介质层形成在第一金属层之上，并且包括第一和第二通孔，每个通孔包括连接到第一金属层的区域的导电插塞。形成在第一层间介质层上的第一和第二电阻随机存取存储器件具有第一和第二端子，并且包括电介质层和离子源层。第一和第二电阻随机存取存储器件的第一端子通过第一和第二导电插塞耦合到第一金属层。

19. 发明授权

US08244791B1 Fast carry lookahead circuits 有权
标题翻译：快速携带查找电路
公开(公告)号：US08244791B1
公开(公告)日：2012-08-14
申请号：US12022721
申请日：2008-01-30
申请人： Volker Hecht , Marcel Derevlean , Jonathan Greene
发明人： Volker Hecht , Marcel Derevlean , Jonathan Greene
IPC分类号： G06F7/50
CPC分类号： G06F7/508
摘要： A fast lookahead carry adder includes adder logic and lookahead carry-path logic coupled to the adder logic. The carry path logic has a main carry path, a carry entrance path and a carry exit path, the carry entrance path separate from the carry exit path.
摘要翻译：快速前瞻进位加法器包括耦合到加法器逻辑的加法器逻辑和先行进位逻辑逻辑。进位路径逻辑具有主进位路径，进位入口路径和进位出口路径，进位路径与进位出口路径分离。

20. 发明申请

US20110001108A1 FRONT TO BACK RESISTIVE RANDOM ACCESS MEMORY CELLS 有权
标题翻译：前端电阻随机存取存储器
公开(公告)号：US20110001108A1
公开(公告)日：2011-01-06
申请号：US12829311
申请日：2010-07-01
申请人： Jonathan Greene , Frank W. Hawley , John McCollum
发明人： Jonathan Greene , Frank W. Hawley , John McCollum
IPC分类号： H01L45/00
CPC分类号： H03K19/1776 , H01L27/2436 , H01L27/2463 , H01L45/085 , H01L45/122 , H01L45/1233 , H01L45/1253 , H01L45/1266 , H01L45/141 , H01L45/142 , H01L45/149 , H01L45/1616 , H01L45/1625 , H01L45/1675 , H03K19/17724 , Y10S438/90
摘要： A resistive random access memory device formed on a semiconductor substrate comprises an interlayer dielectric having a via formed therethrough. A chemical-mechanical-polishing stop layer is formed over the interlayer dielectric. A barrier metal liner lines walls of the via. A conductive plug is formed in the via. A first barrier metal layer is formed over the chemical-mechanical-polishing stop layer and in electrical contact with the conductive plug. A dielectric layer is formed over the first barrier metal layer. An ion source layer is formed over the dielectric layer. A dielectric barrier layer is formed over the ion source layer, and includes a via formed therethrough communicating with the ion source layer. A second barrier metal layer is formed over the dielectric barrier layer and in electrical contact with the ion source layer. A metal interconnect layer is formed over the barrier metal layer.
摘要翻译：形成在半导体衬底上的电阻性随机存取存储器件包括具有穿过其中形成的通孔的层间电介质。在层间电介质上形成化学机械抛光停止层。屏障金属衬垫线路通孔的墙壁。在通孔中形成导电塞。第一阻挡金属层形成在化学机械抛光停止层上并与导电塞电接触。在第一阻挡金属层上形成电介质层。在电介质层上形成离子源层。介电阻挡层形成在离子源层上，并且包括与离子源层连通的通孔。第二阻挡金属层形成在电介质阻挡层上并与离子源层电接触。金属互连层形成在阻挡金属层的上方。

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