专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明申请

US20120233477A1 DYNAMIC CORE SELECTION FOR HETEROGENEOUS MULTI-CORE SYSTEMS 有权
标题翻译：异构多核系统的动态核心选择
公开(公告)号：US20120233477A1
公开(公告)日：2012-09-13
申请号：US13046031
申请日：2011-03-11
申请人： Youfeng Wu , Shiliang Hu , Edson Borin , Cheng Wang
发明人： Youfeng Wu , Shiliang Hu , Edson Borin , Cheng Wang
IPC分类号： G06F9/318 , G06F1/32
CPC分类号： G06F1/329 , G06F1/3287 , G06F9/3851 , G06F9/445 , G06F9/4893 , G06F9/5027 , G06F9/5094 , G06F11/3409 , G06F11/3452 , G06F11/3466 , G06F2201/81 , G06F2201/865 , G06F2201/88 , G06F2209/501 , Y02D10/171 , Y02D10/22 , Y02D10/34 , Y02D50/20
摘要： Dynamically switching cores on a heterogeneous multi-core processing system may be performed by executing program code on a first processing core. Power up of a second processing core may be signaled. A first performance metric of the first processing core executing the program code may be collected. When the first performance metric is better than a previously determined core performance metric, power down of the second processing core may be signaled and execution of the program code may be continued on the first processing core. When the first performance metric is not better than the previously determined core performance metric, execution of the program code may be switched from the first processing core to the second processing core.
摘要翻译：可以通过在第一处理核上执行程序代码来执行异构多核处理系统上的动态切换核。可以用信号通知第二处理核心的加电。可以收集执行程序代码的第一处理核心的第一性能度量。当第一性能指标优于先前确定的核心性能指标时，可以发信号通知第二处理核心的掉电，并且可以在第一处理核心上继续执行程序代码。当第一性能度量不比先前确定的核心性能指标更好时，程序代码的执行可以从第一处理核心切换到第二处理核心。

12. 发明申请

US20120079245A1 DYNAMIC OPTIMIZATION FOR CONDITIONAL COMMIT 审中-公开
标题翻译：动态优化条件咨询
公开(公告)号：US20120079245A1
公开(公告)日：2012-03-29
申请号：US12890638
申请日：2010-09-25
申请人： Cheng Wang , Edson Borin , Youfeng Wu , Shiliang Hu , Wei Liu , Mauricio Breternitz, JR.
发明人： Cheng Wang , Edson Borin , Youfeng Wu , Shiliang Hu , Wei Liu , Mauricio Breternitz, JR.
IPC分类号： G06F9/312 , G06F9/38 , G06F9/30
CPC分类号： G06F9/3842 , G06F8/52 , G06F9/3004 , G06F9/30072 , G06F9/30087 , G06F9/30116 , G06F9/3857
摘要： An apparatus and method is described herein for conditionally committing and/or speculative checkpointing transactions, which potentially results in dynamic resizing of transactions. During dynamic optimization of binary code, transactions are inserted to provide memory ordering safeguards, which enables a dynamic optimizer to more aggressively optimize code. And the conditional commit enables efficient execution of the dynamic optimization code, while attempting to prevent transactions from running out of hardware resources. While the speculative checkpoints enable quick and efficient recovery upon abort of a transaction. Processor hardware is adapted to support dynamic resizing of the transactions, such as including decoders that recognize a conditional commit instruction, a speculative checkpoint instruction, or both. And processor hardware is further adapted to perform operations to support conditional commit or speculative checkpointing in response to decoding such instructions.
摘要翻译：本文描述了用于有条件地提交和/或推测性检查点事务的装置和方法，这可能导致事务的动态调整大小。在二进制代码的动态优化期间，插入事务以提供存储器排序保护措施，这使得动态优化器能够更积极地优化代码。并且条件提交可以有效地执行动态优化代码，同时尝试防止事务用尽硬件资源。虽然投机检查点能够在中止交易后快速有效地恢复。处理器硬件适于支持事务的动态调整大小，诸如包括识别条件提交指令的解码器，推测性检查点指令或两者。并且处理器硬件还适于执行响应于解码这样的指令来支持条件提交或推测性检查点的操作。

13. 发明申请

US20110153999A1 METHODS AND APPARATUS TO MANAGE PARTIAL-COMMIT CHECKPOINTS WITH FIXUP SUPPORT 有权
标题翻译：使用固定支持管理部分提交检查的方法和设备
公开(公告)号：US20110153999A1
公开(公告)日：2011-06-23
申请号：US12644151
申请日：2009-12-22
申请人： Edson Borin , Youfeng Wu
发明人： Edson Borin , Youfeng Wu
IPC分类号： G06F9/312
CPC分类号： G06F9/30145 , G06F9/3834 , G06F9/3842 , G06F9/3857 , G06F9/3863
摘要： Example methods and apparatus to manage partial commit-checkpoints are disclosed. A disclosed example method includes identifying a commit instruction associated with a region of instructions executed by a processor, identifying candidate instructions from the region of instructions, and generating a processor partial commit-checkpoint to save a current state of the processor, the checkpoint based on calculated register values associated with live instructions, and including instruction reference addresses to link the candidate instructions.
摘要翻译：公开了用于管理部分提交检查点的示例性方法和装置。所公开的示例性方法包括识别与由处理器执行的指令区域相关联的提交指令，从指令区域识别候选指令，以及生成处理器部分提交检查点以保存处理器的当前状态，所述检查点基于与实时指令相关联的计算寄存器值，并包括链接候选指令的指令参考地址。

14. 发明授权

US08549267B2 Methods and apparatus to manage partial-commit checkpoints with fixup support 有权
标题翻译：使用fixup支持来管理部分提交检查点的方法和设备
公开(公告)号：US08549267B2
公开(公告)日：2013-10-01
申请号：US12644151
申请日：2009-12-22
申请人： Edson Borin , Youfeng Wu
发明人： Edson Borin , Youfeng Wu
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44 , G06F15/00
CPC分类号： G06F9/30145 , G06F9/3834 , G06F9/3842 , G06F9/3857 , G06F9/3863
摘要： Example methods and apparatus to manage partial commit-checkpoints are disclosed. A disclosed example method includes identifying a commit instruction associated with a region of instructions executed by a processor, identifying candidate instructions from the region of instructions, and generating a processor partial commit-checkpoint to save a current state of the processor, the checkpoint based on calculated register values associated with live instructions, and including instruction reference addresses to link the candidate instructions.
摘要翻译：公开了用于管理部分提交检查点的示例性方法和装置。所公开的示例性方法包括识别与由处理器执行的指令区域相关联的提交指令，从指令区域识别候选指令，以及生成处理器部分提交检查点以保存处理器的当前状态，所述检查点基于与实时指令相关联的计算寄存器值，并包括链接候选指令的指令参考地址。

15. 发明授权

US07506217B2 Apparatus and method for software-based control flow checking for soft error detection to improve microprocessor reliability 有权
标题翻译：用于软件错误检测的软件控制流程检查的装置和方法，以提高微处理器的可靠性
公开(公告)号：US07506217B2
公开(公告)日：2009-03-17
申请号：US11325773
申请日：2005-12-30
申请人： Edson Borin , Cheng C. Wang , Youfeng Wu
发明人： Edson Borin , Cheng C. Wang , Youfeng Wu
IPC分类号： G06F11/00
CPC分类号： G06F11/1004
摘要： A method and apparatus for software-based control flow checking for soft error detection. In one embodiment, the method includes the instrumentation of one basic block of a target program to update a signature register with a successor basic block signature at an end of the basic block. In addition, the basic block is instrumented to verify that contents of the signature register match a basic block signature at a beginning of the basic block. In one embodiment, an instruction is inserted within the basic block to cause the signature register to store a predetermined value if the contents of the signature register match a basic block signature. In one embodiment, a basic block may be subdivided into a plurality of regions; each region is assigned a signature and instrumented to update the signature register at a beginning of each region. Other embodiments are described and claimed.
摘要翻译：一种用于软错误检测的基于软件的控制流程检查的方法和装置。在一个实施例中，该方法包括在基本块的结尾处对目标程序的一个基本块的仪表进行更新具有后继基本块签名的签名寄存器。另外，基本块被验证以验证签名寄存器的内容是否与基本块开头的基本块签名相匹配。在一个实施例中，如果签名寄存器的内容与基本块签名匹配，则在基本块内插入指令以使签名寄存器存储预定值。在一个实施例中，基本块可以被细分为多个区域; 每个区域都被分配一个签名，并在每个区域的开头进行检测以更新签名寄存器。描述和要求保护其他实施例。

16. 发明申请

US20140032885A1 METHODS AND APPARATUS TO MANAGE PARTIAL-COMMIT CHECKPOINTS WITH FIXUP SUPPORT 有权
标题翻译：使用固定支持管理部分提交检查的方法和设备
公开(公告)号：US20140032885A1
公开(公告)日：2014-01-30
申请号：US14041170
申请日：2013-09-30
申请人： Edson Borin , Youfeng Wu
发明人： Edson Borin , Youfeng Wu
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F9/3834 , G06F9/3842 , G06F9/3857 , G06F9/3863
摘要： Example methods and apparatus to manage partial commit-checkpoints are disclosed. A disclosed example method includes identifying a commit instruction associated with a region of instructions executed by a processor, identifying candidate instructions from the region of instructions, and generating a processor partial commit-checkpoint to save a current state of the processor, the checkpoint based on calculated register values associated with live instructions, and including instruction reference addresses to link the candidate instructions.
摘要翻译：公开了用于管理部分提交检查点的示例性方法和装置。所公开的示例性方法包括识别与由处理器执行的指令区域相关联的提交指令，从指令区域识别候选指令，以及生成处理器部分提交检查点以保存处理器的当前状态，所述检查点基于与实时指令相关联的计算寄存器值，并包括链接候选指令的指令参考地址。

17. 发明授权

US09354882B2 Methods and apparatus to manage partial-commit checkpoints with fixup support 有权
公开(公告)号：US09354882B2
公开(公告)日：2016-05-31
申请号：US14041170
申请日：2013-09-30
申请人： Edson Borin , Youfeng Wu
发明人： Edson Borin , Youfeng Wu
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44 , G06F15/00 , G06F9/30 , G06F9/38
CPC分类号： G06F9/30145 , G06F9/3834 , G06F9/3842 , G06F9/3857 , G06F9/3863
摘要： Example methods and apparatus to manage partial commit-checkpoints are disclosed. A disclosed example method includes identifying a commit instruction associated with a region of instructions executed by a processor, identifying candidate instructions from the region of instructions, and generating a processor partial commit-checkpoint to save a current state of the processor, the checkpoint based on calculated register values associated with live instructions, and including instruction reference addresses to link the candidate instructions.

18. 发明申请

US20110320766A1 APPARATUS, METHOD, AND SYSTEM FOR IMPROVING POWER, PERFORMANCE EFFICIENCY BY COUPLING A FIRST CORE TYPE WITH A SECOND CORE TYPE 审中-公开
标题翻译：用于提高功率的装置，方法和系统，通过与第二核心类型耦合的第一核心类型的性能效率
公开(公告)号：US20110320766A1
公开(公告)日：2011-12-29
申请号：US12826107
申请日：2010-06-29
申请人： Youfeng Wu , Shiliang Hu , Edson Borin , Cheng C. Wang , Mauricio Breternitz, JR. , Wei Liu
发明人： Youfeng Wu , Shiliang Hu , Edson Borin , Cheng C. Wang , Mauricio Breternitz, JR. , Wei Liu
IPC分类号： G06F9/30 , G06F15/76
CPC分类号： G06F9/30076 , G06F9/30174 , G06F9/3879 , G06F9/4893 , Y02D10/24
摘要： An apparatus and method is described herein for coupling a processor core of a first type with a co-designed core of a second type. Execution of program code on the first core is monitored and hot sections of the program code are identified. Those hot sections are optimize for execution on the co-designed core, such that upon subsequently encountering those hot sections, the optimized hot sections are executed on the co-designed core. When the co-designed core is executing optimized hot code, the first processor core may be in a low-power state to save power or executing other code in parallel. Furthermore, multiple threads of cold code may be pipelined on the first core, while multiple threads of hot code are pipeline on the co-designed core to achieve maximum performance.
摘要翻译：本文描述了一种用于将第一类型的处理器核与第二类型的共同设计的核耦合的装置和方法。对第一个核心上的程序代码执行进行监控，并且识别程序代码的热部分。这些热部分优化用于在共同设计的芯上执行，使得在随后遇到这些热部分时，优化的热部分在共同设计的核上执行。当共同设计的核心正在执行优化的热代码时，第一处理器核心可以处于低功率状态以节省功率或并行执行其他代码。此外，多个冷码线程可以在第一核心上流水线化，而多个热代码线程在共同设计的核心上进行流水线以实现最大性能。

19. 发明申请

US20160188305A1 TECHNOLOGIES FOR LOW-LEVEL COMPOSABLE HIGH PERFORMANCE COMPUTING LIBRARIES 有权
标题翻译：低水平复合高性能计算机图形技术
公开(公告)号：US20160188305A1
公开(公告)日：2016-06-30
申请号：US14583657
申请日：2014-12-27
申请人： Hongbo Rong , Peng Tu , Tatiana Shpeisman , Hai Liu , Todd A. Anderson , Youfeng Wu , Arthur N. Glew , Paul M. PetersEn , Victor W. Lee , P.G. Lowney , Arch D. Robinson , Cheng Wang
发明人： Hongbo Rong , Peng Tu , Tatiana Shpeisman , Hai Liu , Todd A. Anderson , Youfeng Wu , Arthur N. Glew , Paul M. PetersEn , Victor W. Lee , P.G. Lowney , Arch D. Robinson , Cheng Wang
IPC分类号： G06F9/45 , G06F9/44
CPC分类号： G06F8/43 , G06F8/31 , G06F8/443 , G06F8/4441 , G06F8/453 , G06F8/49 , G06F8/54
摘要： Technologies for generating composable library functions include a first computing device that includes a library compiler configured to compile a composable library and second computing device that includes an application compiler configured to compose library functions of the composable library based on a plurality of abstractions written at different levels of abstractions. For example, the abstractions may include an algorithm abstraction at a high level, a blocked-algorithm abstraction at medium level, and a region-based code abstraction at a low level. Other embodiments are described and claimed herein.
摘要翻译：用于生成可组合库函数的技术包括：第一计算设备，其包括被配置为编译可组合库的库编译器和第二计算设备，所述第二计算设备包括应用编译器，所述应用编译器被配置为基于以不同级别写入的多个抽象来组合所述可组合库的库函数的抽象。例如，抽象可以包括高级别的算法抽象，中等级别的阻塞算法抽象，以及低级别的基于区域的代码抽象。在此描述和要求保护的其它实施例。

20. 发明申请

US20140208085A1 INSTRUCTION AND LOGIC TO EFFICIENTLY MONITOR LOOP TRIP COUNT 有权
标题翻译：指令和逻辑到有效的监视器循环次数
公开(公告)号：US20140208085A1
公开(公告)日：2014-07-24
申请号：US13996861
申请日：2012-03-30
申请人： Jaewoong Chung , Hyunchul Park , Hongbo Rong , Cheng Wang , Youfeng Wu
发明人： Jaewoong Chung , Hyunchul Park , Hongbo Rong , Cheng Wang , Youfeng Wu
IPC分类号： G06F9/32
CPC分类号： G06F9/325 , G06F8/443 , G06F9/30072 , G06F9/3842 , G06F9/3857 , G06F11/3409 , G06F11/348 , G06F2201/88
摘要： Logic and instruction to efficiently monitor loop trip count. Loop trip count information of a loop may be stored in a dedicated hardware buffer. Average loop trip count of the loop may be calculated based on the stored loop trip count information. Based on the average trip count, loop optimizations may be applied or removed from the loop. The stored loop trip count information may include an identifier identifying the loop, a total loop trip count of the loop, and an exit count of the loop.
摘要翻译：有效监控回路行程数的逻辑和指令。循环的循环行程计数信息可以存储在专用硬件缓冲器中。可以基于存储的循环行程计数信息来计算循环的平均循环行程计数。基于平均行程计数，循环优化可以从循环中应用或移除。存储的循环行程计数信息可以包括标识循环的标识符，循环的总循环行程计数以及循环的退出计数。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式