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11. 发明授权

US06356503B1 Reduced latency row selection circuit and method 有权
标题翻译：减少延迟行选择电路和方法
公开(公告)号：US06356503B1
公开(公告)日：2002-03-12
申请号：US09510692
申请日：2000-02-23
申请人： Richard Roy
发明人： Richard Roy
IPC分类号： G11C800
CPC分类号： G11C8/18 , G11C8/10
摘要： A reduced latency row selection circuit and method for selecting a wordline in a memory instance. Capacitance associated with row select path is de-coupled from capacitance associated with row de-select path such that both forward path delay and de-selection path delay may be optimized independently. Clock-to-wordline latency is reduced by a rapid six-stage structure that may be implemented using various logic gates. A row pre-decoder portion generates a decoded wordline clock (DXC) signal based on a row decode select clock (XC) signal and a portion of pre-decoded row address signals. The DXC signal is used by a row decoder portion for generating a wordline select (XWL) signal based on another portion of the address signals. Circuitry is provided for releasing the selected wordline in the memory upon receiving a wordline shutdown clock signal generated responsive to signals provided by dummy wordline and dummy read bitline structures disposed in the memory.
摘要翻译：用于选择存储器实例中的字线的减少延迟行选择电路和方法。与行选择路径相关联的电容与与行去选择路径相关联的电容解耦耦合，使得前向路径延迟和解选路径延迟可以独立地优化。通过可以使用各种逻辑门来实现的快速六级结构来减少时钟到字线延迟。行预解码器部分基于行解码选择时钟（XC）信号和预解码行地址信号的一部分生成解码字线时钟（DXC）信号。 DXC信号由行解码器部分用于基于地址信号的另一部分生成字线选择（XWL）信号。提供电路，用于在接收到响应由设置在存储器中的伪字线和伪读位线结构提供的信号产生的字线关闭时钟信号时释放存储器中的选定字线。

12. 发明授权

US11447017B2 Control of user-selectable vehicle deceleration rate to maximize regeneration for electrified propulsion systems 有权
公开(公告)号：US11447017B2
公开(公告)日：2022-09-20
申请号：US16776906
申请日：2020-01-30
申请人： Nadirsh Patel , James R Hollowell , Divya E Gorecki , Chandan Lakshmanaiah , Zachary C Rogalski , Richard Roy
发明人： Nadirsh Patel , James R Hollowell , Divya E Gorecki , Chandan Lakshmanaiah , Zachary C Rogalski , Richard Roy
IPC分类号： B60L7/26 , B60L3/00 , B60L7/18 , B60T7/12 , B60T8/17 , B60W10/188 , B60W20/00 , B60W30/18 , B60K6/28 , B60T13/58 , B60T17/18 , B60W10/06 , B60W50/14
摘要： An electrical regeneration and vehicle deceleration control method includes operating an electrified powertrain in normal or maximum regeneration modes associated with lesser and greater electrical regeneration and vehicle deceleration rates, respectively, receiving an input from a driver of the vehicle indicative of a request to enable the maximum regeneration mode, detecting a status indicative of an availability of the maximum regeneration mode, and in response to receiving the request and based on the status of the maximum regeneration mode and a current vehicle deceleration rate: (i) operating the electrified powertrain in either the maximum regeneration mode or a normal regeneration mode, (ii) selectively outputting a message to the driver indicative of the status of the maximum regeneration mode, and (iii) selectively commanding a hydraulic brake system of the vehicle to generate brake force based on a driver-expected vehicle deceleration rate associated with the operative regeneration mode.

13. 发明授权

US5649638A Device enabling two containers to be joined with each other and container having such a device 失效
标题翻译：使两个容器彼此连接的装置和具有这种装置的容器
公开(公告)号：US5649638A
公开(公告)日：1997-07-22
申请号：US445291
申请日：1995-05-19
申请人： Richard Roy , Marie-Christine Paris
发明人： Richard Roy , Marie-Christine Paris
IPC分类号： F42B3/02 , F42B5/38 , F16L21/00
CPC分类号： F42B3/02 , F42B5/38
摘要： A device for joining a first face of a first container to a second face of a second container, in which the first face and the second face are alignable along a longitudinal axis, includes a plurality of hooks and a hook receiving portion. The plurality of hooks are spaced around a periphery of the first face of the first container. The hooks have tips and are movable in a direction parallel to the longitudinal axis. The hook receiving portion is disposed around a periphery of the second face of the second container. The hook receiving portion includes a groove shaped to receive the tips of the hooks so that the first container can be joined to the second container. As a result, the device permits two containers to be joined securely yet disassembled quickly.
摘要翻译：用于将第一容器的第一面与第二容器的第二面接合的装置，其中第一面和第二面沿着纵向轴线对准，包括多个钩和钩接收部。多个钩子围绕第一容器的第一面的周边间隔开。钩具有尖端并且可在平行于纵向轴线的方向上移动。钩接收部设置在第二容器的第二面的周围。钩接收部分包括成形为接收钩的尖端的槽，使得第一容器可以接合到第二容器。结果，该装置允许两个容器牢固地连接并快速拆卸。

14. 发明授权

US07379381B1 State maintenance pulsing for a memory device 失效
标题翻译：用于存储设备的状态维护脉冲
公开(公告)号：US07379381B1
公开(公告)日：2008-05-27
申请号：US11175057
申请日：2005-07-05
申请人： Richard Roy , Farid Nemati
发明人： Richard Roy , Farid Nemati
IPC分类号： G11C8/00
CPC分类号： G11C11/404 , G11C11/406 , G11C11/40622
摘要： State maintenance of a memory cell and, more particularly, state maintenance pulsing of identified memory cells more frequently than other memory cells, is described. A memory array includes an array of memory cells. State maintenance circuitry is coupled to the array of memory cells. The state maintenance circuitry is configured to select between a first restore address and a second restore address. In a given operation cycle, the first restore address is associated with a first line in the array of memory cells, and the second restore address is associated with a second line in the array of memory cells. The first line has first memory cells coupled thereto. The second line has second memory cells coupled thereto. The first memory cells are capable of passing a threshold retention time with a first frequency of restore cycling. The second memory cells are capable of passing the threshold retention time with a second frequency of restore cycling. The second frequency of restore cycling is greater than the first frequency of restore cycling.
摘要翻译：描述了存储器单元的状态维护，更具体地，描述了比其他存储器单元更频繁地状态维持所标识的存储器单元的脉冲。存储器阵列包括存储器单元阵列。状态维护电路耦合到存储器单元阵列。状态维护电路被配置为在第一恢复地址和第二恢复地址之间进行选择。在给定的操作周期中，第一恢复地址与存储器单元阵列中的第一行相关联，并且第二恢复地址与存储器单元阵列中的第二行相关联。第一行具有耦合到其上的第一存储单元。第二行具有与其耦合的第二存储单元。第一存储器单元能够以第一恢复循环频率通过阈值保持时间。第二存储器单元能够以第二恢复循环频率通过阈值保持时间。恢复循环的第二个频率大于恢复循环的第一个频率。

15. 发明授权

US07319622B1 Bitline shielding for thyristor-based memory 失效
标题翻译：基于晶闸管的存储器的位线屏蔽
公开(公告)号：US07319622B1
公开(公告)日：2008-01-15
申请号：US11174813
申请日：2005-07-05
申请人： Richard Roy
发明人： Richard Roy
IPC分类号： G11C7/00
CPC分类号： G11C7/02 , G11C5/025 , G11C7/12 , G11C7/18 , G11C2211/5614
摘要： Method and apparatus for writing and reading information to and from a memory cell. For a read, a write path is used to electrically shield at least one adjacent bitline from a bitline associated with the memory cell to be read, and the memory cell is read while the at least one adjacent bitline is electrically shielded from the bitline associated with the memory cell being read. For a write, the write path is used to electrically shield at the least one adjacent bitline from a bitline associated with a memory cell to be written to; memory cells coupled to a wordline are read and buffered; and the memory cell is written to while the at least one adjacent bitline is electrically shielded from the writing to the memory cell.
摘要翻译：用于向存储器单元写入和读取信息的方法和装置。对于读取，写入路径用于将电子屏蔽来自与要读取的存储器单元相关联的位线的至少一个相邻位线，并且读取存储器单元，同时将至少一个相邻位线与与...相关联的位线电屏蔽正在读取存储单元。对于写入，写入路径用于在与要写入的存储器单元相关联的位线的至少一个相邻位线处电屏蔽; 耦合到字线的存储单元被读取和缓冲; 并且所述存储单元被写入，而所述至少一个相邻位线与所述存储单元的写入电屏蔽。

16. 发明授权

US07158425B2 System and method for providing a redundant memory array in a semiconductor memory integrated circuit 失效
标题翻译：一种用于在半导体存储器集成电路中提供冗余存储器阵列的系统和方法
公开(公告)号：US07158425B2
公开(公告)日：2007-01-02
申请号：US10628896
申请日：2003-07-28
申请人： Chao-Wu Chen , Richard Roy , Wasim Khaled
发明人： Chao-Wu Chen , Richard Roy , Wasim Khaled
IPC分类号： G11C7/00
CPC分类号： G11C29/846 , G11C29/842
摘要： A memory device that has an internal memory array provides timing signals to control the output timing of one or more redundant memory blocks that substitute for defective memory blocks in the internal memory array. In one embodiment, the internal memory array includes a pipelined output stage, and the timing signals ensure that the data is output from the memory devices in the order memory access requests are issued, even when the latency of the redundant memory blocks is less than the latency of the main memory array by up to two clock periods. In one embodiment, a FIFO memory queues the output data of the redundant memory blocks waiting to be output.
摘要翻译：具有内部存储器阵列的存储器件提供定时信号以控制代替内部存储器阵列中的缺陷存储器块的一个或多个冗余存储器块的输出定时。在一个实施例中，内部存储器阵列包括流水线输出级，并且定时信号确保以存储器访问请求的顺序从存储器件输出数据，即使当冗余存储器块的等待时间小于主存储器阵列延迟最多两个时钟周期。在一个实施例中，FIFO存储器对等待输出的冗余存储器块的输出数据进行排队。

17. 发明授权

US06236618B1 Centrally decoded divided wordline (DWL) memory architecture 有权
标题翻译：集中解码分割字线（DWL）内存架构
公开(公告)号：US06236618B1
公开(公告)日：2001-05-22
申请号：US09542033
申请日：2000-04-03
申请人： Richard Roy
发明人： Richard Roy
IPC分类号： G11C800
CPC分类号： G11C8/14
摘要： A divided wordline memory architecture for memory compilers wherein a main memory array is organized into a plurality of local memory arrays. A plurality of local wordline decoders are provided such that each local memory array is associated with a local wordline decoder for selecting local wordline segments. Main wordline signals are generated based on a first portion of wordline address signals in a main wordline decoder provided as an integrated centrally located decoder structure. A combination of Plane signals, Set signals, or both, which are generated in the integrated centrally located decoder structure, are provided to the local wordline decoder in conjunction with a portion of the main wordline signals for selecting a local wordline segment based on a select main wordline signal and one of a select Plane signal, a select Set signal, or a combination of both.
摘要翻译：一种用于存储器编译器的分割字线存储器架构，其中主存储器阵列被组织成多个本地存储器阵列。提供多个本地字线解码器，使得每个本地存储器阵列与用于选择本地字线段的本地字线解码器相关联。主字线信号基于作为集成的中央定位的解码器结构提供的主字线解码器中的字线地址信号的第一部分生成。在集成的位于中心的解码器结构中生成的平面信号，设置信号或两者的组合，与主字线信号的一部分相结合地提供给本地字线解码器，用于基于选择来选择本地字线段主字线信号和选择平面信号之一，选择设置信号或两者的组合。

18. 发明授权

US5926895A Vacuum cleaner hose cleaning brush 失效
标题翻译：吸尘器软管清洁刷
公开(公告)号：US5926895A
公开(公告)日：1999-07-27
申请号：US693711
申请日：1996-08-07
申请人： Richard Roy
发明人： Richard Roy
IPC分类号： A46B5/00 , B08B9/04 , B25G1/02 , A46B5/02 , B08B9/02
CPC分类号： B25G1/02 , A46B5/0062 , A46B5/007 , B08B9/0436 , A46B2200/3006
摘要： The subject invention pertains to a tool that may be used for cleaning hoses from vacuum cleaner machines. The tool comprises a brush or similar cleaning device attached to an end of a length a semi-rigid tube. In use, the cleaning tool is inserted into a vacuum cleaner hose after detachment of the hose from the vacuum cleaner; the inside surface of the hose is then cleaned of dust and other entrapped particles.
摘要翻译：本发明涉及一种可用于从真空吸尘器机器清洁软管的工具。该工具包括连接到长度为半刚性管的端部的刷子或类似的清洁装置。在使用中，将软管与真空吸尘器分离后，将清洁工具插入真空吸尘器软管中; 然后将软管的内表面清除灰尘和其他被夹带的颗粒。

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