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11. 发明授权

US4240096A Fluorine-doped P type silicon 失效
标题翻译：氟掺杂P型硅
公开(公告)号：US4240096A
公开(公告)日：1980-12-16
申请号：US952777
申请日：1978-10-19
申请人： Shunichi Hiraki , Kuniaki Kumamaru , Masaharu Aoyama , Toshio Yonezawa
发明人： Shunichi Hiraki , Kuniaki Kumamaru , Masaharu Aoyama , Toshio Yonezawa
IPC分类号： H01L21/265 , H01L21/761 , H01L29/167 , H01L29/8605
CPC分类号： H01L21/26506 , H01L21/761 , H01L29/167 , H01L29/8605
摘要： A semiconductor device comprising a fluorine ion implantation region which is selectively formed in a semiconductor region and further activated. The fluorine ion implantation region is adapted for use as a high resistance layer or electrical isolation layer.
摘要翻译：一种半导体器件，包括选择性地形成在半导体区域中并进一步活化的氟离子注入区。氟离子注入区适合用作高电阻层或电隔离层。

12. 发明授权

US4728627A Method of making multilayered interconnects using hillock studs formed by sintering 失效
标题翻译：使用通过烧结形成的小丘柱制造多层互连的方法
公开(公告)号：US4728627A
公开(公告)日：1988-03-01
申请号：US870117
申请日：1986-06-03
申请人： Yasukazu Mase , Masahiro Abe , Masaharu Aoyama
发明人： Yasukazu Mase , Masahiro Abe , Masaharu Aoyama
IPC分类号： H01L23/522 , H01L21/3205 , H01L21/768 , H01L27/00 , H01L21/28 , H01L21/302
CPC分类号： H01L21/76885 , H01L21/76877 , Y10S438/937
摘要： A method of manufacturing a semiconductor device comprising the steps of preparing a semiconductor substrate on which a first insulation film is formed, forming a first conductive layer on the first insulation film, forming a hillock of the first conductive layer, forming a second insulation film on the structure, removing that portion of the second insulation film, in self-align with the hillock, which is on the hillock, thereby forming a contact hole leading to the first conductive layer, and forming on the structure a second conductive layer extending into the contact hole and contacting the first conductive layer.
摘要翻译：一种制造半导体器件的方法，包括以下步骤：制备其上形成有第一绝缘膜的半导体衬底，在第一绝缘膜上形成第一导电层，形成第一导电层的小丘，在第一绝缘膜上形成第二绝缘膜所述结构将所述第二绝缘膜的所述部分与所述小丘上的小丘自对准，从而形成通向所述第一导电层的接触孔，并且在所述结构上形成延伸到所述第一导电层的第二导电层接触孔并与第一导电层接触。

13. 发明授权

US4613888A Semiconductor device of multilayer wiring structure 失效
标题翻译：多层布线结构半导体器件
公开(公告)号：US4613888A
公开(公告)日：1986-09-23
申请号：US634030
申请日：1984-07-24
申请人： Yasukazu Mase , Masahiro Abe , Masaharu Aoyama , Takashi Ajima
发明人： Yasukazu Mase , Masahiro Abe , Masaharu Aoyama , Takashi Ajima
IPC分类号： H01L21/768 , H01L21/302 , H01L21/3065 , H01L21/316 , H01L23/532 , H01L21/44 , H01L21/47 , H01L21/94
CPC分类号： H01L23/5329 , H01L2924/0002
摘要： A semiconductor device is disclosed which includes a multilayer formed of a hard inorganic main insulation film and a soft subinsulation film as insulation interlayers, and a hard inorganic insulation film as a final passivation film. The final passivation film is directly deposited on the hard inorganic main insulation film of the multilayer.
摘要翻译：公开了一种半导体器件，其包括由作为绝缘夹层的硬质无机主绝缘膜和软嵌层膜形成的多层，以及作为最终钝化膜的硬质无机绝缘膜。最终的钝化膜直接沉积在多层的硬质无机主绝缘膜上。

14. 发明授权

US5175115A Method of controlling metal thin film formation conditions 失效
标题翻译：控制金属薄膜形成条件的方法
公开(公告)号：US5175115A
公开(公告)日：1992-12-29
申请号：US654488
申请日：1991-02-13
申请人： Masahiro Abe , Yasukazu Mase , Toshihiko Katsura , Masaharu Aoyama
发明人： Masahiro Abe , Yasukazu Mase , Toshihiko Katsura , Masaharu Aoyama
IPC分类号： H01L21/48
CPC分类号： H01L21/4846
摘要： Measurement of temperature - internal stress characteristics of an Al thin film formed on an Si substrate is performed. The amount of an impurity or impurities mixed in the thin f ilm can be obtained in accordance with the measured characteristics. A migration start temperature of Al atoms in the thin film in the characteristics obtained when the temperature is increased is fed back as information to the thin film formation step, thereby controlling an impurity amount in an atmosphere for forming the thin film.
摘要翻译：进行在Si衬底上形成的Al薄膜的温度 - 内部应力特性的测量。可以根据测量的特性获得混合在薄膜中的杂质或杂质的量。当温度升高时获得的特性中，薄膜中Al原子的迁移开始温度作为信息反馈到薄膜形成步骤，从而控制用于形成薄膜的气氛中的杂质量。

15. 发明授权

US4853760A Semiconductor device having insulating layer including polyimide film 失效
标题翻译：具有包括聚酰亚胺膜的绝缘层的半导体器件
公开(公告)号：US4853760A
公开(公告)日：1989-08-01
申请号：US89959
申请日：1987-08-25
申请人： Masahiro Abe , Masaharu Aoyama , Jiro Ohshima , Takashi Ajima
发明人： Masahiro Abe , Masaharu Aoyama , Jiro Ohshima , Takashi Ajima
IPC分类号： H01L21/768 , H01L21/3105 , H01L21/3115 , H01L21/312 , H01L23/522
CPC分类号： H01L21/3105 , H01L21/31155 , H01L2924/0002
摘要： A semiconductor device has a passivation layer including a polyimide film. Argon ions are implanted in the polyimide film to convert it into an electrically stable insulating film.
摘要翻译：半导体器件具有包括聚酰亚胺膜的钝化层。将氩离子注入到聚酰亚胺膜中以将其转化为电稳定的绝缘膜。

16. 发明授权

US4634496A Method for planarizing the surface of an interlayer insulating film in a semiconductor device 失效
标题翻译：在半导体器件中对层间绝缘膜的表面进行平面化的方法
公开(公告)号：US4634496A
公开(公告)日：1987-01-06
申请号：US797986
申请日：1985-11-14
申请人： Yasukazu Mase , Masahiro Abe , Masaharu Aoyama
发明人： Yasukazu Mase , Masahiro Abe , Masaharu Aoyama
IPC分类号： H01L21/3205 , H01L21/302 , H01L21/3065 , H01L21/3105 , H01L21/311 , H01L21/768 , B44C1/22 , B29C17/08 , C03C15/00 , C03C25/06
CPC分类号： H01L21/31116 , H01L21/31055 , H01L21/76819
摘要： A method for planarizing the surface of an insulation layer deposited on a first interconnection layer to allow a second interconnection layer deposited thereon without causing a breakage of the second interconnection layer. This method is characterized in that at least two insulation films, different in etching characteristics each other, are first formed on the first interconnection layer, and then a resist layer is deposited on the second insulating film. Subsequently, a portion of the resist layer is etched to expose the top surface of the second insulating film, and the second insulating film is selectively and anisotropically etched using the remaining resist layer as a mask. After removing the first insulating film and the remaining resist mark, a third insulating film is deposited to a thickness sufficient to make flat the surface thereof.
摘要翻译：一种用于平坦化沉积在第一互连层上的绝缘层的表面以允许沉积在其上的第二互连层而不引起第二互连层的破损的方法。该方法的特征在于，首先在第一互连层上形成至少两个彼此不同的蚀刻特性的绝缘膜，然后在第二绝缘膜上沉积抗蚀剂层。随后，蚀刻抗蚀剂层的一部分以暴露第二绝缘膜的顶表面，并且使用剩余的抗蚀剂层作为掩模来选择性地和各向异性地蚀刻第二绝缘膜。在去除第一绝缘膜和剩余的抗蚀剂标记之后，沉积第三绝缘膜至足以使其表面平坦的厚度。

17. 发明授权

US4766086A Method of gettering a semiconductor device and forming an isolation region therein 失效
标题翻译：吸收半导体器件并在其中形成隔离区域的方法
公开(公告)号：US4766086A
公开(公告)日：1988-08-23
申请号：US20758
申请日：1987-03-02
申请人： Jiro Ohshima , Shin-ichi Taka , Toshiyo Ito , Masaharu Aoyama
发明人： Jiro Ohshima , Shin-ichi Taka , Toshiyo Ito , Masaharu Aoyama
IPC分类号： H01L29/73 , H01L21/316 , H01L21/322 , H01L21/331 , H01L21/761 , H01L29/732 , H01L21/265 , H01L21/225
CPC分类号： H01L21/3221 , H01L21/761 , Y10S148/024
摘要： In a method of manufacturing a semiconductor device according to the present invention, a given position of a thermal oxide film formed on a monocrystalline silicon layer is opened to expose a surface of the monocrystalline silicon layer to serve as a getter site, a polycrystalline silicon layer is deposited on the thermal oxide film and the surface of the monocrystalline silicon layer, and the polycrystalline silicon layer is oxidized to convert the surface of the monocrystalline silicon layer directly contacting the polycrystalline silicon layer into an oxide film by thermal oxidation. That is, the position of interface between the oxide film and the monocrystalline silicon layer is shifted into the original monocrystalline silicon layer. During thermal oxidation of the polycrystalline silicon layer, a plurality of crystal defects to serve as getter sites are generated deeper than those generated by a conventional implagetter method in the monocrystalline silicon layer. In addition, the crystal defects generated in the manner described above do not extend to the surrounding region by subsequent annealing so that a region of the crystal defects is limited.
摘要翻译：在根据本发明的半导体器件的制造方法中，形成在单晶硅层上的热氧化膜的给定位置被打开以暴露单晶硅层的表面以用作吸气部位，多晶硅层沉积在热氧化膜和单晶硅层的表面上，并且多晶硅层被氧化，以通过热氧化将直接与多晶硅层接触的单晶硅层的表面转化为氧化膜。也就是说，氧化膜和单晶硅层之间的界面的位置被转移到原始的单晶硅层中。在多晶硅层的热氧化过程中，产生比用于单晶硅层中常规的投影仪方法产生的多个晶体缺陷作为吸气位置。此外，以上述方式产生的晶体缺陷通过随后的退火不会延伸到周围区域，使得晶体缺陷的区域受到限制。

18. 发明授权

US5266526A Method of forming trench buried wiring for semiconductor device 失效
标题翻译：形成用于半导体器件的沟槽埋地布线的方法
公开(公告)号：US5266526A
公开(公告)日：1993-11-30
申请号：US854812
申请日：1992-03-19
申请人： Masaharu Aoyama , Masahiro Abe
发明人： Masaharu Aoyama , Masahiro Abe
IPC分类号： H01L21/3205 , H01L21/288 , H01L21/74 , H01L21/768 , H01L23/52 , H01L21/441 , H01L21/469
CPC分类号： H01L21/7688 , H01L21/743 , Y10S148/10
摘要： A method of forming a trench buried wiring on a semiconductor device. The method includes the steps of: forming a trench in a first insulating film formed on a semiconductor substrate, by using as a mask a photoresist layer, the trench having substantially an upright step; depositing a first electrode material on the surface of the photoresist layer and on the bottom of the trench, while leaving the photoresist layer; removing the photoresist layer and the first electrode material on the photoresist layer while leaving the first electrode material only on the bottom of the trench; and filling a second electrode material in the trench to form a composite electrode with the second electrode material being superposed on the first electrode material.
摘要翻译：一种在半导体器件上形成沟槽埋入布线的方法。该方法包括以下步骤：在形成在半导体衬底上的第一绝缘膜中形成沟槽，通过使用光刻胶层作为掩模，该沟槽具有基本上直立的步骤; 在光致抗蚀剂层的表面上和沟槽的底部上沉积第一电极材料，同时留下光致抗蚀剂层; 在光致抗蚀剂层上除去光致抗蚀剂层和第一电极材料，同时仅在沟槽的底部留下第一电极材料; 以及在沟槽中填充第二电极材料以形成复合电极，其中第二电极材料叠置在第一电极材料上。

19. 发明授权

US4717682A Method of manufacturing a semiconductor device with conductive trench sidewalls 失效
标题翻译：制造具有导电沟槽侧壁的半导体器件的方法
公开(公告)号：US4717682A
公开(公告)日：1988-01-05
申请号：US830928
申请日：1986-02-19
申请人： Shin-ichi Taka , Jiro Ohshima , Masahiro Abe , Masaharu Aoyama
发明人： Shin-ichi Taka , Jiro Ohshima , Masahiro Abe , Masaharu Aoyama
IPC分类号： H01L21/76 , H01L21/265 , H01L21/302 , H01L21/3065 , H01L21/74 , H01L21/283
CPC分类号： H01L21/743
摘要： A method of manufacturing a semiconductor device, comprising the steps of sequentially forming a buried region and an epitaxial layer on a major surface of a semiconductor substrate, forming a conductive layer along an annular trench extending to the buried region, filling the annular trench with an insulating material and forming a functional element in said epitaxial layer surrounded by said buried region and said insulating material within said annular trench. In this method, the step of forming the conductive layer along the annular trench is carried out by the steps of forming an annular trench extending through said buried region, and depositing a conductive layer on only a side wall surface of said annular trench.
摘要翻译：一种制造半导体器件的方法，包括以下步骤：在半导体衬底的主表面上依次形成掩埋区域和外延层，沿着延伸到掩埋区域的环形沟槽形成导电层，用环形沟槽填充绝缘材料，并在由所述掩埋区域围绕的所述外延层中形成功能元件，并在所述环形沟槽内形成所述绝缘材料。在该方法中，沿着环形沟槽形成导电层的步骤是通过形成延伸穿过所述掩埋区域的环形沟槽以及仅在所述环形沟槽的侧壁表面上沉积导电层的步骤来执行的。

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