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11. 发明授权

US08450195B2 Method of reducing floating body effect of SOI MOS device via a large tilt ion implantation 有权
标题翻译：通过大型倾斜离子注入降低SOI MOS器件浮体效应的方法
公开(公告)号：US08450195B2
公开(公告)日：2013-05-28
申请号：US12937258
申请日：2010-07-14
申请人： Jing Chen , Xiaolu Huang , Jiexin Luo , Qingqing Wu , Xi Wang
发明人： Jing Chen , Xiaolu Huang , Jiexin Luo , Qingqing Wu , Xi Wang
IPC分类号： H01L21/425
CPC分类号： H01L21/26586 , H01L29/66545 , H01L29/78615
摘要： The present invention discloses a method of reducing floating body effect of SOI MOS device via a large tilt ion implantation including a step of: (a) implanting ions in an inclined direction into an NMOS with a buried insulation layer forming a highly doped P region under a source region of the NMOS and above the buried insulation layer, wherein the angle between a longitudinal line of the NMOS and the inclined direction is ranging from 15 to 45 degrees. Through this method, the highly doped P region under the source region and a highly doped N region form a tunnel junction so as to reduce the floating body effect. Furthermore, the chip area will not be increased, manufacturing process is simple and the method is compatible with conventional CMOS process.
摘要翻译：本发明公开了一种通过大的倾斜离子注入降低SOI MOS器件的浮体效应的方法，包括以下步骤：（a）将倾斜方向的离子注入到具有形成高掺杂P区的掩埋绝缘层的NMOS中 NMOS的源极区域和掩埋绝缘层之上，其中NMOS的纵向线与倾斜方向之间的角度为15至45度。通过这种方法，源区下的高掺杂P区和高掺杂N区形成隧道结，以减少浮体效应。此外，芯片面积不会增加，制造工艺简单，方法与常规CMOS工艺兼容。

12. 发明授权

US08354714B2 SOI MOS device having BTS structure and manufacturing method thereof 有权
标题翻译：具有BTS结构的SOI MOS器件及其制造方法
公开(公告)号：US08354714B2
公开(公告)日：2013-01-15
申请号：US13132879
申请日：2010-09-07
申请人： Jing Chen , Jiexin Luo , Qingqing Wu , Xiaolu Huang , Xi Wang
发明人： Jing Chen , Jiexin Luo , Qingqing Wu , Xiaolu Huang , Xi Wang
IPC分类号： H01L29/76 , H01L31/062
CPC分类号： H01L29/78615 , H01L29/458 , H01L29/78621
摘要： The present invention discloses a SOI MOS device having BTS structure and manufacturing method thereof. The source region of the SOI MOS device comprises: two heavily doped N-type regions, a heavily doped P-type region formed between the two heavily doped N-type regions, a silicide formed above the heavily doped N-type regions and the heavily doped P-type region, and a shallow N-type region which is contact to the silicide; an ohmic contact is formed between the heavily doped P-type region and the silicide thereon to release the holes accumulated in body region of the SOI MOS device and eliminate floating body effects thereof without increasing the chip area and also overcome the disadvantages such as decreased effective channel width of the devices in the BTS structure of the prior art. The manufacturing method comprises steps of: forming a heavily doped P-type region via ion implantation, forming a metal layer above the source region and forming a silicide via the heat treatment between the metal layer and the Si underneath. The device in the present invention could be fabricated via simplified fabricating process with great compatibility with traditional CMOS technology.
摘要翻译：本发明公开了一种具有BTS结构的SOI MOS器件及其制造方法。 SOI MOS器件的源极区域包括：两个重掺杂N型区域，形成在两个重掺杂N型区域之间的重掺杂P型区域，在重掺杂N型区域上形成的硅化物，掺杂P型区域和与硅化物接触的浅N型区域; 在重掺杂的P型区域和其上的硅化物之间形成欧姆接触以释放积聚在SOI MOS器件的体区中的空穴，并且消除其浮体效应而不增加芯片面积，并且还克服了诸如降低有效性现有技术的BTS结构中的设备的信道宽度。该制造方法包括以下步骤：通过离子注入形成重掺杂的P型区，在源区上方形成金属层，并通过金属层与Si之间的Si之间的热处理形成硅化物。本发明中的器件可以通过简化的制造工艺制造，与传统CMOS技术具有很好的兼容性。

13. 发明授权

US08354310B2 SOI MOS device having a source/body ohmic contact and manufacturing method thereof 有权
标题翻译：具有源/体欧姆接触的SOI MOS器件及其制造方法
公开(公告)号：US08354310B2
公开(公告)日：2013-01-15
申请号：US13131126
申请日：2010-09-07
申请人： Jing Chen , Qingqing Wu , Jiexin Luo , Xiaolu Huang , Xi Wang
发明人： Jing Chen , Qingqing Wu , Jiexin Luo , Xiaolu Huang , Xi Wang
IPC分类号： H01L21/00 , H01L21/84 , H01L21/336 , H01L21/8234 , H01L21/331
CPC分类号： H01L29/458 , H01L29/66772 , H01L29/78615 , H01L29/78621
摘要： The present invention discloses a manufacturing method of SOI MOS device having a source/body ohmic contact. The manufacturing method comprises steps of: firstly creating a gate region, then performing high dose source and drain light doping to form the lightly doped N-type source region and lightly doped N-type drain region; forming an insulation spacer surrounding the gate region; performing large tilt heavily-doped P ion implantation in an inclined direction via a mask with an opening at the position of the N type Si source region and implanting P ions into the space between the N type Si source region and the N type drain region to form a heavily-doped P-type region; finally forming a metal layer on the N type Si source region, then allowing the reaction between the metal layer and the remained Si material underneath to form silicide by heat treatment. In the device prepared by the method of the present invention, an ohmic contact is formed between the silicide and the heavily-doped P-type region nearby in order to release the holes accumulated in body region of the SOI MOS device and eliminate floating body effects thereof. Besides, the device of the present invention also has following advantages, such as limited chip area, simplified fabricating process and great compatibility with traditional CMOS technology.
摘要翻译：本发明公开了一种具有源/体欧姆接触的SOI MOS器件的制造方法。该制造方法包括以下步骤：首先产生栅极区域，然后进行高剂量源和漏极掺杂以形成轻掺杂的N型源极区域和轻掺杂的N型漏极区域; 形成围绕所述栅极区域的绝缘间隔物; 通过在N型Si源极区域的位置处具有开口的掩模在倾斜方向上进行大倾斜重掺杂P离子注入，并且将P离子注入到N型Si源极区域和N型漏极区域之间的空间中，以形成重掺杂P型区; 最后在N型Si源区上形成金属层，然后通过热处理使金属层与下面残留的Si材料之间的反应形成硅化物。在通过本发明的方法制备的器件中，在硅化物和附近的重掺杂P型区域之间形成欧姆接触，以释放积累在SOI MOS器件的体区中的空穴并消除浮体效应其中。此外，本发明的器件还具有以下优点，例如有限的芯片面积，简化的制造工艺和与传统CMOS技术的很好的兼容性。

14. 发明申请

US20120009741A1 SOI MOS DEVICE HAVING A SOURCE/BODY OHMIC CONTACT AND MANUFACTURING METHOD THEREOF 有权
标题翻译：具有源/体OHMIC接触的SOI MOS器件及其制造方法
公开(公告)号：US20120009741A1
公开(公告)日：2012-01-12
申请号：US13131126
申请日：2010-09-07
申请人： Jing Chen , Qingqing Wu , Jiexin Luo , Xiaolu Huang , Xi Wang
发明人： Jing Chen , Qingqing Wu , Jiexin Luo , Xiaolu Huang , Xi Wang
IPC分类号： H01L21/336
CPC分类号： H01L29/458 , H01L29/66772 , H01L29/78615 , H01L29/78621
摘要： The present invention discloses a manufacturing method of SOI MOS device having a source/body ohmic contact. The manufacturing method comprises steps of: firstly creating a gate region, then performing high dose source and drain light doping to form the lightly doped N-type source region and lightly doped N-type drain region; forming an insulation spacer surrounding the gate region; performing large tilt heavily-doped P ion implantation in an inclined direction via a mask with an opening at the position of the N type Si source region and implanting P ions into the space between the N type Si source region and the N type drain region to form a heavily-doped P-type region; finally forming a metal layer on the N type Si source region, then allowing the reaction between the metal layer and the remained Si material underneath to form silicide by heat treatment. In the device prepared by the method of the present invention, an ohmic contact is formed between the silicide and the heavily-doped P-type region nearby in order to release the holes accumulated in body region of the SOI MOS device and eliminate floating body effects thereof. Besides, the device of the present invention also has following advantages, such as limited chip area, simplified fabricating process and great compatibility with traditional CMOS technology.
摘要翻译：本发明公开了一种具有源/体欧姆接触的SOI MOS器件的制造方法。该制造方法包括以下步骤：首先产生栅极区域，然后进行高剂量源和漏极掺杂以形成轻掺杂的N型源极区域和轻掺杂的N型漏极区域; 形成围绕所述栅极区域的绝缘间隔物; 通过在N型Si源极区域的位置处具有开口的掩模在倾斜方向上进行大倾斜重掺杂P离子注入，并且将P离子注入到N型Si源极区域和N型漏极区域之间的空间中，以形成重掺杂P型区; 最后在N型Si源区上形成金属层，然后通过热处理使金属层与下面残留的Si材料之间的反应形成硅化物。在通过本发明的方法制备的器件中，在硅化物和附近的重掺杂P型区域之间形成欧姆接触，以释放积累在SOI MOS器件的体区中的空穴并消除浮体效应其中。此外，本发明的器件还具有以下优点，例如有限的芯片面积，简化的制造工艺和与传统CMOS技术的很好的兼容性。

15. 发明申请

US20130054210A1 Method for Determining BSIMSOI4 DC Model Parameters 有权
标题翻译：确定BSIMSOI4直流模型参数的方法
公开(公告)号：US20130054210A1
公开(公告)日：2013-02-28
申请号：US13696455
申请日：2011-09-25
申请人： Jing Chen , Qingqing Wu , Jiexin Luo , Zhan Chai , Xi Wang
发明人： Jing Chen , Qingqing Wu , Jiexin Luo , Zhan Chai , Xi Wang
IPC分类号： G06F17/10
CPC分类号： G01R31/2628 , G01R31/2603 , G06F17/5036
摘要： The present invention provides a method for determining BSIMSOI4 Direct Current (DC) model parameters, where a plurality of Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices of a body leading-out structure and of different sizes, and a plurality of MOSFET devices of a floating structure and of different sizes are provided; Id-Vg-Vp, Id/Ip-Vd-Vg, Ig-Vg-Vd, Ig-Vp, Ip-Vg-vd, Is/Id-Vp, and Id/Ip-Vp-Vd properties of all the MOSFET devices of a body leading-out structure, and Id-Vg-Vp, Id-Vd-Vg, and Ig-Vg-Vd properties of all the MOSFET devices of a floating structure are measured; electrical property curves without a self-heating effect of each MOSFET device of a body leading-out structure and each MOSFET device of a floating structure are obtained; and then DC parameters of a BSIMSOI4 model are successively extracted according to specific steps. In the present invention, proper test curves are successively selected according to model equations, and various kinds of parameters are successively determined, thereby accurately and effectively extracting the DC parameters of the BSIMSOI4 model.
摘要翻译：本发明提供了一种用于确定BSIMSOI4直流（DC）模型参数的方法，其中，体内引出结构和不同尺寸的多个金属氧化物半导体场效应晶体管（MOSFET）器件和多个MOSFET器件提供浮动结构和不同尺寸; 所有MOSFET器件的Id-Vg-Vp，Id / Ip-Vd-Vg，Ig-Vg-Vd，Ig-Vp，Ip-Vg-vd，Is / Id-Vp和Id / Ip-Vp-Vd特性测量浮体结构的所有MOSFET器件的体导体结构和Id-Vg-Vp，Id-Vd-Vg和Ig-Vg-Vd特性; 获得不具有体引出结构的每个MOSFET器件和浮置结构的每个MOSFET器件的自发热效应的电性能曲线; 然后根据具体步骤依次提取BSIMSOI4模型的DC参数。在本发明中，根据模型方程依次选择适当的试验曲线，并连续确定各种参数，从而准确有效地提取BSIMSOI4型号的直流参数。

16. 发明申请

US20130054219A1 Equivalent Electrical Model of SOI FET of Body Leading-Out Structure, and Modeling Method Thereof 审中-公开
标题翻译：体引出结构SOI FET的等效电气模型及其建模方法
公开(公告)号：US20130054219A1
公开(公告)日：2013-02-28
申请号：US13696416
申请日：2011-09-25
申请人： Jing Chen , Qingqing Wu , Jiexin Luo , Zhan Chai , Xi Wang
发明人： Jing Chen , Qingqing Wu , Jiexin Luo , Zhan Chai , Xi Wang
IPC分类号： G06G7/62
CPC分类号： G06F17/5036
摘要： The present invention provides an equivalent electrical model of a Silicon On Insulator (SOI) Field Effect Transistor (FET) of a body leading-out structure, and a modeling method thereof. The equivalent electrical model is formed by an internal FET and an external FET connected in parallel, where the SOI FET of a body leading-out structure is divided into a body leading-out part and a main body part, the internal FET represents a parasitic transistor of the body leading-out part, and the external FET represents a normal transistor of the main body part. The equivalent electrical model provided in the present invention completely includes the influence of parts of a physical structure of the SOIMOSFET device of a body leading-out structure, that is, the body leading-out part and the main body part, on the electrical properties, thereby improving a fitting effect of the model on the electrical properties of the device.
摘要翻译：本发明提供了体导出结构的绝缘体硅（SOI）场效应晶体管（FET）的等效电气模型及其建模方法。等效电气模型由并联连接的内部FET和外部FET形成，其中主体引出结构的SOI FET被分为主体引出部分和主体部分，内部FET表示寄生体外引出部分的晶体管，外部FET表示主体部分的正常晶体管。本发明提供的等效电气模型完全包括体导体结构的SOIMOSFET装置的物理结构的部分，即主体引出部分和主体部分对电性能的影响，从而提高了模型对装置的电气特性的拟合效果。

17. 发明申请

US20130152033A1 TCAD Emulation Calibration Method of SOI Field Effect Transistor 失效
标题翻译： SOI场效应晶体管的TCAD仿真校准方法
公开(公告)号：US20130152033A1
公开(公告)日：2013-06-13
申请号：US13696401
申请日：2011-09-23
申请人： Zhan Chai , Jing Chen , Jiexin Luo , Qingqing Wu , Xi Wang
发明人： Zhan Chai , Jing Chen , Jiexin Luo , Qingqing Wu , Xi Wang
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5036 , H01L22/20
摘要： The present invention provides a Technology Computer Aided Design (TCAD) emulation calibration method of a Silicon On Insulator (SOI) field effect transistor, where process emulation Metal Oxide Semiconductor (MOS) device structures with different channel lengths Lgate are obtained by establishing a TCAD process emulation program; based on the process emulation MOS device structures, the process emulation MOS device structures are calibrated according to a Transmission Electron Microscope (TEM) test result, a secondary ion mass spectrometer (SIMS) test result, a Capacitor Voltage (CV) test result, a WAT test result, and a square resistance test result of an actual device, so as to complete TCAD emulation calibration of key electrical parameters of an SOI field effect transistor. Through the calibration method consistent with the present invention, in the same SOI process, TCAD emulation results of key parameters Vt and Idsat of MOSFETs of different sizes all meet a high-precision requirement that an error is less than 10%; moreover, accurate and effective pretest can be implement in the case of multiple splits, thereby providing effective guidance for research, development and optimization of a new process flow.
摘要翻译：本发明提供了一种硅绝缘体（SOI）场效应晶体管的技术计算机辅助设计（TCAD）仿真校准方法，其中通过建立TCAD工艺获得具有不同沟道长度Lgate的工艺仿真金属氧化物半导体（MOS）器件结构仿真程序; 基于过程仿真MOS器件结构，根据透射电子显微镜（TEM）测试结果，二次离子质谱仪（SIMS）测试结果，电容器电压（CV）测试结果， WAT测试结果和实际器件的方形电阻测试结果，以完成SOI场效应晶体管关键电参数的TCAD仿真校准。通过与本发明一致的校准方法，在相同的SOI工艺中，不同尺寸的MOSFET的关键参数Vt和Idsat的TCAD仿真结果均满足误差小于10％的高精度要求; 此外，在多次拆分的情况下可以实现准确有效的预测试，从而为新工艺流程的研究，开发和优化提供有力的指导。

18. 发明申请

US20130054209A1 Modeling Method of SPICE Model Series of SOI FET 有权
标题翻译： SOI FET的SPICE模型系列建模方法
公开(公告)号：US20130054209A1
公开(公告)日：2013-02-28
申请号：US13696437
申请日：2011-09-25
申请人： Jing Chen , Qingqing Wu , Jiexin Luo , Zhan Chai , Xi Wang
发明人： Jing Chen , Qingqing Wu , Jiexin Luo , Zhan Chai , Xi Wang
IPC分类号： G06F17/10
CPC分类号： G06F17/5036
摘要： The present invention provides a modeling method of a SPICE model series of a Silicon On Insulator (SOI) Field Effect Transistor (FET), where auxiliary devices are designed and fabricated, electrical property data is measured, intermediate data is obtained, model parameters are extracted based on the intermediate data, a SPICE model of an SOI FET of a floating structure is established, model parameters are extracted by using the intermediate data and data of the auxiliary devices, a macro model is complied, and a SPICE model of an SOI FET of a body leading-out structure is established. The modeling method provided in the present invention takes an influence of a parasitic transistor of a leading-out part in a body leading-out structure into consideration, and model series established by using the method can more accurately reflect actual operating conditions and electrical properties of the SOI FET of a body leading-out structure and the SOI FET of a floating structure, thereby improving fitting effects of the models.
摘要翻译：本发明提供了一种在绝缘体上硅（SOI）场效应晶体管（FET）的SPICE模型系列的建模方法，其中设计和制造辅助装置，测量电性能数据，获得中间数据，提取模型参数基于中间数据，建立了浮动结构的SOI FET的SPICE模型，通过使用辅助设备的中间数据和数据，宏模型以及SOI FET的SPICE模型来提取模型参数建立了身体导出结构。本发明提供的建模方法考虑了体导出结构中的导出部分的寄生晶体管的影响，并且通过使用该方法建立的模型系列可以更准确地反映实际的操作条件和电气特性主体引出结构的SOI FET和浮动结构的SOI FET，从而提高了模型的拟合效果。

19. 发明授权

US09953118B2 Modeling method of SPICE model series of SOI FET 有权
公开(公告)号：US09953118B2
公开(公告)日：2018-04-24
申请号：US13696437
申请日：2011-09-25
申请人： Jing Chen , Qingqing Wu , Jiexin Luo , Zhan Chai , Xi Wang
发明人： Jing Chen , Qingqing Wu , Jiexin Luo , Zhan Chai , Xi Wang
IPC分类号： G06F17/10 , G06F17/50
CPC分类号： G06F17/5036
摘要： The present invention provides a modeling method of a SPICE model series of a Silicon On Insulator (SOI) Field Effect Transistor (FET), where auxiliary devices are designed and fabricated, electrical property data is measured, intermediate data is obtained, model parameters are extracted based on the intermediate data, a SPICE model of an SOI FET of a floating structure is established, model parameters are extracted by using the intermediate data and data of the auxiliary devices, a macro model is complied, and a SPICE model of an SOI FET of a body leading-out structure is established. The modeling method provided in the present invention takes an influence of a parasitic transistor of a leading-out part in a body leading-out structure into consideration, and model series established by using the method can more accurately reflect actual operating conditions and electrical properties of the SOI FET of a body leading-out structure and the SOI FET of a floating structure, thereby improving fitting effects of the models.

20. 发明授权

US09134361B2 Method for determining BSIMSOI4 DC model parameters 有权
标题翻译：确定BSIMSOI4 DC模型参数的方法
公开(公告)号：US09134361B2
公开(公告)日：2015-09-15
申请号：US13696455
申请日：2011-09-25
申请人： Jing Chen , Qingqing Wu , Jiexin Luo , Zhan Chai , Xi Wang
发明人： Jing Chen , Qingqing Wu , Jiexin Luo , Zhan Chai , Xi Wang
IPC分类号： G06F7/60 , G01R31/26 , G06F17/50
CPC分类号： G01R31/2628 , G01R31/2603 , G06F17/5036
摘要： The present invention provides a method for determining BSIMSOI4 Direct Current (DC) model parameters, where a plurality of Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices of a body leading-out structure and of different sizes, and a plurality of MOSFET devices of a floating structure and of different sizes are provided; Id-Vg-Vp, Id/Ip-Vd-Vg, Ig-Vg-Vd, Ig-Vp, Ip-Vg-vd, Is/Id-Vp, and Id/Ip-Vp-Vd properties of all the MOSFET devices of a body leading-out structure, and Id-Vg-Vp, Id-Vd-Vg, and Ig-Vg-Vd properties of all the MOSFET devices of a floating structure are measured; electrical property curves without a self-heating effect of each MOSFET device of a body leading-out structure and each MOSFET device of a floating structure are obtained; and then DC parameters of a BSIMSOI4 model are successively extracted according to specific steps. In the present invention, proper test curves are successively selected according to model equations, and various kinds of parameters are successively determined, thereby accurately and effectively extracting the DC parameters of the BSIMSOI4 model.
摘要翻译：本发明提供了一种用于确定BSIMSOI4直流（DC）模型参数的方法，其中，体内引出结构和不同尺寸的多个金属氧化物半导体场效应晶体管（MOSFET）器件和多个MOSFET器件提供浮动结构和不同尺寸; 所有MOSFET器件的Id-Vg-Vp，Id / Ip-Vd-Vg，Ig-Vg-Vd，Ig-Vp，Ip-Vg-vd，Is / Id-Vp和Id / Ip-Vp-Vd特性测量浮体结构的所有MOSFET器件的体导体结构和Id-Vg-Vp，Id-Vd-Vg和Ig-Vg-Vd特性; 获得不具有体引出结构的每个MOSFET器件和浮置结构的每个MOSFET器件的自发热效应的电性能曲线; 然后根据具体步骤依次提取BSIMSOI4模型的DC参数。在本发明中，根据模型方程依次选择适当的试验曲线，并连续确定各种参数，从而准确有效地提取BSIMSOI4型号的直流参数。

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