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11. 发明申请

US20120299105A1 ETSOI CMOS with Back Gates 有权
标题翻译：带后盖的ETSOI CMOS
公开(公告)号：US20120299105A1
公开(公告)日：2012-11-29
申请号：US13114410
申请日：2011-05-24
申请人： Jin Cai , Robert H. Dennard , Ali Khakifirooz
发明人： Jin Cai , Robert H. Dennard , Ali Khakifirooz
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L27/1203
摘要： A structure has a functional region having a first type of conductivity and a top surface. The functional region is connected to a bias contact. The structure further includes an insulating layer; a semiconductor layer and first and second transistor devices having the same type of conductivity disposed upon the semiconductor layer. The structure further includes a first back gate region adjacent to the top surface and underlying one of the transistor devices, the first back gate region having a second type of conductivity; and a second back gate region adjacent to the top surface and underlying the other one of the transistor devices, the second back gate region having the first type of conductivity. The first transistor device has a first characteristic threshold voltage and the second transistor device has a second characteristic threshold voltage that differs from the first characteristic threshold voltage.
摘要翻译：结构具有具有第一类型的导电性的功能区域和顶表面。功能区域连接到偏置触点。该结构还包括绝缘层; 半导体层和具有相同类型导电性的第一和第二晶体管器件设置在半导体层上。所述结构还包括与所述顶表面相邻并且位于所述晶体管器件之一下方的第一后栅极区域，所述第一背栅极区域具有第二类型的导电性; 以及与顶表面相邻并且位于另一个晶体管器件下方的第二背栅极区域，第二背栅极区域具有第一类型的导电性。第一晶体管器件具有第一特征阈值电压，并且第二晶体管器件具有不同于第一特征阈值电压的第二特征阈值电压。

12. 发明申请

US20120138953A1 STRUCTURE AND METHOD FOR Vt TUNING AND SHORT CHANNEL CONTROL WITH HIGH K/METAL GATE MOSFETs 有权
标题翻译：具有高K /金属栅极MOSFET的调谐和短路控制的结构和方法
公开(公告)号：US20120138953A1
公开(公告)日：2012-06-07
申请号：US12960589
申请日：2010-12-06
申请人： Jin Cai , Xiangdong Chen , Xinlin Wang
发明人： Jin Cai , Xiangdong Chen , Xinlin Wang
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823892 , H01L21/823807 , H01L29/1041
摘要： A semiconductor device is provided that includes a semiconductor substrate having a well region located within an upper region thereof. A semiconductor material stack is located on the well region. The semiconductor material stack includes, from bottom to top, a semiconductor-containing buffer layer and a non-doped semiconductor-containing channel layer; the semiconductor-containing buffer layer of the semiconductor material stack is located directly on an upper surface of the well region. The structure also includes a gate material stack located directly on an upper surface of the non-doped semiconductor-containing channel layer. The gate material stack employed in the present disclosure includes, from bottom to top, a high k gate dielectric layer, a work function metal layer and a polysilicon layer.
摘要翻译：提供一种半导体器件，其包括具有位于其上部区域内的阱区的半导体衬底。半导体材料堆叠位于阱区上。半导体材料堆叠包括从底部到顶部的含半导体的缓冲层和非掺杂的含半导体的沟道层; 半导体材料堆叠的含半导体的缓冲层直接位于阱区的上表面。该结构还包括直接位于非掺杂半导体沟道层的上表面上的栅极材料堆叠。本公开中采用的栅极材料堆叠包括从底部到顶部的高k栅介质层，功函数金属层和多晶硅层。

13. 发明授权

US07919812B2 Partially depleted SOI field effect transistor having a metallized source side halo region 有权
标题翻译：部分耗尽的SOI场效应晶体管具有金属化源极侧区域
公开(公告)号：US07919812B2
公开(公告)日：2011-04-05
申请号：US12554344
申请日：2009-09-04
申请人： Jin Cai , Wilfried Haensch , Amlan Majumdar
发明人： Jin Cai , Wilfried Haensch , Amlan Majumdar
IPC分类号： H01L21/70 , H01K29/60
CPC分类号： H01L29/78696 , H01L29/458 , H01L29/66772 , H01L29/78612 , H01L29/78624
摘要： Source and drain extension regions and source side halo region and drain side halo region are formed in a top semiconductor layer aligned with a gate stack on an SOI substrate. A deep source region and a deep drain region are formed asymmetrically in the top semiconductor layer by an angled ion implantation. The deep source region is offset away from one of the outer edges of the at least spacer to expose the source extension region on the surface of the semiconductor substrate. A source metal semiconductor alloy is formed by reacting a metal layer with portions of the deep source region, the source extension region, and the source side halo region. The source metal semiconductor alloy abuts the remaining portion of the source side halo region, providing a body contact tied to the deep source region to the partially depleted SOI MOSFET.
摘要翻译：源极和漏极延伸区域和源极侧卤素区域和漏极侧晕圈形成在与SOI衬底上的栅极堆叠对准的顶部半导体层中。通过成角度的离子注入，在顶部半导体层中不均匀地形成深源区和深漏区。深源区域远离至少间隔物的外缘之一偏离以暴露半导体衬底的表面上的源延伸区域。源金属半导体合金通过使金属层与深源区，源极延伸区和源极侧晕区的一部分反应而形成。源极金属半导体合金与源极侧光晕区域的剩余部分相邻，从而将与源极区域连接的体接触部分连接到部分耗尽的SOI MOSFET。

14. 发明授权

US07700993B2 CMOS EPROM and EEPROM devices and programmable CMOS inverters 有权
标题翻译： CMOS EPROM和EEPROM器件以及可编程CMOS反相器
公开(公告)号：US07700993B2
公开(公告)日：2010-04-20
申请号：US11935143
申请日：2007-11-05
申请人： Jin Cai , Tak H. Ning , John M. Safran
发明人： Jin Cai , Tak H. Ning , John M. Safran
IPC分类号： H01L27/092
CPC分类号： H01L21/823857 , G11C16/0433 , G11C16/10 , H01L21/823885 , H01L21/84 , H01L27/0922 , H01L27/105 , H01L27/11521 , H01L27/11524 , H01L27/11558 , H01L27/1203 , H01L29/66825 , H01L29/785 , H01L29/7881
摘要： A CMOS EPROM, EEPROM or inverter device includes an nFET device with a thin gate dielectric layer and a pFET device juxtaposed with the nFET device with a thick gate dielectric layer and a floating gate electrode. The thick gate dielectric layer is substantially thicker than the thin gate dielectric layer. A common drain node connected both FET devices has no external connection in the case of a memory device and has an external connection in the case of an inverter. There are external circuit connections to the source regions of both FET devices and to the gate electrode of the nFET device. The pFET and nFET devices can be planar, vertical or FinFET devices.
摘要翻译： CMOS EPROM，EEPROM或逆变器装置包括具有薄栅介质层的nFET器件和与nFET器件并置的pFET器件，其具有厚栅极介电层和浮栅电极。厚栅极电介质层基本上比薄栅极电介质层厚。连接两个FET器件的公共漏极节点在存储器件的情况下没有外部连接，并且在逆变器的情况下具有外部连接。存在与FET器件的源极区域和nFET器件的栅电极的外部电路连接。 pFET和nFET器件可以是平面，垂直或FinFET器件。

15. 发明申请

US20100038695A1 Computing Apparatus Employing Dynamic Memory Cell Structures 有权
标题翻译：采用动态存储单元结构的计算设备
公开(公告)号：US20100038695A1
公开(公告)日：2010-02-18
申请号：US12542801
申请日：2009-08-18
申请人： Wing K. Luk , Jin Cai
发明人： Wing K. Luk , Jin Cai
IPC分类号： H01L27/108
CPC分类号： G11C11/4097 , G11C7/18 , G11C8/16 , G11C11/405 , H01L21/28079 , H01L21/84 , H01L27/10873 , H01L29/495
摘要： A dynamic random access memory cell is disclosed that comprises a capacitive storage device and a write access transistor. The write access transistor is operatively coupled to the capacitive storage device and has a gate stack that comprises a high-K dielectric, wherein the high-K dielectric has a dielectric constant greater than a dielectric constant of silicon dioxide. Also disclosed are a memory array using the cells, a computing apparatus using the memory array, a method of storing data, and a method of manufacturing.
摘要翻译：公开了一种动态随机存取存储器单元，其包括电容存储器件和写入存取晶体管。写入存取晶体管可操作地耦合到电容存储器件，并且具有包括高K电介质的栅极堆叠，其中高K电介质具有大于二氧化硅介电常数的介电常数。还公开了使用这些单元的存储器阵列，使用存储器阵列的计算装置，存储数据的方法和制造方法。

16. 发明授权

US07655983B2 SOI FET with source-side body doping 有权
标题翻译：具有源极体掺杂的SOI FET
公开(公告)号：US07655983B2
公开(公告)日：2010-02-02
申请号：US11757472
申请日：2007-06-04
申请人： Jin Cai , Tak Hung Ning
发明人： Jin Cai , Tak Hung Ning
IPC分类号： H01L31/119 , H01L21/336
CPC分类号： H01L29/78612 , H01L29/66772
摘要： An SOI FET device with improved floating body is proposed. Control of the body potential is accomplished by having a body doping concentration next to the source electrode higher than the body doping concentration next to the drain electrode. The high source-side dopant concentration leads to elevated forward leakage current between the source electrode and the body, which leakage current effectively locks the body potential to the source electrode potential. Furthermore, having the source-to-body junction capacitance larger than the drain-to-body junction capacitance has additional advantages in device operation. The device has no structure fabricated for the purpose of electrically connecting the body potential to other elements of the device.
摘要翻译：提出了一种具有改进的浮体的SOI FET器件。体电位的控制是通过使源电极旁边的体掺杂浓度高于漏电极旁边的体掺杂浓度来实现的。高源侧掺杂剂浓度导致源电极和体之间的向前泄漏电流升高，这种泄漏电流有效地将体电位锁定到源极电位。此外，具有大于漏极 - 体结结电容的源极 - 体结结电容在器件操作中具有额外的优点。该装置没有制造用于将身体电势电连接到装置的其它元件的结构。

17. 发明申请

US20090302388A1 Method for Fabricating Super-Steep Retrograde Well Mosfet on SOI or Bulk Silicon Substrate, and Device Fabricated in Accordance with the Method 有权
标题翻译：在SOI或体硅衬底上制造超陡逆行阱Mosfet的方法，以及按照该方法制造的器件
公开(公告)号：US20090302388A1
公开(公告)日：2009-12-10
申请号：US12542879
申请日：2009-08-18
申请人： Jin Cai , Amlan Majumdar , Tak H. Ning , Zhibin Ren
发明人： Jin Cai , Amlan Majumdar , Tak H. Ning , Zhibin Ren
IPC分类号： H01L27/12 , H01L27/092
CPC分类号： H01L29/1083 , H01L21/28052 , H01L21/28088 , H01L21/28247 , H01L29/165 , H01L29/4933 , H01L29/4966 , H01L29/517 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： A method is provided to fabricate a semiconductor device, where the method includes providing a substrate comprised of crystalline silicon; implanting a ground plane in the crystalline silicon so as to be adjacent to a surface of the substrate, the ground plane being implanted to exhibit a desired super-steep retrograde well (SSRW) implant doping profile; annealing implant damage using a substantially diffusionless thermal annealing to maintain the desired super-steep retrograde well implant doping profile in the crystalline silicon and, prior to performing a shallow trench isolation process, depositing a silicon cap layer over the surface of the substrate. The substrate may be a bulk Si substrate or a Si-on-insulator substrate. The method accommodates the use of an oxynitride gate stack structure or a high dielectric constant oxide/metal (high-K/metal) gate stack structure. The various thermal processes used during fabrication are selected/controlled so as to maintain the desired super-steep retrograde well implant doping profile in the crystalline silicon.
摘要翻译：提供了一种制造半导体器件的方法，其中该方法包括提供由晶体硅构成的衬底; 在晶体硅中注入接地平面以与衬底的表面相邻，所述接地平面被植入以呈现期望的超陡逆向阱（SSRW）注入掺杂分布; 使用基本上无扩散的热退火来退火植入物损伤，以在晶体硅中保持期望的超陡逆向阱注入掺杂分布，并且在执行浅沟槽隔离工艺之前，在衬底的表面上沉积硅帽层。衬底可以是体积Si衬底或绝缘体上硅衬底。该方法适应于使用氧氮化物栅叠层结构或高介电常数氧化物/金属（高K /金属）栅叠层结构。选择/控制在制造期间使用的各种热处理，以便在晶体硅中保持期望的超陡逆向阱注入掺杂分布。

18. 发明申请

US20090108350A1 Method For Fabricating Super-Steep Retrograde Well Mosfet On SOI or Bulk Silicon Substrate, And Device Fabricated In Accordance With The Method 有权
标题翻译：在SOI或体硅衬底上制造超陡逆向阱的方法以及根据该方法制造的器件
公开(公告)号：US20090108350A1
公开(公告)日：2009-04-30
申请号：US11925069
申请日：2007-10-26
申请人： Jin Cai , Amlan Majumdar , Tak H. Ning , Zhibin Ren
发明人： Jin Cai , Amlan Majumdar , Tak H. Ning , Zhibin Ren
IPC分类号： H01L21/336 , H01L29/786
CPC分类号： H01L29/1083 , H01L21/28052 , H01L21/28088 , H01L21/28247 , H01L29/165 , H01L29/4933 , H01L29/4966 , H01L29/517 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： A method is provided to fabricate a semiconductor device, where the method includes providing a substrate comprised of crystalline silicon; implanting a ground plane in the crystalline silicon so as to be adjacent to a surface of the substrate, the ground plane being implanted to exhibit a desired super-steep retrograde well (SSRW) implant doping profile; annealing implant damage using a substantially diffusionless thermal annealing to maintain the desired super-steep retrograde well implant doping profile in the crystalline silicon and, prior to performing a shallow trench isolation process, depositing a silicon cap layer over the surface of the substrate. The substrate may be a bulk Si substrate or a Si-on-insulator substrate. The method accommodates the use of an oxynitride gate stack structure or a high dielectric constant oxide/metal (high-K/metal) gate stack structure. The various thermal processes used during fabrication are selected/controlled so as to maintain the desired super-steep retrograde well implant doping profile in the crystalline silicon.
摘要翻译：提供了一种制造半导体器件的方法，其中该方法包括提供由晶体硅构成的衬底; 在晶体硅中注入接地平面以与衬底的表面相邻，所述接地平面被植入以呈现期望的超陡逆向阱（SSRW）注入掺杂分布; 使用基本上无扩散的热退火来退火植入物损伤，以在晶体硅中保持期望的超陡逆向阱注入掺杂分布，并且在执行浅沟槽隔离工艺之前，在衬底的表面上沉积硅帽层。衬底可以是体积Si衬底或绝缘体上硅衬底。该方法适应于使用氧氮化物栅叠层结构或高介电常数氧化物/金属（高K /金属）栅叠层结构。选择/控制在制造期间使用的各种热处理，以便在晶体硅中保持期望的超陡逆向阱注入掺杂分布。

19. 发明申请

US20080296676A1 SOI FET With Source-Side Body Doping 有权
标题翻译：具有源极侧体掺杂的SOI FET
公开(公告)号：US20080296676A1
公开(公告)日：2008-12-04
申请号：US11757472
申请日：2007-06-04
申请人： Jin Cai , Tak Hung Ning
发明人： Jin Cai , Tak Hung Ning
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/78612 , H01L29/66772
摘要： An SOI FET device with improved floating body is proposed. Control of the body potential is accomplished by having a body doping concentration next to the source electrode higher than the body doping concentration next to the drain electrode. The high source-side dopant concentration leads to elevated forward leakage current between the source electrode and the body, which leakage current effectively locks the body potential to the source electrode potential. Furthermore, having the source-to-body junction capacitance larger than the drain-to-body junction capacitance has additional advantages in device operation. The device has no structure fabricated for the purpose of electrically connecting the body potential to other elements of the device.
摘要翻译：提出了一种具有改进的浮体的SOI FET器件。体电位的控制是通过使源电极旁边的体掺杂浓度高于漏电极旁边的体掺杂浓度来实现的。高源侧掺杂剂浓度导致源电极和体之间的向前泄漏电流升高，这种泄漏电流有效地将体电位锁定到源极电位。此外，具有大于漏极 - 体结结电容的源极 - 体结结电容在器件操作中具有额外的优点。该装置没有制造用于将身体电势电连接到装置的其它元件的结构。

20. 发明授权

US06870213B2 EEPROM device with substrate hot-electron injector for low-power 失效
标题翻译：具有基板热电子注入器的EEPROM器件，用于低功耗
公开(公告)号：US06870213B2
公开(公告)日：2005-03-22
申请号：US10143291
申请日：2002-05-10
申请人： Jin Cai , Tak Hung Ning
发明人： Jin Cai , Tak Hung Ning
IPC分类号： H01L21/8247 , H01L21/84 , H01L27/115 , H01L27/12 , H01L29/788 , H01L29/76
CPC分类号： H01L27/11521 , H01L21/84 , H01L27/115 , H01L27/1203 , H01L29/7881
摘要： A low programming power, high speed EEPROM device is disclosed which is adapted for large scale integration. The device comprises a body, a source, a drain, and it has means for injecting a programming current into the body. The hot carriers from the body enter the floating gate with much higher efficiency than channel current carriers are capable of doing. The drain current of this device is controlled by the body bias. The device is built on an insulator, with a bottom common plate, and a top side body. These features make the device ideal for SOI and thin film technologies.
摘要翻译：公开了一种适用于大规模集成的低编程能力的高速EEPROM器件。该装置包括主体，源极，漏极，并且具有用于将编程电流注入到体内的装置。来自身体的热载体进入浮动门，效率高于通道载流子能够做到的效率。该器件的漏极电流由器件偏置控制。该装置建立在绝缘体上，底部共同板和顶侧体。这些特性使得器件成为SOI和薄膜技术的理想选择。

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