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11. 发明授权

US06323523B1 N-type structure for n-type pull-up and down I/O protection circuit 有权
标题翻译： N型结构用于n型上拉和下拉I / O保护电路
公开(公告)号：US06323523B1
公开(公告)日：2001-11-27
申请号：US09494682
申请日：2000-01-31
申请人： Jian-Hsing Lee , Yi-Hsun Wu , Shui-Hung Chen , Jiaw-Ren Shih
发明人： Jian-Hsing Lee , Yi-Hsun Wu , Shui-Hung Chen , Jiaw-Ren Shih
IPC分类号： H01L2362
CPC分类号： H01L27/0262 , H01L2924/0002 , H01L2924/00
摘要： An ESD protective circuit formed by n-type pull-up transistors and n-type pull-down transistors on a p-type silicon substrate for protecting an internal device circuit is disclosed. In the circuit, a n-well region having a p+ diffusion and a n+ diffusion therein being formed adjacent one drain region of one pull-up transistors, the p+ diffusion and a n+ diffusion, as well as all the drain regions of the pull-up transistors are coupled to a power supply. All the source regions of the pull-up transistors and drain regions of the pull-down transistors are connected to an I/O pad. All the source regions of the pull-down transistors including the p+ guardings are grounded. The gates of all transistors are connected to the internal device circuit so that the internal device circuit will be immunity from the ESD.
摘要翻译：公开了一种用于保护内部器件电路的p型硅衬底上的n型上拉晶体管和n型下拉晶体管形成的ESD保护电路。在该电路中，在一个上拉晶体管的一个漏极区附近形成有p +扩散和n +扩散的n阱区，p +扩散和n +扩散以及所述漏极区的所有漏极区，上拉晶体管耦合到电源。下拉晶体管的上拉晶体管和漏极区域的所有源极区域都连接到I / O焊盘。包括p +保护的下拉晶体管的所有源极区域接地。所有晶体管的栅极连接到内部器件电路，使得内部器件电路将免受ESD的影响。

12. 发明授权

US06277723B1 Plasma damage protection cell using floating N/P/N and P/N/P structure 有权
标题翻译：使用浮动N / P / N和P / N / P结构的等离子体损伤保护电池
公开(公告)号：US06277723B1
公开(公告)日：2001-08-21
申请号：US09418030
申请日：1999-10-14
申请人： Jiaw-Ren Shih , Shui-Hung Chen , Jian-Hsing Lee , Chrong Jung Lin
发明人： Jiaw-Ren Shih , Shui-Hung Chen , Jian-Hsing Lee , Chrong Jung Lin
IPC分类号： H01L2144
CPC分类号： H01L21/28123
摘要： A plasma damage protection cell using floating N/P/N and P/N/P structure, and a method to form the same are disclosed. Floating structures of the protection cell and the floating gates for the MOS devices are formed simultaneously on a semiconductor substrate having shallow trench isolation. The floating structures are implanted separately to form the N/P/N and P/N/P bipolar base, emitter and collector regions while the source/drain of the respective NMOS and PMOS devices are implanted with appropriate sequencing. The floating structures are connected to the substrate with appropriate polarity to provide protection at low leakage current levels and with tunable punch-through voltages.
摘要翻译：公开了使用浮动N / P / N和P / N / P结构的等离子体损伤保护单元及其形成方法。保护电池的浮动结构和用于MOS器件的浮置栅极同时形成在具有浅沟槽隔离的半导体衬底上。分别注入浮动结构以形成N / P / N和P / N / P双极基极，发射极和集电极区域，同时以适当的顺序植入各个NMOS和PMOS器件的源极/漏极。浮动结构以适当的极性连接到基板，以在低泄漏电流水平和可调穿通电压下提供保护。

13. 发明授权

US6122201A Clipped sine wave channel erase method to reduce oxide trapping charge generation rate of flash EEPROM 有权
标题翻译：缩短正弦波通道擦除方法，以减少闪存EEPROM的氧化物俘获电荷产生速率
公开(公告)号：US6122201A
公开(公告)日：2000-09-19
申请号：US421516
申请日：1999-10-20
申请人： Jian-Hsing Lee , Kuo-Reay Peng , Shui-Hung Chen , Jiaw-Ren Shih
发明人： Jian-Hsing Lee , Kuo-Reay Peng , Shui-Hung Chen , Jiaw-Ren Shih
IPC分类号： G11C16/16 , G11C16/04
CPC分类号： G11C16/16
摘要： A method to channel erase data from a flash EEPROM while electrical charges trapped in the tunneling oxide of a flash EEPROM are eliminated to maintain proper separation of the programmed threshold voltage and the erased threshold voltage after extended programming and erasing cycles. The method to channel erase a flash EEPROM cell begins by removing the charge from the floating gate of the flash EEPROM cell. The channel erasing consists of applying a relatively large clipped sinusoidal negative voltage pulse to the control gate of said EEPROM cell and concurrently applying a moderately large positive voltage pulse to a first diffusion region. At the same time a ground reference potential is applied to the semiconductor substrate, while the drain, the source and a second diffusion well are allowed to float.
摘要翻译：在快速EEPROM的隧道氧化物中捕获电荷的同时消除闪存EEPROM擦除数据的方法，以便在延长编程和擦除周期之后，保持编程阈值电压和擦除阈值电压的适当分离。通过从闪存EEPROM单元的浮动栅极去除电荷，开始通道擦除闪存EEPROM单元的方法。通道擦除包括将相对较大的限幅正弦负电压脉冲施加到所述EEPROM单元的控制栅极，同时向第一扩散区域施加适度大的正电压脉冲。同时，对半导体衬底施加接地参考电位，同时使漏极，源极和第二扩散阱浮动。

14. 发明授权

US07309905B2 Bipolar-based SCR for electrostatic discharge protection 有权
标题翻译：双极型SCR用于静电放电保护
公开(公告)号：US07309905B2
公开(公告)日：2007-12-18
申请号：US11065848
申请日：2005-02-25
申请人： Kuo-Feng Yu , Jian-Hsing Lee , Jiaw-Ren Shih , Fu Chin Yang
发明人： Kuo-Feng Yu , Jian-Hsing Lee , Jiaw-Ren Shih , Fu Chin Yang
IPC分类号： H01L29/00 , H01L29/74 , H01L31/111
CPC分类号： H01L29/7436 , H01L29/74
摘要： A system and method is disclosed for implementing a new bipolar-based silicon controlled rectifier (SCR) circuit for an electrostatic discharge (ESD) protection. The SCR circuit comprises a bipolar device to be formed on a semiconductor substrate. The bipolar device comprises at least an N-well for providing a high resistance and a P+ material to be used as a collector thereof for further providing a high resistance. At least an Nmoat guard ring and a Pmoat guard ring surround the bipolar device, wherein when an ESD event occurs, the high resistance provided by the N-well and the P+ material of the bipolar device increases a turn-on speed.
摘要翻译：公开了一种用于实现用于静电放电（ESD）保护的新的基于双极的可控硅整流器（SCR）电路的系统和方法。 SCR电路包括要形成在半导体衬底上的双极器件。双极器件至少包括用于提供高电阻的N阱和用作集电极的P +材料以进一步提供高电阻。至少一个Nmoat保护环和Pmoat保护环围绕双极器件，其中当ESD事件发生时，由N阱和双极器件的P +材料提供的高电阻增加了接通速度。

15. 发明申请

US20070159754A1 Circuit system for protecting thin dielectric devices from ESD induced damages 有权
标题翻译：用于保护薄介电元件免受ESD引起的损坏的电路系统
公开(公告)号：US20070159754A1
公开(公告)日：2007-07-12
申请号：US11332565
申请日：2006-01-12
申请人： Shao-Chang Huang , Jian-Hsing Lee , Yi-Hsun Wu , Jiaw-Ren Shih
发明人： Shao-Chang Huang , Jian-Hsing Lee , Yi-Hsun Wu , Jiaw-Ren Shih
IPC分类号： H02H3/22
CPC分类号： H01L27/0266 , H01L27/0255
摘要： A circuit system is disclosed for protecting a capacitor coupled between a voltage supply node and a complementary voltage supply node from an ESD. The circuit system includes at least one NMOS transistor having a drain coupled to the voltage supply node, a source and a gate together coupled to the complementary voltage supply node, and at least one diode chain having one or more diodes serially coupled between the voltage supply node and the complementary voltage supply node. During an ESD event, the diode chain and the NMOS transistor dissipate an ESD current from the voltage supply node to the complementary voltage supply node, thereby protecting the capacitor from ESD induced damages.
摘要翻译：公开了一种用于保护耦合在电压供应节点和互补电压供应节点之间的电容器与ESD的电路系统。电路系统包括至少一个NMOS晶体管，其具有耦合到电压供应节点的漏极，一起耦合到互补电源节点的源极和至少一个二极管链，其具有串联耦合在电压源之间的一个或多个二极管节点和互补电源节点。在ESD事件期间，二极管链和NMOS晶体管消耗从电压供应节点到互补电源节点的ESD电流，从而保护电容器免受ESD引起的损坏。

16. 发明申请

US20050212097A1 Charge device model (CDM) electrostatic discharge (ESD) failure rate via capacitive coating 审中-公开
标题翻译：充电器件型号（CDM）静电放电（ESD）故障率通过电容式涂层
公开(公告)号：US20050212097A1
公开(公告)日：2005-09-29
申请号：US10811656
申请日：2004-03-29
申请人： Jiaw-Ren Shih , Jian-Hsing Lee
发明人： Jiaw-Ren Shih , Jian-Hsing Lee
IPC分类号： H01L21/58 , H01L23/60 , H01L23/62 , H01L23/64
CPC分类号： H01L23/60 , G01R31/002 , H01L23/49513 , H01L23/642 , H01L24/48 , H01L24/83 , H01L2224/48091 , H01L2224/48227 , H01L2224/83 , H01L2924/00014 , H01L2924/01019 , H01L2924/14 , H01L2924/30107 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Improving charged device model (CDM) electrostatic discharge (ESD) testing failure rate is disclosed by applying a capacitive coating to an integrated circuit (IC). The IC includes a primary substrate, a number of contacts, and the coating. The substrate has a top surface, a bottom surface, and side surfaces. The contacts are on the top surface, and are connectable to packaging element pins. The capacitive coating is on at least the bottom surface, to make contact with a lead frame intended to secure the substrate to the packaging element. The coating provides a capacitance electrically in series with the capacitance of the IC. The total capacitance during CDM testing is decreased, decreasing the RC constant governing discharge of charge placed on the IC. Discharge occurs more slowly, the discharge current being inversely related to the constant. The maximum discharge current is decreased, allowing the IC to better withstand CDM testing.
摘要翻译：通过向集成电路（IC）施加电容涂层来公开改进充电装置模型（CDM）静电放电（ESD）测试失败率。该IC包括一个基底，多个触点和涂层。衬底具有顶表面，底表面和侧表面。触点位于顶面，可连接到封装元件引脚。电容涂层至少在底表面上，以与用于将基底固定到包装元件的引线框架接触。涂层提供与IC的电容电连接的电容。 CDM测试期间的总电容降低，从而降低控制IC上放电放电的RC常数。放电发生得更慢，放电电流与常数成反比。最大放电电流降低，使IC更好地承受CDM测试。

17. 发明授权

US06441438B1 ESD protect device structure 有权
标题翻译： ESD保护器件结构
公开(公告)号：US06441438B1
公开(公告)日：2002-08-27
申请号：US09709597
申请日：2000-11-13
申请人： Jiaw-Ren Shih , Jian-Hsing Lee , Huey-Liang Hwang
发明人： Jiaw-Ren Shih , Jian-Hsing Lee , Huey-Liang Hwang
IPC分类号： H01L2362
CPC分类号： H01L27/027 , H01L2924/0002 , H01L2924/00
摘要： An ESD protection structure that when connected between an input/output pad on a semiconductor substrate and a reference voltage source, will protect internal circuits formed on the semiconductor substrate from over stress due to excessively high voltages of an ESD voltage source. The ESD protection structure has a uniform discharge current to prevent damage to the ESD protection device thus allowing increased protection to the internal circuits. The ESD protection device has at least one source region that is the emitters of parasitic transistors connected to the reference voltage source and at least one drain region that is the collectors of the parasitic transistors connected to the junction of the input/output pad and the internal circuitry. The ESD protection device further has at least one gate electrode formed above a channel region. The channel region is the region is between each of the source regions and the drain regions. The gate electrodes are connected to the reference voltage source. Each gate electrode has a variable length and thus the channel region has a variable length. The channel region is the base of the parasitic transistors formed by the ESD protection structure. The variable length of the channel region and thus the base of the parasitic transistors create an ESD current that is distributed uniformly over said ESD protection structure.
摘要翻译：当连接在半导体衬底上的输入/输出焊盘与参考电压源之间时，ESD保护结构将保护由于ESD电压源的过高电压而在半导体衬底上形成的内部电路免受过度应力。 ESD保护结构具有均匀的放电电流，以防止ESD保护器件的损坏，从而允许增加对内部电路的保护。 ESD保护器件具有至少一个源极区域，其是连接到参考电压源的寄生晶体管的发射极，以及连接到输入/输出焊盘和内部的结的寄生晶体管的集电极的至少一个漏极区域电路。 ESD保护器件还具有形成在通道区域上方的至少一个栅电极。沟道区域是在源极区域和漏极区域中的每一个之间的区域。栅电极连接到参考电压源。每个栅电极具有可变长度，因此沟道区具有可变长度。通道区域是由ESD保护结构形成的寄生晶体管的基极。沟道区域的可变长度以及寄生晶体管的基极产生均匀分布在所述ESD保护结构上的ESD电流。

18. 发明授权

US06306695B1 Modified source side inserted anti-type diffusion ESD protection device 有权
标题翻译：修改源极侧插入防扩散ESD保护装置
公开(公告)号：US06306695B1
公开(公告)日：2001-10-23
申请号：US09407110
申请日：1999-09-27
申请人： Jian-Hsing Lee , Jiaw-Ren Shih , Shui-Hung Chen , Yi-Hsun Wu
发明人： Jian-Hsing Lee , Jiaw-Ren Shih , Shui-Hung Chen , Yi-Hsun Wu
IPC分类号： H01L2100
CPC分类号： H01L27/0277 , H01L27/0259 , H01L2924/0002 , H01L2924/00
摘要： An ESD protection circuit that will prevent internal circuits of an integrated circuit is formed on a semiconductor substrate to prevent damage during extreme voltage levels from an ESD voltage source and is connected to an input/output pad. A plurality of drains of multiple MOS FET's is formed within the surface of the semiconductor substrate and are each connected to the input/output pad. A plurality of sources of the multiple MOS FET's is formed within the surface of the semiconductor substrate and are placed at a distance from the plurality of drains and are connected to a ground reference potential. Pairs of the plurality of sources are adjacent to each other. A plurality of isolation regions placed between each source of the pairs of sources and are allowed to float. The multiple MOS FET's have a plurality of parasitic bipolar junction transistors. When contacting an ESD voltage source to the collectors of the plurality of parasitic bipolar junction transistors, the junction formed between the collector and the base of the parasitic bipolar junction transistor enters into avalanche breakdown. The avalanche breakdown generates a large current through the substrate bulk resistances that is sufficiently large as to cause the base emitter junctions of all the parasitic bipolar junction transistors and turn on the parasitic bipolar junction transistors. The conduction of all the parasitic bipolar junction transistors is sufficient to cause the ESD voltage to be discharged thus preventing damage to the internal circuitry.
摘要翻译：在半导体衬底上形成防止集成电路的内部电路的ESD保护电路，以防止在来自ESD电压源的极端电压电平期间的损坏并连接到输入/输出焊盘。多个MOS FET的漏极形成在半导体衬底的表面内，并且各自连接到输入/输出焊盘。多个MOS FET的多个源极形成在半导体衬底的表面内并且被放置在与多个漏极相距一定距离处并连接到接地参考电位。多个源的对彼此相邻。放置在源对之间的每个源之间并被允许浮动的多个隔离区域。多个MOS FET具有多个寄生双极结型晶体管。当将ESD电压源接触到多个寄生双极结型晶体管的集电极时，在集电极与寄生双极结型晶体管的基极之间形成的结形成为雪崩击穿。雪崩击穿通过衬底体电阻产生大的电流，该电阻足够大，以致引起所有寄生双极结型晶体管的基极发射极结并导通寄生双极结型晶体管。所有寄生双极结晶体管的导通足以使ESD电压放电，从而防止对内部电路的损坏。

19. 发明授权

US06268992B1 Displacement current trigger SCR 有权
公开(公告)号：US06268992B1
公开(公告)日：2001-07-31
申请号：US09292362
申请日：1999-04-15
申请人： Jian-Hsing Lee , Jiaw-Ren Shih , Yi-Hsun Wu , Jing-Meng Liu
发明人： Jian-Hsing Lee , Jiaw-Ren Shih , Yi-Hsun Wu , Jing-Meng Liu
IPC分类号： H02H322
CPC分类号： H01L27/0262 , H01L29/87
摘要： Circuits, device structures and methods are disclosed which protect CMOS semiconductor devices, having oxides as thin as 32 Angstrom, from electrostatic discharge (ESD) by utilizing a parasitic silicon controlled rectifier (SCR), intrinsic to the semiconductor device. The protection is afforded by providing low voltage triggering of the parasitic SCR in the order of 1.2 Volt. Triggering at such low voltages is made possible by means of a displacement current trigger which causes components of the SCR (parasitic npn and pnp bipolar transistors) to conduct, i.e., to trigger the SCR. The displacement current is realized by a junction capacitance, which is connected on one side to the pad to be protected and on the other side to terminals of the aforementioned parasitic bipolar transistors. Two ways of realizing the junction capacitance are disclosed.

20. 发明授权

US06258672B1 Method of fabricating an ESD protection device 有权
标题翻译：制造ESD保护装置的方法
公开(公告)号：US06258672B1
公开(公告)日：2001-07-10
申请号：US09252630
申请日：1999-02-18
申请人： Jiaw-Ren Shih , Jian-Hsing Lee , Huey-Liang Hwang
发明人： Jiaw-Ren Shih , Jian-Hsing Lee , Huey-Liang Hwang
IPC分类号： H01L218234
CPC分类号： H01L27/027 , H01L2924/0002 , H01L2924/00
摘要： An ESD protection structure that when connected between an input/output pad on a semiconductor substrate and a reference voltage source, will protect internal circuits formed on the semiconductor substrate from over stress due to excessively high voltages of an ESD voltage source. The ESD protection structure has a uniform discharge current to prevent damage to the ESD protection device thus allowing increased protection to the internal circuits. The ESD protection device has at least one source region that is the emitters of parasitic transistors connected to the reference voltage source and at least one drain region that is the collectors of the parasitic transistors connected to the junction of the input/output pad and the internal circuitry. The ESD protection device further has at least one gate electrode formed above a channel region. The channel region is the region is between each of the source regions and the drain regions. The gate electrodes are connected to the reference voltage source. Each gate electrode has a variable length and thus the channel region has a variable length. The channel region is the base of the parasitic transistors formed by the ESD protection structure. The variable length of the channel region and thus the base of the parasitic transistors create an ESD current that is distributed uniformly over said ESD protection structure.
摘要翻译：当连接在半导体衬底上的输入/输出焊盘与参考电压源之间时，ESD保护结构将保护由于ESD电压源的过高电压而在半导体衬底上形成的内部电路免受过度应力。 ESD保护结构具有均匀的放电电流，以防止ESD保护器件的损坏，从而允许增加对内部电路的保护。 ESD保护器件具有至少一个源极区域，其是连接到参考电压源的寄生晶体管的发射极，以及连接到输入/输出焊盘和内部的结的寄生晶体管的集电极的至少一个漏极区域电路。 ESD保护器件还具有形成在通道区域上方的至少一个栅电极。沟道区域是在源极区域和漏极区域中的每一个之间的区域。栅电极连接到参考电压源。每个栅电极具有可变长度，因此沟道区具有可变长度。通道区域是由ESD保护结构形成的寄生晶体管的基极。沟道区域的可变长度以及寄生晶体管的基极产生均匀分布在所述ESD保护结构上的ESD电流。

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