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11. 发明授权

US07825683B2 On die termination device and semiconductor memory device including the same 有权
标题翻译：在晶片终端器件和包括其的半导体存储器件中
公开(公告)号：US07825683B2
公开(公告)日：2010-11-02
申请号：US12181628
申请日：2008-07-29
申请人： Ki-Ho Kim , Ji-Eun Jang
发明人： Ki-Ho Kim , Ji-Eun Jang
IPC分类号： H03K17/16
CPC分类号： G11C5/063 , G11C7/1051 , G11C7/1057 , G11C2207/2254
摘要： On die termination (ODT) device that can reduce the number of lines for transferring calibration codes to reduce the size of a chip including the ODT device. The ODT device includes a calibration circuit configured to generate calibration codes for determining a termination resistance, a counting circuit configured to generate counting codes increasing with time. A transferring circuit of the device is configured sequentially to transfer the calibration codes in response to the counting codes. A receiving circuit is configured sequentially to receive the calibration codes from the transferring circuit in response to the counting codes. A termination resistance circuit of the device is configured to perform impedance matching using a resistance determined according to the calibration codes.
摘要翻译：在终端（ODT）设备上，可以减少用于传送校准码的行数，以减少包括ODT设备在内的芯片的尺寸。 ODT装置包括：校准电路，被配置为产生用于确定终止电阻的校准码;计数电路，被配置为产生随时间增加的计数码。依次配置设备的传送电路以响应于计数代码传送校准代码。接收电路被顺序配置以响应于计数代码从传送电路接收校准码。该器件的终端电阻电路被配置为使用根据校准码确定的电阻来执行阻抗匹配。

12. 发明授权

US07660171B2 Semiconductor memory device and method for driving the same 有权
标题翻译：半导体存储器件及其驱动方法
公开(公告)号：US07660171B2
公开(公告)日：2010-02-09
申请号：US11823878
申请日：2007-06-29
申请人： Ji-Eun Jang
发明人： Ji-Eun Jang
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G11C7/1051 , G11C7/1066 , G11C7/20 , G11C7/222 , G11C11/4072 , G11C11/4076 , G11C11/4093
摘要： A semiconductor memory device includes: a first count unit for counting a delayed locked loop (DLL) clock in response to a clock enable signal; a first delay unit for delaying the clock enable signal for a delay time which corresponds to a delay amount of a delay model included in a DLL circuit; a second count unit for counting an external clock in response to the delayed clock enable signal; a comparison unit for comparing an output of the first count unit with an output of the second count unit in order to generate a latency signal; and an output enable signal generation unit for generating an output enable signal by using the latency signal.
摘要翻译：半导体存储器件包括：第一计数单元，用于响应于时钟使能信号对延迟锁定环（DLL）时钟进行计数; 第一延迟单元，用于将对应于包括在DLL电路中的延迟模型的延迟量的延迟时间延迟所述时钟使能信号; 第二计数单元，用于响应延迟的时钟使能信号对外部时钟进行计数; 比较单元，用于将第一计数单元的输出与第二计数单元的输出进行比较，以产生等待时间信号; 以及输出使能信号生成单元，用于通过使用等待时间信号来产生输出使能信号。

13. 发明申请

US20090003096A1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US20090003096A1
公开(公告)日：2009-01-01
申请号：US12003680
申请日：2007-12-31
申请人： Kyung-Whan Kim , Ji-Eun Jang
发明人： Kyung-Whan Kim , Ji-Eun Jang
IPC分类号： G11C7/22
CPC分类号： G11C7/22 , G11C7/1045 , G11C11/4076 , G11C11/408 , G11C2207/2254
摘要： A semiconductor memory device is provided to improve the tAA characteristics. The semiconductor memory device includes: a discrimination signal generating unit for generating a first discrimination signal denoting a write operation of the semiconductor memory device; a selective delay unit for delaying a command-group signal in response to a second discrimination signal; and a fuse unit for generating the second discrimination signal based on the first discrimination signal, the second discrimination signal determining whether the selective delay unit selectively delays the command-group signal in response to the first discrimination signal.
摘要翻译：提供半导体存储器件以改善tAA特性。半导体存储器件包括：识别信号产生单元，用于产生表示半导体存储器件的写入操作的第一鉴别信号; 选择延迟单元，用于响应于第二鉴别信号延迟命令组信号; 以及熔丝单元，用于基于所述第一判别信号产生所述第二判别信号，所述第二判别信号确定所述选择延迟单元是否响应于所述第一判别信号有选择地延迟所述命令组信号。

14. 发明申请

US20080159025A1 Semiconductor memory device with various delay values 失效
标题翻译：具有各种延迟值的半导体存储器件
公开(公告)号：US20080159025A1
公开(公告)日：2008-07-03
申请号：US11819802
申请日：2007-06-29
申请人： Ji-Eun Jang , Kyung-Whan Kim
发明人： Ji-Eun Jang , Kyung-Whan Kim
IPC分类号： G11C5/14 , G11C7/00
CPC分类号： G11C7/22 , G11C29/50 , G11C29/50012
摘要： A memory device includes a delay circuit and a delay selection unit. The delay circuit delays a pulse signal to generate a delayed pulse signal. The pulse signal is used to generate a write enable signal and a read enable signal. The delay selection unit selects one of the delayed pulse signal output from the delay circuit in a test mode and the pulse signal in a normal mode.
摘要翻译：存储器件包括延迟电路和延迟选择单元。延迟电路延迟脉冲信号以产生延迟的脉冲信号。脉冲信号用于产生写使能信号和读使能信号。延迟选择单元在测试模式中选择从延迟电路输出的延迟脉冲信号和正常模式中的脉冲信号之一。

15. 发明申请

US20070070714A1 Synchronous semiconductor memory device 有权
标题翻译：同步半导体存储器件
公开(公告)号：US20070070714A1
公开(公告)日：2007-03-29
申请号：US11478087
申请日：2006-06-30
申请人： Ji-Eun Jang
发明人： Ji-Eun Jang
IPC分类号： G11C7/10
CPC分类号： G11C11/4087 , G11C7/22 , G11C7/225 , G11C11/4076
摘要： A synchronous semiconductor memory device can perform an internal operation for an input address with reliability regardless of the frequency of a system clock. The semiconductor memory device includes an internal operation detecting unit for generating a flag signal in response to internal command signals; a delay unit for delaying the flag signal for a programmed time; and an enable signal generating unit for generating an enable signal activated in response to a transition timing of the flag signal and inactivated in response to a transition timing of the delayed flag signal, wherein an internal address derived from an external address is transferred to a core area while the enable signal is activated.
摘要翻译：同步半导体存储器件可以对输入地址进行内部操作，而与系统时钟的频率无关。半导体存储器件包括：内部操作检测单元，用于响应于内部命令信号产生标志信号; 延迟单元，用于将所述标志信号延迟编程时间; 以及使能信号生成单元，用于响应于所述标志信号的转换定时而产生使能信号，并响应于所述延迟标志信号的转换定时而被去激活，其中从外部地址导出的内部地址被传送到核心区域，同时使能信号被激活。

16. 发明授权

US07106112B2 Apparatus for generating power-up signal 失效
标题翻译：用于产生上电信号的装置
公开(公告)号：US07106112B2
公开(公告)日：2006-09-12
申请号：US10875403
申请日：2004-06-25
申请人： Ji-Eun Jang
发明人： Ji-Eun Jang
IPC分类号： H03L7/00
CPC分类号： H03K17/223 , G11C5/143 , G11C7/20
摘要： An apparatus for generating a power-up signal in a semiconductor memory device includes a signal generator for generating the power-up signal from a supply voltage in response to a first control signal, a temperature sensing block for sensing a circumference temperature and enabling one of a plurality of second control signals in response to the circumference temperature, and a selection block for receiving the plurality of divided voltages and outputting one of the plurality of divided voltages to the signal generator as the first control signal in response to a corresponding second control signal, wherein the divided voltages are generated by dividing a supply voltage.
摘要翻译：一种用于在半导体存储器件中产生上电信号的装置包括：信号发生器，用于响应于第一控制信号从电源电压产生上电信号;温度检测块，用于感测周围温度，响应于所述周围温度的多个第二控制信号;以及选择块，用于接收所述多个分压，并响应于相应的第二控制信号，将所述多个分压的所述多个分压中的一个输出到所述信号发生器作为所述第一控制信号其中，通过分压电源电压来产生分压。

17. 发明申请

US20060146631A1 Self refresh oscillator and oscillation signal generation method of the same 失效
标题翻译：自刷振荡器和振荡信号产生方法相同
公开(公告)号：US20060146631A1
公开(公告)日：2006-07-06
申请号：US11319718
申请日：2005-12-29
申请人： Ji-Eun Jang
发明人： Ji-Eun Jang
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C2211/4065
摘要： A self refresh period signal generator includes: a voltage detection unit for detecting a voltage level of a power supply voltage in order to generate a plurality of period control signals according to the detected voltage level; and an oscillation unit for generating a ring oscillation signal having a constant period determined by a resistance of a period control resistor when a self refresh signal is activated, wherein the resistance of the period control resistor is controlled according to logic levels of the plurality of period control signals.
摘要翻译：自刷新周期信号发生器包括：电压检测单元，用于检测电源电压的电压电平，以便根据检测的电压电平产生多个周期控制信号; 以及振荡单元，用于当自刷新信号被激活时产生具有由周期控制电阻器的电阻确定的恒定周期的环形振荡信号，其中周期控制电阻器的电阻根据多个周期的逻辑电平进行控制控制信号。

18. 发明授权

US06980040B2 Delay adjusting apparatus providing different delay times by producing a plurality of delay control signals 失效
标题翻译：延迟调整装置通过产生多个延迟控制信号来提供不同的延迟时间
公开(公告)号：US06980040B2
公开(公告)日：2005-12-27
申请号：US10746645
申请日：2003-12-23
申请人： Ji-Eun Jang , Jae-Jin Lee
发明人： Ji-Eun Jang , Jae-Jin Lee
IPC分类号： G11C7/00 , G01R31/30 , G01R31/317 , H03K5/00 , H03K5/13 , H03K5/135 , H03K19/00
CPC分类号： G01R31/3016 , G01R31/31727 , H03K5/133 , H03K5/135 , H03K2005/00156 , H03K2005/00234
摘要： The present invention relates to a semiconductor device; and, more particularly, to a delay adjusting circuit which is required to adjust a delay time of an internal circuit in a test mode and required to verify a characteristic and a margin of the semiconductor device. The delay adjusting apparatus according to the present invention comprises: a normal delayer for delaying an input signal from an external circuit; a delay time storage for maintaining a predetermined delay time produced by a control signal and delaying the input signal based on the predetermined delay time; and a selector for selectively outputting one of output signals from the normal delayer and the delay time storage in response to a test mode signal.
摘要翻译：本发明涉及半导体器件; 更具体地，涉及一种延迟调整电路，其需要在测试模式中调整内部电路的延迟时间并且需要验证半导体器件的特性和余量。根据本发明的延迟调整装置包括：用于延迟来自外部电路的输入信号的正常延迟器; 延迟时间存储器，用于维持由控制信号产生的预定延迟时间，并且基于所述预定延迟时间延迟所述输入信号; 以及选择器，用于响应于测试模式信号选择性地输出来自正常延迟器的输出信号和延迟时间存储中的一个。

19. 发明申请

US20050024129A1 Reference voltage generating circuit for outputting multi-level reference voltage using fuse trimming 有权
标题翻译：参考电压发生电路，用于使用熔丝修整输出多电平参考电压
公开(公告)号：US20050024129A1
公开(公告)日：2005-02-03
申请号：US10746494
申请日：2003-12-23
申请人： Ji-Eun Jang
发明人： Ji-Eun Jang
IPC分类号： G11C5/14 , G05F1/46 , G05F1/10
CPC分类号： G05F1/465
摘要： A reference voltage generating circuit includes voltage outputting means for outputting a reference voltage corresponding to a difference between a band gap reference voltage and an input voltage; a first resistor having one end that is coupled to the output of the voltage outputting unit; first variable resistor unit having a plurality of second resistors that are serially coupled between the first resistor and a ground voltage, for providing the input voltage of the voltage outputting unit with a first trimming voltage that is inputted to one end of selected one of the plurality of the second resistors in response to decoded signals for trimming the reference voltage; second variable resistor having a plurality of third resistors coupled serially between the first resistor and the ground voltage, the third resistors having different resistances from the second resistors, for providing the input voltage of the voltage outputting unit with a second trimming voltage that is inputted to one end of selected one of the plurality of the third resistors in response to the decoded signals for trimming the reference voltage; and selecting unit for selectively providing the first trimming voltage or the second trimming voltage to the input voltage of the voltage outputting unit.
摘要翻译：参考电压产生电路包括电压输出装置，用于输出对应于带隙基准电压和输入电压之间的差的参考电压; 第一电阻器，其一端耦合到电压输出单元的输出; 第一可变电阻器单元，具有串联地耦合在第一电阻器和接地电压之间的多个第二电阻器，用于提供电压输出单元的输入电压，该第一微调电压被输入到多个选定的一个的一端的第二电阻器响应于用于修整参考电压的解码信号; 所述第二可变电阻器具有串联地耦合在所述第一电阻器和所述接地电压之间的多个第三电阻器，所述第三电阻器具有与所述第二电阻器不同的电阻，用于向所述电压输出单元提供输入至所述第二电阻器的第二微调电压响应于用于修整参考电压的解码信号，多个第三电阻器中的所选择的一个的一端; 以及选择单元，用于选择性地将第一微调电压或第二微调电压提供给电压输出单元的输入电压。

20. 发明授权

US08860770B2 Method of driving a display panel and a display apparatus performing the method 有权
标题翻译：驱动显示面板的方法和执行该方法的显示装置
公开(公告)号：US08860770B2
公开(公告)日：2014-10-14
申请号：US13242098
申请日：2011-09-23
申请人： Yong-Ju Jeong , Jong-Hee Na , Young-Min Choi , Jae-Kil Lee , Seung-Kuk Yun , Ji-Eun Jang
发明人： Yong-Ju Jeong , Jong-Hee Na , Young-Min Choi , Jae-Kil Lee , Seung-Kuk Yun , Ji-Eun Jang
IPC分类号： G09G5/10 , G09G5/02 , H04N13/04 , G09G3/00
CPC分类号： H04N13/398 , G09G3/00 , G09G3/2074 , G09G3/3607 , G09G3/3677 , G09G2320/0233 , G09G2320/0252 , G09G2320/0653 , H04N13/359
摘要： A method of driving a display panel includes driving a first sub area and a second sub area of a pixel part in a two-dimensional (2D) image mode, wherein a first luminance difference exists between the first and second sub areas in the 2D image mode, and driving the first sub area and the second sub area of the pixel part in a three-dimensional (3D) image mode, wherein a second luminance difference exists between the first and second sub areas in the 3D image mode, the second luminance difference being smaller than the first luminance difference.
摘要翻译：驱动显示面板的方法包括以二维（2D）图像模式驱动像素部分的第一子区域和第二子区域，其中在2D图像中的第一和第二子区域之间存在第一亮度差异模式，并且在三维（3D）图像模式中驱动像素部分的第一子区域和第二子区域，其中在3D图像模式中的第一和第二子区域之间存在第二亮度差，第二亮度差小于第一亮度差。

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