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11. 发明申请

US20160111449A1 HIGH VOLTAGE THREE-DIMENSIONAL DEVICES HAVING DIELECTRIC LINERS 有权
公开(公告)号：US20160111449A1
公开(公告)日：2016-04-21
申请号：US14975645
申请日：2015-12-18
申请人： Walid M. Hafez , Jeng-Ya D. Yeh , Curtis Tsai , Joodong Park , Chia-Hong Jan , Gopinath Bhimarasetti
发明人： Walid M. Hafez , Jeng-Ya D. Yeh , Curtis Tsai , Joodong Park , Chia-Hong Jan , Gopinath Bhimarasetti
IPC分类号： H01L27/12 , H01L29/66 , H01L29/51 , H01L29/423 , H01L21/8234
CPC分类号： H01L27/1211 , H01L21/02164 , H01L21/0228 , H01L21/02532 , H01L21/02598 , H01L21/28158 , H01L21/823412 , H01L21/823418 , H01L21/823431 , H01L21/823437 , H01L21/823462 , H01L21/823468 , H01L21/845 , H01L29/42356 , H01L29/51 , H01L29/513 , H01L29/66545 , H01L29/6656 , H01L29/6681
摘要： High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region. The second gate structure includes a second gate dielectric, a second gate electrode, and second spacers. The second gate dielectric is composed of the second dielectric layer disposed on the second fin active region and along sidewalls of the second spacers.

12. 发明申请

US20150179525A1 HIGH VOLTAGE THREE-DIMENSIONAL DEVICES HAVING DIELECTRIC LINERS 有权
标题翻译：具有电介质衬底的高电压三维器件
公开(公告)号：US20150179525A1
公开(公告)日：2015-06-25
申请号：US14641117
申请日：2015-03-06
申请人： Walid M. Hafez , Jeng-Ya D. Yeh , Curtis Tsai , Joodong Park , Chia-Hong Jan , Gopinath Bhimarasetti
发明人： Walid M. Hafez , Jeng-Ya D. Yeh , Curtis Tsai , Joodong Park , Chia-Hong Jan , Gopinath Bhimarasetti
IPC分类号： H01L21/8234 , H01L21/02 , H01L21/28 , H01L29/66
CPC分类号： H01L27/1211 , H01L21/02164 , H01L21/0228 , H01L21/02532 , H01L21/02598 , H01L21/28158 , H01L21/823412 , H01L21/823418 , H01L21/823431 , H01L21/823437 , H01L21/823462 , H01L21/823468 , H01L21/845 , H01L29/42356 , H01L29/51 , H01L29/513 , H01L29/66545 , H01L29/6656 , H01L29/6681
摘要： High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region. The second gate structure includes a second gate dielectric, a second gate electrode, and second spacers. The second gate dielectric is composed of the second dielectric layer disposed on the second fin active region and along sidewalls of the second spacers.
摘要翻译：描述了具有电介质衬垫的高压三维器件和形成具有电介质衬垫的高电压三维器件的方法。例如，半导体结构包括设置在基板上方的第一鳍状物活性区域和第二鳍状物活性区域。第一栅极结构设置在第一鳍片活动区域的顶表面之上并且沿着第一鳍片活动区域的侧壁的上方。第一栅极结构包括第一栅极电介质，第一栅极电极和第一间隔物。第一栅极电介质由设置在第一鳍状物活性区域上并沿着第一间隔物的侧壁的第一介电层和设置在第一介电层上并沿着第一间隔物的侧壁的第二不同介电层组成。半导体结构还包括第二栅极结构，其设置在第二鳍片活动区域的顶表面之上并且沿着第二鳍片活动区域的侧壁的上方。第二栅极结构包括第二栅极电介质，第二栅电极和第二间隔物。第二栅极电介质由设置在第二鳍状物活性区域和第二间隔物的侧壁上的第二介电层构成。

13. 发明授权

US08981481B2 High voltage three-dimensional devices having dielectric liners 有权
标题翻译：具有电介质衬垫的高压三维器件
公开(公告)号：US08981481B2
公开(公告)日：2015-03-17
申请号：US13536732
申请日：2012-06-28
申请人： Walid M. Hafez , Jeng-Ya D. Yeh , Curtis Tsai , Joodong Park , Chia-Hong Jan , Gopinath Bhimarasetti
发明人： Walid M. Hafez , Jeng-Ya D. Yeh , Curtis Tsai , Joodong Park , Chia-Hong Jan , Gopinath Bhimarasetti
IPC分类号： H01L21/84 , H01L27/12 , H01L21/8234 , H01L29/66
CPC分类号： H01L27/1211 , H01L21/02164 , H01L21/0228 , H01L21/02532 , H01L21/02598 , H01L21/28158 , H01L21/823412 , H01L21/823418 , H01L21/823431 , H01L21/823437 , H01L21/823462 , H01L21/823468 , H01L21/845 , H01L29/42356 , H01L29/51 , H01L29/513 , H01L29/66545 , H01L29/6656 , H01L29/6681
摘要： High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric composed of a first dielectric layer disposed on the first fin active region, and a second, different, dielectric layer disposed on the first dielectric layer. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region. The second gate structure includes a second gate dielectric composed of the second dielectric layer disposed on the second fin active region.
摘要翻译：描述了具有电介质衬垫的高压三维器件和形成具有电介质衬垫的高电压三维器件的方法。例如，半导体结构包括设置在基板上方的第一鳍状物活性区域和第二鳍状物活性区域。第一栅极结构设置在第一鳍片活动区域的顶表面之上并且沿着第一鳍片活动区域的侧壁的上方。第一栅极结构包括由设置在第一鳍片有源区上的第一介电层和设置在第一介电层上的第二不同介电层构成的第一栅极电介质。半导体结构还包括第二栅极结构，其设置在第二鳍片活动区域的顶表面之上并且沿着第二鳍片活动区域的侧壁的上方。第二栅极结构包括由设置在第二鳍片有源区上的第二介电层构成的第二栅极电介质。

14. 发明申请

US20120161237A1 MULTI-GATE TRANSISTORS 有权
标题翻译：多栅极晶体管
公开(公告)号：US20120161237A1
公开(公告)日：2012-06-28
申请号：US12978182
申请日：2010-12-23
申请人： Chia-Hong Jan , Curtis Tsai , Joodong Park , Jeng-Ya D. Yeh , Walid M. Hafez
发明人： Chia-Hong Jan , Curtis Tsai , Joodong Park , Jeng-Ya D. Yeh , Walid M. Hafez
IPC分类号： H01L27/088 , B82Y10/00
CPC分类号： H01L21/823857 , H01L21/26506 , H01L21/28158 , H01L21/2822 , H01L21/823462 , H01L29/495 , H01L29/513 , H01L29/517 , H01L29/66545 , H01L29/78
摘要： Provided are devices having at least three and at least four different types of transistors wherein the transistors are distinguished at least by the thicknesses and or compositions of the gate dielectric regions. Methods for making devices having three and at least four different types of transistors that are distinguished at least by the thicknesses and or compositions of the gate dielectric regions are also provided.
摘要翻译：提供了具有至少三种和至少四种不同类型的晶体管的器件，其中晶体管至少区别于栅极电介质区域的厚度和/或组成。还提供了制造具有三个至少四种不同类型晶体管的器件的方法，其至少区别于栅极电介质区域的厚度和/或组成。

15. 发明申请

US20140319623A1 METHODS OF INTEGRATING MULTIPLE GATE DIELECTRIC TRANSISTORS ON A TRI-GATE (FINFET) PROCESS 审中-公开
标题翻译：在三极（FINFET）工艺上集成多个栅极介质晶体管的方法
公开(公告)号：US20140319623A1
公开(公告)日：2014-10-30
申请号：US13997624
申请日：2011-12-28
申请人： Curtis Tsai , Chia-Hong Jan , Jeng-Ya David Yeh , Joodong Park , Walid M. Hafez
发明人： Curtis Tsai , Chia-Hong Jan , Jeng-Ya David Yeh , Joodong Park , Walid M. Hafez
IPC分类号： H01L21/8234 , H01L29/423 , H01L27/088
摘要： Two or more types of fin-based transistors having different gate structures and formed on a single integrated circuit are described. The gate structures for each type of transistor are distinguished at least by the thickness or composition of the gate dielectric layer(s) or the composition of the work function metal layer(s) in the gate electrode. Methods are also provided for fabricating an integrated circuit having at least two different types of fin-based transistors, where the transistor types are distinguished by the thickness and composition of the gate dielectric layer(s) and/or the thickness and composition of the work function metal in the gate electrode.
摘要翻译：描述了具有不同栅极结构并形成在单个集成电路上的两种或多种类型的鳍式晶体管。每种类型的晶体管的栅极结构至少区别于栅极电介质层的厚度或组成或栅电极中功函数金属层的组成。还提供了用于制造具有至少两种不同类型的基于鳍的晶体管的集成电路的方法，其中晶体管类型通过栅极电介质层的厚度和组成和/或工件的厚度和组成来区分功能金属在栅电极。

16. 发明授权

US10658361B2 Methods of integrating multiple gate dielectric transistors on a tri-gate (FINFET) process 有权
公开(公告)号：US10658361B2
公开(公告)日：2020-05-19
申请号：US13997624
申请日：2011-12-28
申请人： Curtis Tsai , Chia-Hong Jan , Jeng-Ya David Yeh , Joodong Park , Walid M. Hafez
发明人： Curtis Tsai , Chia-Hong Jan , Jeng-Ya David Yeh , Joodong Park , Walid M. Hafez
IPC分类号： H01L27/092 , H01L29/66 , H01L29/40 , H01L29/78 , H01L21/8234 , H01L27/088 , H01L29/49 , H01L29/423 , H01L29/51
摘要： Two or more types of fin-based transistors having different gate structures and formed on a single integrated circuit are described. The gate structures for each type of transistor are distinguished at least by the thickness or composition of the gate dielectric layer(s) or the composition of the work function metal layer(s) in the gate electrode. Methods are also provided for fabricating an integrated circuit having at least two different types of fin-based transistors, where the transistor types are distinguished by the thickness and composition of the gate dielectric layer(s) and/or the thickness and composition of the work function metal in the gate electrode.

17. 发明申请

US20100164001A1 Implant process for blocked salicide poly resistor and structures formed thereby 审中-公开
标题翻译：植入过程中封闭的自杀化合物多晶硅电阻和结构形成
公开(公告)号：US20100164001A1
公开(公告)日：2010-07-01
申请号：US12319015
申请日：2008-12-30
申请人： Joodong Park , Chia-Hong Jan , Lisa M. McGill
发明人： Joodong Park , Chia-Hong Jan , Lisa M. McGill
IPC分类号： H01L27/092 , H01L21/8238 , H01L21/22
CPC分类号： H01L21/26506 , H01L21/26513 , H01L27/0629 , H01L28/24 , H01L29/665 , H01L29/66575
摘要： Methods and associated structures of forming a microelectronic device are described. Those methods may include implanting an exposed p type silicon portion of a substrate with a carbon species, wherein endcap regions of a blocked salicide resistor and a p type structure that are both disposed on the exposed p type silicon portion of the substrate are implanted with the carbon species.
摘要翻译：描述形成微电子器件的方法和相关结构。这些方法可以包括用碳物种植入衬底的暴露的p型硅部分，其中嵌入在衬底的暴露的p型硅部分上的封闭的自对夹硅电阻器和ap型结构的端盖区域被植入碳种类。

18. 发明申请

US20090170273A1 Dual layer hard mask for block salicide poly resistor (BSR) patterning 失效
标题翻译：双层硬掩模用于块状硅化物电阻（BSR）图案化
公开(公告)号：US20090170273A1
公开(公告)日：2009-07-02
申请号：US12005944
申请日：2007-12-27
申请人： Joodong Park , Chia-Hong Jan , Paul Reese
发明人： Joodong Park , Chia-Hong Jan , Paul Reese
IPC分类号： H01L21/02
CPC分类号： H01L29/8605 , H01L28/24
摘要： In general, in one aspect, a method includes forming a semiconductor substrate having an N+ diffusion region, a shallow trench isolation (STI) region adjacent to the N+ diffusion region, and a blocked salicide poly resistor (BSR) region over the STI region. An oxide layer is over the substrate. A nitride layer is formed over the oxide layer and is annealed. A resist layer is patterned on the annealed nitride layer, wherein the resist layer covers a portion of the BSR region. The annealed nitride layer is etched using the resist layer as a pattern. The resist layer is removed and the oxide layer is etched using the annealed nitride layer as a pattern. Germanium pre-amorphization is implanted into the substrate, wherein the oxide and the annealed nitride layers protect a portion of the BSR region from the implanting.
摘要翻译：通常，在一个方面，一种方法包括形成具有N +扩散区域，与N +扩散区域相邻的浅沟槽隔离（STI）区域和在STI区域上的封闭的自对准硅化物多晶硅电阻器（BSR）区域的半导体衬底。氧化物层在衬底上。在氧化物层上形成氮化物层并进行退火。在退火的氮化物层上图案化抗蚀剂层，其中抗蚀剂层覆盖BSR区域的一部分。使用抗蚀剂层作为图案蚀刻退火的氮化物层。去除抗蚀剂层，并使用退火的氮化物层作为图案来蚀刻氧化物层。将锗预非晶化植入衬底中，其中氧化物和退火的氮化物层保护BSR区域的一部分免受植入。

19. 发明授权

US07691718B2 Dual layer hard mask for block salicide poly resistor (BSR) patterning 失效
标题翻译：双层硬掩模用于块状硅化物电阻（BSR）图案化
公开(公告)号：US07691718B2
公开(公告)日：2010-04-06
申请号：US12005944
申请日：2007-12-27
申请人： Joodong Park , Chia-Hong Jan , Paul Reese
发明人： Joodong Park , Chia-Hong Jan , Paul Reese
IPC分类号： H01L21/20
CPC分类号： H01L29/8605 , H01L28/24
摘要： In general, in one aspect, a method includes forming a semiconductor substrate having an N+ diffusion region, a shallow trench isolation (STI) region adjacent to the N+ diffusion region, and a blocked salicide poly resistor (BSR) region over the STI region. An oxide layer is over the substrate. A nitride layer is formed over the oxide layer and is annealed. A resist layer is patterned on the annealed nitride layer, wherein the resist layer covers a portion of the BSR region. The annealed nitride layer is etched using the resist layer as a pattern. The resist layer is removed and the oxide layer is etched using the annealed nitride layer as a pattern. Germanium pre-amorphization is implanted into the substrate, wherein the oxide and the annealed nitride layers protect a portion of the BSR region from the implanting.
摘要翻译：通常，在一个方面，一种方法包括形成具有N +扩散区域，与N +扩散区域相邻的浅沟槽隔离（STI）区域和在STI区域上的封闭的自对准硅化物多晶硅电阻器（BSR）区域的半导体衬底。氧化物层在衬底上。在氧化物层上形成氮化物层并进行退火。在退火的氮化物层上图案化抗蚀剂层，其中抗蚀剂层覆盖BSR区域的一部分。使用抗蚀剂层作为图案蚀刻退火的氮化物层。去除抗蚀剂层，并使用退火的氮化物层作为图案来蚀刻氧化物层。将锗预非晶化植入衬底中，其中氧化物和退火的氮化物层保护BSR区域的一部分免受植入。

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