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11. 发明申请

US20090282184A1 COMPENSATING NON-VOLATILE STORAGE USING DIFFERENT PASS VOLTAGES DURING PROGRAM-VERIFY AND READ 有权
标题翻译：在程序验证和读取期间使用不同的PASS电压来补偿非易失性存储
公开(公告)号：US20090282184A1
公开(公告)日：2009-11-12
申请号：US12118446
申请日：2008-05-09
申请人： Deepanshu Dutta , Jeffrey W. Lutze
发明人： Deepanshu Dutta , Jeffrey W. Lutze
IPC分类号： G06F12/02
CPC分类号： G11C16/0483 , B05B11/3098 , G11C11/5628 , G11C11/5642 , G11C16/26 , G11C16/3454 , G11C2211/5621
摘要： Optimized verify and read pass voltages are obtained to improve read accuracy in a non-volatile storage device. The optimized voltages account for changes in unselected storage element resistance when the storage elements become programmed. This change in resistance is referred to as a front pattern effect. In one approach, the verify pass voltage is higher than the read pass voltage, and a common verify voltage is applied on the source and drain sides of a selected word line. In other approaches, different verify pass voltages are applied on the source and drain sides of the selected word line. An optimization process can include determining a metric for different sets of verify and read pass voltages. The metric can indicate threshold voltage width, read errors or a decoding time or number of iterations of an ECC decoding engine.
摘要翻译：获得优化的验证和读取通过电压，以提高非易失性存储设备的读取精度。当存储元件变为编程时，优化的电压表示未选择的存储元件电阻的变化。这种电阻变化被称为前模式效应。在一种方法中，验证通过电压高于读取通过电压，并且在所选字线的源极和漏极侧施加公共验证电压。在其他方法中，不同的验证通过电压施加在所选字线的源极和漏极侧。优化过程可以包括确定不同组的验证和读取通过电压的度量。该度量可以指示ECC解码引擎的阈值电压宽度，读取错误或解码时间或迭代次数。

12. 发明授权

US08369149B2 Multi-step channel boosting to reduce channel to floating gate coupling in memory 有权
标题翻译：多级通道升压以减少通道到存储器中的浮动栅极耦合
公开(公告)号：US08369149B2
公开(公告)日：2013-02-05
申请号：US12894889
申请日：2010-09-30
申请人： Deepanshu Dutta , Jeffrey W. Lutze , Henry Chin
发明人： Deepanshu Dutta , Jeffrey W. Lutze , Henry Chin
IPC分类号： G11C11/34
CPC分类号： G11C16/3418 , G11C7/02 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/3427 , G11C16/3454 , G11C2211/5621
摘要： In a programming operation, selected storage elements which reach a lockout condition are subject to reduced channel boosting in a program portion of the next program-verify iteration, to reduce coupling effects on the storage elements which continue to be programmed. In subsequent program-verify iterations, the locked out storage elements are subject to full channel boosting. Or, the boosting can be stepped up over multiple program-verify iterations after lockout. The amount of channel boosting can be set by adjusting the timing of a channel pre-charge operation and by stepping up pass voltages which are applied to unselected word lines. The reduced channel boosting can be implemented for a range of program-verify iterations where the lockout condition is most likely to be first reached, for one or more target data states.
摘要翻译：在编程操作中，达到锁定状态的所选择的存储元件在下一个程序验证迭代的程序部分中经历减少的信道增强，以减少对继续被编程的存储元件的耦合效应。在随后的程序验证迭代中，锁定的存储元件进行全通道升压。或者，在锁定之后，可以通过多次程序验证迭代来加强升压。可以通过调整通道预充电操作的定时和通过加压施加到未选字线的通过电压来设置通道升压量。对于一个或多个目标数据状态，减少的信道增强可以针对最可能首先达到锁定条件的一系列程序验证迭代来实现。

13. 发明授权

US08310870B2 Natural threshold voltage distribution compaction in non-volatile memory 有权
标题翻译：非易失性存储器中的自然阈值电压分布压缩
公开(公告)号：US08310870B2
公开(公告)日：2012-11-13
申请号：US12849510
申请日：2010-08-03
申请人： Deepanshu Dutta , Jeffrey W. Lutze
发明人： Deepanshu Dutta , Jeffrey W. Lutze
IPC分类号： G11C11/34
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/3454 , G11C16/3459
摘要： In a non-volatile memory system, a programming speed-based slow down measure such as a raised bit line is applied to the faster-programming storage elements. A multi-phase programming operation which uses a back-and-forth word line order is performed in which programming speed data is stored in latches in one programming phase and read from the latches for use in a subsequent programming phase of a given word line. The faster and slower-programming storage elements can be distinguished by detecting when a number of storage elements reach a specified verify level, counting an additional number of program pulses which is set based on a natural threshold voltage distribution of the storage elements, and subsequently performing a read operation that separates the faster and slower programming storage elements. A drain-side select gate voltage can be adjusted in different programming phases to accommodate different bit line bias levels.
摘要翻译：在非易失性存储器系统中，基于速度的编程速度减慢测量例如升高的位线被应用于更快编程的存储元件。执行使用来回字线顺序的多相编程操作，其中编程速度数据被存储在一个编程阶段的锁存器中，并且从锁存器读取以用于给定字线的后续编程阶段。可以通过检测多个存储元件何时达到指定的验证电平，计数基于存储元件的自然阈值电压分布而设置的附加数量的编程脉冲，并且随后执行一种分离更快和慢速编程存储元件的读取操作。可以在不同的编程阶段调整漏极侧选择栅极电压，以适应不同的位线偏置电平。

14. 发明申请

US20120163083A1 ALTERNATE BIT LINE BIAS DURING PROGRAMMING TO REDUCE CHANNEL TO FLOATING GATE COUPLING IN MEMORY 有权
标题翻译：编程过程中的替代位线偏移，以减少通道到存储器中的门控耦合
公开(公告)号：US20120163083A1
公开(公告)日：2012-06-28
申请号：US12976893
申请日：2010-12-22
申请人： Deepanshu Dutta , Jeffrey W. Lutze
发明人： Deepanshu Dutta , Jeffrey W. Lutze
IPC分类号： G11C16/12 , G11C16/04 , G11C16/34
CPC分类号： G11C16/24 , G11C16/3418 , G11C16/3436
摘要： In a non-volatile storage system, capacitive coupling effects are reduced by reducing the probability that adjacent storage elements reach the lockout condition at close to the same program pulse. A slow down measure such as an elevated bit line voltage is applied to the storage elements of a word line which are associated with odd-numbered bit lines, but not to the storage elements associated with even-numbered bit lines. The elevated bit line voltage is applied over a range of program pulses, then stepped down to ground over one or more program pulses. The range of programming pulses over which the slow down measure is applied, can be fixed or determined adaptively. A program pulse increment can be dropped, then increased, when the bit line voltage is stepped down. Storage elements which are programmed to a highest target data state can be excluded from the slow down measure.
摘要翻译：在非易失性存储系统中，通过减少相邻存储元件在接近相同的编程脉冲时达到锁定状态的可能性来降低电容耦合效应。诸如升高的位线电压之类的减速措施被施加到与奇数位线相关联的字线的存储元件，而不是与与偶数位线相关联的存储元件。升高的位线电压施加在编程脉冲的范围上，然后通过一个或多个编程脉冲降压到地。施加减速措施的编程脉冲的范围可以自适应地固定或确定。当位线电压降低时，程序脉冲增量可以下降，然后增加。被编程为最高目标数据状态的存储元件可以从减速测量中排除。

15. 发明授权

US08169822B2 Data state-dependent channel boosting to reduce channel-to-floating gate coupling in memory 有权
标题翻译：数据状态相关通道升压以减少存储器中的通道至浮置栅极耦合
公开(公告)号：US08169822B2
公开(公告)日：2012-05-01
申请号：US12616269
申请日：2009-11-11
申请人： Deepanshu Dutta , Jeffrey W. Lutze , Grishma Shah
发明人： Deepanshu Dutta , Jeffrey W. Lutze , Grishma Shah
IPC分类号： G11C11/34
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/3427
摘要： In a programming operation, selected storage elements on a selected word line are programmed while unselected storage elements on the selected word line are inhibited from programming by channel boosting. To provide a sufficient but not excessive level of boosting, the amount of boosting can be set based on a data state of the unselected storage element. A greater amount of boosting can be provided for a lower data state which represents a lower threshold voltage and hence is more vulnerable to program disturb. A common boosting scheme can be used for groups of multiple data states. The amount of boosting can be set by adjusting the timing and magnitude of voltages used for a channel pre-charge operation and for pass voltages which are applied to word lines. In one approach, stepped pass voltages on unselected word lines can be used to adjust boosting for channels with selected data states.
摘要翻译：在编程操作中，选择的字线上的所选择的存储元件被编程，同时通过通道增强来禁止所选字线上的未选择的存储元件的编程。为了提供足够但不是过高的升压水平，可以基于未选择的存储元件的数据状态来设定升压量。可以为代表较低阈值电压的较低数据状态提供更大量的升压，因此更易受编程干扰的影响。一个共同的升压方案可以用于多个数据状态的组。可以通过调整用于通道预充电操作的电压的时序和幅度以及施加到字线的通过电压来设置升压量。在一种方法中，可以使用未选择字线上的阶梯式通过电压来调整具有所选数据状态的通道的升压。

16. 发明授权

US08051240B2 Compensating non-volatile storage using different pass voltages during program-verify and read 有权
标题翻译：在程序验证和读取期间使用不同的通过电压补偿非易失性存储器
公开(公告)号：US08051240B2
公开(公告)日：2011-11-01
申请号：US12118446
申请日：2008-05-09
申请人： Deepanshu Dutta , Jeffrey W. Lutze
发明人： Deepanshu Dutta , Jeffrey W. Lutze
IPC分类号： G06F12/00
CPC分类号： G11C16/0483 , B05B11/3098 , G11C11/5628 , G11C11/5642 , G11C16/26 , G11C16/3454 , G11C2211/5621
摘要： Optimized verify and read pass voltages are obtained to improve read accuracy in a non-volatile storage device. The optimized voltages account for changes in unselected storage element resistance when the storage elements become programmed. This change in resistance is referred to as a front pattern effect. In one approach, the verify pass voltage is higher than the read pass voltage, and a common verify voltage is applied on the source and drain sides of a selected word line. In other approaches, different verify pass voltages are applied on the source and drain sides of the selected word line. An optimization process can include determining a metric for different sets of verify and read pass voltages. The metric can indicate threshold voltage width, read errors or a decoding time or number of iterations of an ECC decoding engine.
摘要翻译：获得优化的验证和读取通过电压，以提高非易失性存储设备的读取精度。当存储元件变为编程时，优化的电压表示未选择的存储元件电阻的变化。这种电阻变化被称为前模式效应。在一种方法中，验证通过电压高于读取通过电压，并且在所选字线的源极和漏极侧施加公共验证电压。在其他方法中，不同的验证通过电压施加在所选字线的源极和漏极侧。优化过程可以包括确定不同组的验证和读取通过电压的度量。该度量可以指示ECC解码引擎的阈值电压宽度，读取错误或解码时间或迭代次数。

17. 发明申请

US20100097861A1 Multi-Pass Programming For Memory Using Word Line Coupling 有权
标题翻译：使用字线耦合的内存多通程序编程
公开(公告)号：US20100097861A1
公开(公告)日：2010-04-22
申请号：US12252727
申请日：2008-10-16
申请人： Deepanshu Dutta , Jeffrey W. Lutze
发明人： Deepanshu Dutta , Jeffrey W. Lutze
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/0483 , G11C11/5628 , G11C16/3418 , G11C16/3454 , G11C2211/5621 , G11C2211/5648
摘要： A multiple pass programming scheme is optimized using capacitive coupling in the word line to word line direction during program-verify operations. A different pass voltage is used in different programming passes on an adjacent word line of a selected word line which is being verified. In particular, a lower pass voltage can be used in a first pass than in a second pass. The programming process may involve a word line look ahead or zigzag sequence in which WLn is programmed in a first pass, followed by WLn+1 in a first pass, followed by WLn in a second pass, followed by WLn+1 in a second pass. An initial programming pass may be performed before the first pass in which storage elements are programmed to an intermediate state and/or to a highest state.
摘要翻译：在编程验证操作期间，使用字线到字线方向的电容耦合来优化多通道编程方案。在正在验证的所选择的字线的相邻字线上的不同的编程遍中使用不同的通过电压。特别地，可以在第一遍中比在第二遍中使用较低通过电压。编程过程可以包括字线前视或之字形序列，其中WLn在第一遍中编程，其次是第一遍中的WLn + 1，之后是第二遍中的WLn，之后是第二遍中的WLn + 1 。可以在其中存储元件被编程到中间状态和/或最高状态的第一遍之前执行初始编程遍。

18. 发明申请

US20100034022A1 COMPENSATING FOR COUPLING DURING READ OPERATIONS IN NON-VOLATILE STORAGE 有权
标题翻译：在非易失性存储中读取操作期间的耦合补偿
公开(公告)号：US20100034022A1
公开(公告)日：2010-02-11
申请号：US12188629
申请日：2008-08-08
申请人： Deepanshu Dutta , Jeffrey W. Lutze , Yingda Dong , Henry Chin , Toru Ishigaki
发明人： Deepanshu Dutta , Jeffrey W. Lutze , Yingda Dong , Henry Chin , Toru Ishigaki
IPC分类号： G11C16/06
CPC分类号： G11C11/5642 , G11C16/0483 , G11C16/24 , G11C16/3418
摘要： Capacitive coupling from storage elements on adjacent bit lines is compensated by adjusting voltages applied to the adjacent bit lines. An initial rough read is performed to ascertain the data states of the bit line-adjacent storage elements, and during a subsequent fine read, bit line voltages are set based on the ascertained states and the current control gate read voltage which is applied to a selected word line. When the current control gate read voltage corresponds to a lower data state than the ascertained state of an adjacent storage element, a compensating bit line voltage is used. Compensation of coupling from a storage element on an adjacent word line can also be provided by applying different read pass voltages to the adjacent word line, and obtaining read data using a particular read pass voltage which is identified based on a data state of the word line-adjacent storage element.
摘要翻译：通过调整施加到相邻位线的电压来补偿相邻位线上的存储元件的电容耦合。执行初始粗略读取以确定位线相邻存储元件的数据状态，并且在随后的精细读取期间，基于确定的状态和施加到所选择的电流控制栅极读取电压的电流控制栅极读取电压来设置位线电压字线。当电流控制栅极读取电压对应于比相邻存储元件的确定状态低的数据状态时，使用补偿位线电压。也可以通过对相邻字线应用不同的读通过电压来提供来自相邻字线上的存储元件的耦合的补偿，并且使用基于字线的数据状态来识别的特定读通过电压来获得读取数据相邻的存储元件。

19. 发明授权

US08385132B2 Alternate bit line bias during programming to reduce channel to floating gate coupling in memory 有权
标题翻译：在编程期间交替的位线偏置，以减少通道到存储器中的浮动栅极耦合
公开(公告)号：US08385132B2
公开(公告)日：2013-02-26
申请号：US12976893
申请日：2010-12-22
申请人： Deepanshu Dutta , Jeffrey W. Lutze
发明人： Deepanshu Dutta , Jeffrey W. Lutze
IPC分类号： G11C16/04
CPC分类号： G11C16/24 , G11C16/3418 , G11C16/3436
摘要： In a non-volatile storage system, capacitive coupling effects are reduced by reducing the probability that adjacent storage elements reach the lockout condition at close to the same program pulse. A slow down measure such as an elevated bit line voltage is applied to the storage elements of a word line which are associated with odd-numbered bit lines, but not to the storage elements associated with even-numbered bit lines. The elevated bit line voltage is applied over a range of program pulses, then stepped down to ground over one or more program pulses. The range of programming pulses over which the slow down measure is applied, can be fixed or determined adaptively. A program pulse increment can be dropped, then increased, when the bit line voltage is stepped down. Storage elements which are programmed to a highest target data state can be excluded from the slow down measure.
摘要翻译：在非易失性存储系统中，通过减少相邻存储元件在接近相同的编程脉冲时达到锁定状态的可能性来降低电容耦合效应。诸如升高的位线电压之类的减速措施被施加到与奇数位线相关联的字线的存储元件，而不是与与偶数位线相关联的存储元件。升高的位线电压施加在编程脉冲的范围上，然后通过一个或多个编程脉冲降压到地。施加减速措施的编程脉冲的范围可以自适应地固定或确定。当位线电压降低时，程序脉冲增量可以下降，然后增加。被编程为最高目标数据状态的存储元件可以从减速测量中排除。

20. 发明授权

US08274838B2 Programming non-volatile memory with bit line voltage step up 有权
标题翻译：用位线电压编程非易失性存储器
公开(公告)号：US08274838B2
公开(公告)日：2012-09-25
申请号：US12838902
申请日：2010-07-19
申请人： Deepanshu Dutta , Jeffrey W. Lutze
发明人： Deepanshu Dutta , Jeffrey W. Lutze
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/24 , G11C16/3454 , G11C16/3486 , G11C2216/14
摘要： Threshold voltage distributions in a non-volatile memory device are narrowed, and/or programming time is reduced, using a programming technique in which the bit line voltage for storage elements having a target data state is stepped up, in lock step with a step up in the program voltage. The step up in the bit line voltage is performed at different times in the programming pass, for different subsets of storage elements, according to their target data state. The start and stop of the step up in the bit line voltage can be set based on a fixed program pulse number, or adaptive based on a programming progress. Variations include using a fixed bit line step, a varying bit line step, a data state-dependent bit line step, an option to not step up the bit line for one or more data states and an option to add an additional bit line bias.
摘要翻译：使用编程技术使非易失性存储器件中的阈值电压分布变窄，并且/或编程时间减少，其中具有目标数据状态的存储元件的位线电压被升高，在升压锁定步骤中在编程电压。根据其目标数据状态，针对存储元件的不同子集，在编程遍历中的不同时刻对位线电压进行升压。可以基于固定的编程脉冲数或基于编程进度的自适应来设置位线电压中的升压的开始和停止。变化包括使用固定的位线步长，变化的位线步长，数据状态相关的位线步长，不增加一个或多个数据状态的位线的选项以及增加额外位线偏置的选项。

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