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11. 发明授权

US08077268B2 Thin film transistor substrate and method of manufacturing the same 有权
标题翻译：薄膜晶体管基板及其制造方法
公开(公告)号：US08077268B2
公开(公告)日：2011-12-13
申请号：US12140655
申请日：2008-06-17
申请人： Eun-Guk Lee , Chang-Oh Jeong , Je-Hun Lee , Do-Hyun Kim , Soon-Kwon Lim
发明人： Eun-Guk Lee , Chang-Oh Jeong , Je-Hun Lee , Do-Hyun Kim , Soon-Kwon Lim
IPC分类号： G02F1/13
CPC分类号： H01L27/1225 , H01L29/7869
摘要： A thin film transistor array substrate comprising a base substrate, a first wire on the base substrate, a first insulating layer on the base substrate to cover the first wire, a semiconductor layer on the first insulating layer, a second insulating layer on the first insulating layer on which the semiconductor layer is formed, and a second wire on the second insulating layer on the second insulating layer is provided, and a portion of the second wire makes contact with the semiconductor layer through the contact hole.
摘要翻译：一种薄膜晶体管阵列基板，包括基底基板，在基底基板上的第一布线，在基底基板上覆盖第一布线的第一绝缘层，第一绝缘层上的半导体层，第一绝缘层上的第二绝缘层设置有半导体层的层，第二绝缘层上的第二绝缘层上的第二布线，第二布线的一部分通过接触孔与半导体层接触。

12. 发明授权

US07998786B2 Method of manufacturing a TFT array panel 有权
标题翻译：制造TFT阵列面板的方法
公开(公告)号：US07998786B2
公开(公告)日：2011-08-16
申请号：US12369839
申请日：2009-02-12
申请人： Je-Hun Lee , Jae-Kyeong Lee , Chang-Oh Jeong , Beom-Seok Cho
发明人： Je-Hun Lee , Jae-Kyeong Lee , Chang-Oh Jeong , Beom-Seok Cho
IPC分类号： H01L21/00
CPC分类号： H01L29/66765 , H01L27/12 , H01L29/458 , H01L29/4908
摘要： Multi-layered wiring for a larger flat panel display is formed by depositing molybdenum on a substrate in presence of a precursor gas containing at least one oxygen, nitrogen and carbon to form a molybdenum layer. An aluminum layer is deposited on the molybdenum layer. Another metal layer may be formed on the aluminum layer. The molybdenum layer has a face-centered cubic (FCC) lattice structure with a preferred orientation of (111).
摘要翻译：在含有至少一个氧，氮和碳的前体气体的存在下，在基板上沉积钼以形成钼层，形成用于较大平板显示器的多层布线。铝层沉积在钼层上。可以在铝层上形成另一金属层。钼层具有面心立方（FCC）晶格结构，其优选取向为（111）。

13. 发明授权

US07863607B2 Thin film transistor array panel and manufacturing method thereof 有权
标题翻译：薄膜晶体管阵列面板及其制造方法
公开(公告)号：US07863607B2
公开(公告)日：2011-01-04
申请号：US11980871
申请日：2007-10-30
申请人： Je-Hun Lee , Do-Hyun Kim , Chang-Oh Jeong
发明人： Je-Hun Lee , Do-Hyun Kim , Chang-Oh Jeong
IPC分类号： H01L29/786
CPC分类号： H01L29/7869 , H01L27/1225
摘要： The disclosed thin film transistor array panel includes an insulating substrate, a channel layer including an oxide formed on the insulating substrate. A gate insulating is layer formed on the channel layer and a gate electrode is formed on the gate insulating layer. An interlayer insulating layer is formed on the gate electrode and a data line formed on the interlayer insulating layer and includes a source electrode, wherein the data line is made of a first conductive layer and a second conductive layer. A drain electrode formed on the interlayer insulating layer, and includes the first conductive layer and the second conductive layer. A pixel electrode extends from the first conductive layer of the drain electrode and a passivation layer formed on the data line and the drain electrode. A spacer formed on the passivation layer.
摘要翻译：所公开的薄膜晶体管阵列面板包括绝缘基板，包括形成在绝缘基板上的氧化物的沟道层。栅极绝缘层是在沟道层上形成的层，栅电极形成在栅极绝缘层上。在栅电极上形成层间绝缘层，形成在层间绝缘层上的数据线，包括源电极，其中数据线由第一导电层和第二导电层构成。一种形成在层间绝缘层上的漏极，包括第一导电层和第二导电层。像素电极从漏电极的第一导电层和形成在数据线和漏电极上的钝化层延伸。形成在钝化层上的间隔物。

14. 发明授权

US07843518B2 LCD aperture ratios 有权
标题翻译： LCD开口率
公开(公告)号：US07843518B2
公开(公告)日：2010-11-30
申请号：US11975968
申请日：2007-10-22
申请人： Sung-Hoon Yang , So-Woon Kim , Chong-Chul Chai , Chang-Oh Jeong , Eun-Guk Lee , Je-Hun Lee
发明人： Sung-Hoon Yang , So-Woon Kim , Chong-Chul Chai , Chang-Oh Jeong , Eun-Guk Lee , Je-Hun Lee
IPC分类号： G02F1/1343
CPC分类号： G02F1/136213 , G02F1/136227 , G02F2201/40
摘要： A display substrate includes respective pluralities of gate lines, data lines, switching elements, storage lines, pixel electrodes, and an organic insulation layer. The gate lines and the data lines define a plurality of unit pixels. The storage lines are respectively formed adjacent to the respective drain electrodes of the respective switching elements of respective rows of the unit pixels. The organic insulation layer has a hole that is formed within the area of each of the unit pixels and that extends from a contact area formed at a portion of the corresponding drain electrode of the pixel to a portion corresponding to the storage line thereof. This arrangement enables the marginal area needed to prevent mismatch of the hole in the areas of the contact area and the storage line to be reduced, thereby increasing the aperture ratio of the display.
摘要翻译：显示基板包括多条栅极线，数据线，开关元件，存储线，像素电极和有机绝缘层。栅极线和数据线限定多个单位像素。存储线分别形成为与各行的单位像素的各个开关元件的各个漏电极相邻。有机绝缘层具有形成在每个单位像素的区域内的孔，并且从形成在像素的相应漏电极的一部分的接触区域延伸到对应于其存储线的部分。这种布置使得能够减小接触区域和存储线的区域中的孔的失配所需的边缘区域，从而增加显示器的开口率。

15. 发明申请

US20090184315A1 THIN FILM TRANSISTOR ARRAY SUBSTRATE HAVING IMPROVED ELECTRICAL CHARACTERISTICS AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：具有改进的电气特性的薄膜晶体管阵列基板及其制造方法
公开(公告)号：US20090184315A1
公开(公告)日：2009-07-23
申请号：US12355646
申请日：2009-01-16
申请人： Je-Hun Lee , Kap-Soo Yoon , Kyung-Seok Son , Do-Hyun Kim , Chang-Oh Jeong
发明人： Je-Hun Lee , Kap-Soo Yoon , Kyung-Seok Son , Do-Hyun Kim , Chang-Oh Jeong
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/7869 , H01L27/1225 , H01L27/1296 , H01L29/4908
摘要： A thin film transistor array substrate, which can have high mobility of charge and can achieve uniform electrical characteristics for wide display devices, and a method of manufacturing the thin film transistor array substrate, are provided. The thin film transistor array substrate includes an oxide semiconductor layer having a channel and formed on an insulating substrate, a gate electrode overlapping the oxide semiconductor layer, a gate insulating film disposed between the oxide semiconductor layer and the gate electrode, and a passivation film formed on the oxide semiconductor layer and the gate electrode. At least one of the gate insulating film and the passivation film contains fluorine-containing silicon.
摘要翻译：提供了可以具有高电荷迁移率并且可以实现宽显示装置的均匀电特性的薄膜晶体管阵列基板，以及制造薄膜晶体管阵列基板的方法。薄膜晶体管阵列基板包括具有通道并形成在绝缘基板上的氧化物半导体层，与氧化物半导体层重叠的栅极电极，设置在氧化物半导体层和栅电极之间的栅极绝缘膜，以及形成的钝化膜在氧化物半导体层和栅电极上。栅极绝缘膜和钝化膜中的至少一个含有含氟硅。

16. 发明申请

US20080142797A1 Thin film transistor, thin film transistor substate, and method of manufacturing the same 有权
标题翻译：薄膜晶体管，薄膜晶体管子状态及其制造方法
公开(公告)号：US20080142797A1
公开(公告)日：2008-06-19
申请号：US12001031
申请日：2007-12-06
申请人： Eun-Guk Lee , Do-Hyun Kim , Chang-Oh Jeong , Je-Hun Lee , Soon-Kwon Lim
发明人： Eun-Guk Lee , Do-Hyun Kim , Chang-Oh Jeong , Je-Hun Lee , Soon-Kwon Lim
IPC分类号： H01L29/22 , H01L21/84
CPC分类号： H01L27/124 , H01L27/1214 , H01L27/1225 , H01L27/1288 , H01L29/45 , H01L29/7869
摘要： A thin film transistor substrate and a method of manufacturing the same are disclosed. The method of manufacturing a thin film transistor substrate includes forming a first conductive pattern group including a gate line, a gate electrode, and a lower gate pad electrode on a substrate, forming a gate insulating layer on the substrate on which the first conductive pattern group is formed, forming an oxide semiconductor pattern overlapping the gate electrode on the gate insulating layer, and forming first and second conductive layers on the substrate on which the oxide semiconductor pattern is formed and patterning the first and second conductive layers to form a second conductive pattern group including a data line, a source electrode, a drain electrode, and a data pad.
摘要翻译：公开了一种薄膜晶体管基板及其制造方法。制造薄膜晶体管基板的方法包括在基板上形成包括栅极线，栅电极和下栅极焊盘电极的第一导电图案组，在基板上形成栅极绝缘层，第一导电图案组形成，在所述栅极绝缘层上形成与所述栅电极重叠的氧化物半导体图案，以及在其上形成有所述氧化物半导体图案的所述基板上形成第一和第二导电层，并且对所述第一导电层和所述第二导电层进行构图以形成第二导电图案包括数据线，源电极，漏电极和数据焊盘。

17. 发明授权

US07352004B2 Thin film transistor array panel and method for manufacturing the same 有权
标题翻译：薄膜晶体管阵列面板及其制造方法
公开(公告)号：US07352004B2
公开(公告)日：2008-04-01
申请号：US11249500
申请日：2005-10-14
申请人： Je-Hun Lee , Yang-Ho Bae , Beom-Seok Cho , Chang-Oh Jeong
发明人： Je-Hun Lee , Yang-Ho Bae , Beom-Seok Cho , Chang-Oh Jeong
IPC分类号： H01L29/04 , H01L29/10 , H01L31/00
CPC分类号： H01L27/3279 , H01L27/124 , H01L27/1288 , H01L51/0023 , H01L51/56
摘要： The invention provides a thin film transistor (TFT) array panel that includes an insulating substrate; a gate line formed on the insulating substrate and having a first layer of an Al containing metal, a second layer of a Cu containing metal that is thicker than the first layer, and a gate electrode; a gate insulating layer arranged on the gate line; a semiconductor arranged on the gate insulating layer; a data line having a source electrode and arranged on the gate insulating layer and the semiconductor; a drain electrode arranged on the gate insulating layer and the semiconductor and facing the source electrode; a passivation layer having a contact hole and arranged on the data line and the drain electrode; and a pixel electrode arranged on the passivation layer and coupled with the drain electrode through the contact hole.
摘要翻译：本发明提供一种薄膜晶体管（TFT）阵列面板，其包括绝缘基板; 形成在所述绝缘基板上并具有含有Al的金属的第一层，比所述第一层更厚的含Cu金属的第二层的栅极线和栅电极; 栅极绝缘层，布置在栅极线上; 布置在栅绝缘层上的半导体; 数据线，其具有源电极并且布置在所述栅极绝缘层和所述半导体上; 布置在所述栅绝缘层和所述半导体上并面对所述源电极的漏电极; 钝化层，其具有接触孔并且布置在所述数据线和所述漏电极上; 以及设置在钝化层上并通过接触孔与漏电极耦合的像素电极。

18. 发明申请

US20060102907A1 Thin film transistor array panel and method for manufacturing the same 有权
标题翻译：薄膜晶体管阵列面板及其制造方法
公开(公告)号：US20060102907A1
公开(公告)日：2006-05-18
申请号：US11228852
申请日：2005-09-16
申请人： Je-Hun Lee , Yang-Ho Bae , Beom-Seok Cho , Chang-Oh Jeong
发明人： Je-Hun Lee , Yang-Ho Bae , Beom-Seok Cho , Chang-Oh Jeong
IPC分类号： H01L29/04
CPC分类号： H01L27/1214 , H01L27/1225 , H01L27/124
摘要： The present invention provides a thin film transistor array panel comprising an insulating substrate; a gate line formed on the insulating substrate; a gate insulating layer formed on the gate line; a drain electrode and a data line having a source electrode formed on the gate insulating layer, the drain electrode being adjacent to the source electrode with a gap therebetween; and a pixel electrode coupled to the drain electrode, wherein at least one of the gate line, the data line, and the drain electrode comprises a first conductive layer comprising a conductive oxide and a second conductive layer comprising copper (Cu).
摘要翻译：本发明提供一种薄膜晶体管阵列板，其包括绝缘基板; 形成在所述绝缘基板上的栅极线; 栅极绝缘层，形成在栅极线上; 漏电极和数据线，其具有形成在所述栅极绝缘层上的源电极，所述漏电极与所述源电极相邻，其间具有间隙; 以及耦合到所述漏电极的像素电极，其中所述栅极线，所述数据线和所述漏电极中的至少一个包括包括导电氧化物的第一导电层和包含铜（Cu）的第二导电层。

19. 发明授权

US07919795B2 Wire structure, method for fabricating wire, thin film transistor substrate, and method for fabricating the thin film transistor substrate 有权
标题翻译：线结构，制造线的方法，薄膜晶体管基板以及制造薄膜晶体管基板的方法
公开(公告)号：US07919795B2
公开(公告)日：2011-04-05
申请号：US11961149
申请日：2007-12-20
申请人： Je-Hun Lee , Chang-Oh Jeong , Eun-Guk Lee , Do-Hyun Kim
发明人： Je-Hun Lee , Chang-Oh Jeong , Eun-Guk Lee , Do-Hyun Kim
IPC分类号： H01L29/76 , H01L29/40 , H01L29/43 , H01L29/49 , H01L33/00
CPC分类号： H01L29/458 , H01L27/124 , H01L29/4908
摘要： Provided are a wire structure, a method for fabricating a wire, a thin film transistor (TFT) substrate and a method for fabricating a TFT substrate. The wire structure includes a barrier layer formed on a substrate and including copper, copper solid solution layer.
摘要翻译：提供线结构，制造线的方法，薄膜晶体管（TFT）基板和制造TFT基板的方法。导线结构包括形成在基板上并包括铜，铜固溶体层的阻挡层。

20. 发明申请

US20110065220A1 THIN FILM TRANSISTOR ARRAY PANEL AND METHOD FOR MANUFACTURING THE SAME 失效
标题翻译：薄膜晶体管阵列及其制造方法
公开(公告)号：US20110065220A1
公开(公告)日：2011-03-17
申请号：US12951981
申请日：2010-11-22
申请人： Je-Hun LEE , Beom-Seok Cho , Chang-Oh Jeong , Joo-Han Kim
发明人： Je-Hun LEE , Beom-Seok Cho , Chang-Oh Jeong , Joo-Han Kim
IPC分类号： H01L21/336
CPC分类号： H01L27/124 , H01L27/1288 , H01L29/12 , H01L29/458
摘要： The present invention provides a thin film transistor array panel comprising: an insulating substrate; a gate line formed on the insulating substrate and having a gate electrode; a gate insulating layer formed on the gate line; a semiconductor formed on the gate insulating layer and overlapping the gate electrode; diffusion barriers formed on the semiconductor and containing nitrogen; a data line crossing the gate line and having a source electrode partially contacting the diffusion barriers; a drain electrode partially contacting the diffusion barriers and facing the source electrode on the gate electrode; and a pixel electrode electrically connected to the drain electrode.
摘要翻译：本发明提供一种薄膜晶体管阵列板，包括：绝缘基板; 形成在所述绝缘基板上并具有栅电极的栅极线; 栅极绝缘层，形成在栅极线上; 形成在栅极绝缘层上并与栅电极重叠的半导体; 在半导体上形成并含有氮的扩散阻挡层; 跨越栅极线并且具有部分地接触扩散阻挡层的源电极的数据线; 漏电极部分地接触扩散阻挡层并面对栅电极上的源电极; 以及电连接到漏电极的像素电极。

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