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11. 发明授权

US09843309B2 Receiver with time-varying threshold voltage 有权
公开(公告)号：US09843309B2
公开(公告)日：2017-12-12
申请号：US13393314
申请日：2010-11-10
申请人： Jared L. Zerbe , Brian S. Leibowitz , Qi Lin
发明人： Jared L. Zerbe , Brian S. Leibowitz , Qi Lin
IPC分类号： H04L25/34 , H03K3/013 , G11C7/02 , H03K5/153 , H04L25/49 , H04L25/06 , H04L25/03
CPC分类号： H03K3/013 , G11C7/02 , H03K5/153 , H04L25/03057 , H04L25/066 , H04L25/4902 , H04L25/4917
摘要： A system for communicating information between circuits is described. A transmit circuit provides pulse-amplitude-modulation (PAM) signals via a communication channel to a receiver. A circuit in the receiver determines digital values from the received signals using a time-varying threshold voltage, which varies during the bit-time. This approach may compensate for inter-symbol interference (ISI) to increase the voltage and timing margins of the system.

12. 发明申请

US20130241622A1 RECEIVER WITH TIME-VARYING THRESHOLD VOLTAGE 审中-公开
标题翻译：接收器具有时变阈值电压
公开(公告)号：US20130241622A1
公开(公告)日：2013-09-19
申请号：US13393314
申请日：2010-11-10
申请人： Jared L. Zerbe , Brian S. Leibowitz , Qi Lin
发明人： Jared L. Zerbe , Brian S. Leibowitz , Qi Lin
IPC分类号： H03K3/013 , H03K5/153
CPC分类号： H03K3/013 , G11C7/02 , H03K5/153 , H04L25/03057 , H04L25/066 , H04L25/4902 , H04L25/4917
摘要： A system for communicating information between circuits is described. A transmit circuit provides pulse-amplitude-modulation (PAM) signals via a communication channel to a receiver. A circuit in the receiver determines digital values from the received signals using a time-varying threshold voltage, which varies during the bit-time. This approach may compensate for inter-symbol interference (ISI) to increase the voltage and timing margins of the system.
摘要翻译：描述用于在电路之间传送信息的系统。发射电路经由通信信道向接收机提供脉冲幅度调制（PAM）信号。接收器中的一个电路使用随时间变化的阈值电压来确定来自接收信号的数字值，其在比特时间期间变化。该方法可以补偿符号间干扰（ISI）以增加系统的电压和时序余量。

13. 发明授权

US08941420B2 Low-latency, frequency-agile clock multiplier 有权
标题翻译：低延迟，频率敏捷的时钟倍频器
公开(公告)号：US08941420B2
公开(公告)日：2015-01-27
申请号：US13983836
申请日：2012-05-24
申请人： Jared L. Zerbe , Brian S. Leibowitz , Masum Hossain
发明人： Jared L. Zerbe , Brian S. Leibowitz , Masum Hossain
IPC分类号： H03B19/00 , H03K5/00 , H03L7/06 , H03L7/099
CPC分类号： H03L7/16 , H03J2200/10 , H03K3/0315 , H03K5/00006 , H03K5/13 , H03K5/14 , H03L7/06 , H03L7/0995 , H03L7/24
摘要： In a first clock frequency multiplier, multiple injection-locked oscillators (ILOs) having spectrally-staggered lock ranges are operated in parallel to effect a collective input frequency range substantially wider than that of a solitary ILO. After each input frequency change, the ILO output clocks may be evaluated according to one or more qualifying criteria to select one of the ILOs as the final clock source. In a second clock frequency multiplier, a flexible-injection-rate injection-locked oscillator locks to super-harmonic, sub-harmonic or at-frequency injection pulses, seamlessly transitioning between the different injection pulse rates to enable a broad input frequency range. The frequency multiplication factor effected by the first and/or second clock frequency multipliers in response to an input clock is determined on the fly and then compared with a programmed (desired) multiplication factor to select between different frequency-divided instances of the frequency-multiplied clock.
摘要翻译：在第一时钟频率倍增器中，具有光谱交错锁定范围的多个注入锁定振荡器（ILO）并行操作，以实现基本上比孤立的国际劳工组织的输入频率范围更宽的集体输入频率范围。在每个输入频率变化之后，可以根据一个或多个限定条件评估国际劳工组织输出时钟，以选择其中一个ILO作为最终的时钟源。在第二个时钟倍频器中，灵活注入速率的注入锁定振荡器锁定到超谐波，次谐波或全频率注入脉冲，在不同的注入脉冲速率之间无缝转换，以实现宽的输入频率范围。响应于输入时钟由第一和/或第二时钟频率乘法器影响的倍频因子在飞行中确定，然后与编程的（期望的）乘法因子进行比较，以在频率乘法器的不同分频实例之间进行选择时钟。

14. 发明授权

US08824222B2 Fast-wake memory 有权
标题翻译：快速唤醒记忆
公开(公告)号：US08824222B2
公开(公告)日：2014-09-02
申请号：US13702112
申请日：2011-08-04
申请人： Frederick A. Ware , Jared L. Zerbe , Brian S. Leibowitz
发明人： Frederick A. Ware , Jared L. Zerbe , Brian S. Leibowitz
IPC分类号： G11C7/22 , G11C5/14
CPC分类号： G06F1/3275 , G06F1/324 , G06F3/0625 , G06F3/0659 , G06F3/0673 , G06F2213/0038 , G11C5/14 , G11C5/148 , G11C7/04 , G11C7/22 , G11C7/222 , G11C11/4072 , G11C11/4076 , G11C2207/2227 , G11C2207/2254
摘要： One or more timing signals used to time data and command transmission over highspeed data and command signaling links are paused or otherwise disabled when a memory system enters a low-power state, and require substantial time to be re-established at appropriate frequency and/or phase as the system returns to an active operating state. Instead of waiting for the high-speed timing signals to be re-established before beginning memory access operations, an alternative, lower-frequency timing source is used to time transfer of one or more memory-access commands over a combination of data and command signaling links while the high-speed timing signals are being restored, thereby hastening transmission of memory-access commands to memory devices and reducing the incremental latency required to exit the low-power state. A timing signal generators capable of glitchlessly shifting a timing signal between two or more oscillation frequencies may also (or alternatively) be provided, thus enabling different-frequency timing signals to be delivered to system components via the same timing signal paths in either operating state. When the timing signal is used to time data (or command) transfer over information-bearing signaling links, the ability to glitchlessly shift the timing signal frequency enables a corresponding glitchless shift between lower and higher data rates on the information-bearing signaling links.
摘要翻译：当存储器系统进入低功率状态时，用于对高速数据和命令信令链路进行时间数据和命令传输的一个或多个定时信号被暂停或者被禁用，并且需要相当长的时间以适当的频率和/或系统返回到活动状态。代替在开始存储器访问操作之前等待重新建立高速定时信号，替代的低频定时源用于通过数据和命令信令的组合来对一个或多个存储器访问命令进行时间传送链路同时高速定时信号被恢复，从而加快了对存储器件的存储器访问命令的传输，并减少了退出低功率状态所需的增量等待时间。也可以（或替代地）提供能够在两个或更多个振荡频率之间无差错地移位定时信号的定时信号发生器，从而使得能够在任一操作状态下通过相同的定时信号路径将不同频率的定时信号传送到系统组件。当使用定时信号来通过信息承载信令链路对数据（或命令）进行时间传输时，无信号地移动定时信号频率的能力使能够在信息载体信令链路上的较低和较高数据速率之间相应的无间隙移位。

15. 发明申请

US20130227329A1 USING A STUTTERED CLOCK SIGNAL TO REDUCE SELF-INDUCED VOLTAGE NOISE 审中-公开
标题翻译：使用经调制的时钟信号来减少自感电压噪声
公开(公告)号：US20130227329A1
公开(公告)日：2013-08-29
申请号：US13883265
申请日：2011-10-31
申请人： Brian S. Leibowitz , Jared L. Zerbe
发明人： Brian S. Leibowitz , Jared L. Zerbe
IPC分类号： G06F1/12
CPC分类号： G06F1/12 , G06F1/08 , G06F1/3237 , Y02D10/128 , Y02D50/20
摘要： The disclosed embodiments relate to a technique that uses a modified timing signal to reduce self-induced voltage noise in a synchronous system. During a transient period associated with a deterministic event in the synchronous system, the technique uses a modified timing signal generated based on a normal timing signal as a timing signal for the synchronous system. Outside of the transient period, the technique uses the normal timing as the timing signal for the synchronous system. In some embodiments, the modified timing signal is generated by skipping a pattern of
摘要翻译：所公开的实施例涉及使用修改的定时信号来减少同步系统中的自感应电压噪声的技术。在与同步系统中的确定性事件相关联的瞬态时段期间，该技术使用基于正常定时信号生成的经修改的定时信号作为同步系统的定时信号。在瞬态周期之外，该技术使用正常定时作为同步系统的定时信号。在一些实施例中，经修改的定时信号通过跳过图案来产生

16. 发明授权

US08667347B2 Active calibration for high-speed memory devices 有权
标题翻译：高速存储设备的主动校准
公开(公告)号：US08667347B2
公开(公告)日：2014-03-04
申请号：US13130515
申请日：2009-12-29
申请人： Jared L. Zerbe , Frederick A. Ware , Brian S. Leibowitz
发明人： Jared L. Zerbe , Frederick A. Ware , Brian S. Leibowitz
IPC分类号： G11C29/00
CPC分类号： G06F13/1689
摘要： A system for calibrating timing for write operations between a memory controller and a memory device. During operation, the system identifies a time gap required to transition from writing data from the memory controller to the memory device to reading data from the memory device to the memory controller. The system then transmits a test data pattern to the memory device within the time gap. The system subsequently uses the received test data pattern to calibrate a phase relationship between a received timing signal and data transmitted from the memory controller to the memory device during write operations.
摘要翻译：一种用于校准存储器控制器和存储器件之间的写操作的定时的系统。在操作期间，系统识别从从存储器控制器写入数据到存储器件以从存储器件读取数据到存储器控制器的转换所需的时间间隔。系统然后在时间间隙内将测试数据模式发送到存储器件。该系统随后使用所接收的测试数据模式来校准在写入操作期间所接收的定时信号和从存储器控制器发送到存储器件的数据之间的相位关系。

17. 发明申请

US20110239063A1 ACTIVE CALIBRATION FOR HIGH-SPEED MEMORY DEVICES 有权
标题翻译：高速存储器件的主动校准
公开(公告)号：US20110239063A1
公开(公告)日：2011-09-29
申请号：US13130515
申请日：2009-12-29
申请人： Jared L. Zerbe , Frederick A. Ware , Brian S. Leibowitz
发明人： Jared L. Zerbe , Frederick A. Ware , Brian S. Leibowitz
IPC分类号： G06F11/16 , G06F12/00
CPC分类号： G06F13/1689
摘要： A system for calibrating timing for write operations between a memory controller and a memory device is described. During operation, the system identifies a time gap required to transition from writing data from the memory controller to the memory device to reading data from the memory device to the memory controller. The system then transmits a test data pattern to the memory device within the time gap. The system subsequently uses the received test data pattern to calibrate a phase relationship between a received timing signal and data transmitted from the memory controller to the memory device during write operations.
摘要翻译：描述了用于校准存储器控制器和存储器件之间的写入操作的定时的系统。在操作期间，系统识别从从存储器控制器写入数据到存储器件以从存储器件读取数据到存储器控制器的转换所需的时间间隔。系统然后在时间间隙内将测试数据模式发送到存储器件。该系统随后使用所接收的测试数据模式来校准在写入操作期间所接收的定时信号和从存储器控制器发送到存储器件的数据之间的相位关系。

18. 发明授权

US09094238B2 High-speed signaling systems with adaptable pre-emphasis and equalization 有权
公开(公告)号：US09094238B2
公开(公告)日：2015-07-28
申请号：US13216047
申请日：2011-08-23
申请人： Jared L. Zerbe , Fred F. Chen , Andrew Ho , Ramin Farjad-Rad , John W. Poulton , Kevin S. Donnelly , Brian S. Leibowitz
发明人： Jared L. Zerbe , Fred F. Chen , Andrew Ho , Ramin Farjad-Rad , John W. Poulton , Kevin S. Donnelly , Brian S. Leibowitz
IPC分类号： H03H7/30 , H03H7/40 , H03K5/159 , H04L27/01 , H04L1/00 , H04L7/033 , H04L25/03 , H04L25/497 , H04W52/20 , H04L7/00 , H04L25/02 , H04W52/22
CPC分类号： H04L27/01 , H04L1/0026 , H04L7/0025 , H04L7/0087 , H04L7/0337 , H04L25/0272 , H04L25/028 , H04L25/03057 , H04L25/03343 , H04L25/03885 , H04L25/497 , H04L2025/03503 , H04W52/20 , H04W52/225 , Y02D70/00
摘要： A signaling system includes a pre-emphasizing transmitter and an equalizing receiver coupled to one another via a high-speed signal path. The receiver measures the quality of data conveyed from the transmitter. A controller uses this information and other information to adaptively establish appropriate transmit pre-emphasis and receive equalization settings, e.g. to select the lowest power setting for which the signaling system provides some minimum communication bandwidth without exceeding a desired bit-error rate.

19. 发明授权

US08989249B2 High-speed signaling systems with adaptable pre-emphasis and equalization 有权
标题翻译：具有适应性预加重和均衡的高速信号系统
公开(公告)号：US08989249B2
公开(公告)日：2015-03-24
申请号：US13215951
申请日：2011-08-23
申请人： Jared L. Zerbe , Fred F. Chen , Andrew Ho , Ramin Farjad-Rad , John W. Poulton , Kevin S. Donnelly , Brian S. Leibowitz
发明人： Jared L. Zerbe , Fred F. Chen , Andrew Ho , Ramin Farjad-Rad , John W. Poulton , Kevin S. Donnelly , Brian S. Leibowitz
IPC分类号： H03H7/30 , H03H7/40 , H03K5/159 , H04L27/01 , H04L1/00 , H04L7/033 , H04L25/03 , H04L25/497 , H04W52/20 , H04L7/00 , H04L25/02 , H04W52/22
CPC分类号： H04L27/01 , H04L1/0026 , H04L7/0025 , H04L7/0087 , H04L7/0337 , H04L25/0272 , H04L25/028 , H04L25/03057 , H04L25/03343 , H04L25/03885 , H04L25/497 , H04L2025/03503 , H04W52/20 , H04W52/225 , Y02D70/00
摘要： A signaling system includes a pre-emphasizing transmitter and an equalizing receiver coupled to one another via a high-speed signal path. The receiver measures the quality of data conveyed from the transmitter. A controller uses this information and other information to adaptively establish appropriate transmit pre-emphasis and receive equalization settings, e.g. to select the lowest power setting for which the signaling system provides some minimum communication bandwidth without exceeding a desired bit-error rate.
摘要翻译：一个信令系统包括一个预先强调的发射机和一个通过高速信号路径相互耦合的均衡接收机。接收机测量从发射机传送的数据的质量。控制器使用该信息和其他信息来自适应地建立适当的发送预加重和接收均衡设置，例如，选择信令系统提供一些最小通信带宽而不超过所需误码率的最低功率设置。

20. 发明授权

US10401900B2 Using a stuttered clock signal to reduce self-induced voltage noise 有权
公开(公告)号：US10401900B2
公开(公告)日：2019-09-03
申请号：US13883265
申请日：2011-10-31
申请人： Brian S. Leibowitz , Jared L. Zerbe
发明人： Brian S. Leibowitz , Jared L. Zerbe
IPC分类号： G06F1/08 , G06F1/12 , G06F1/3237
摘要： The disclosed embodiments relate to a technique that uses a modified timing signal to reduce self-induced voltage noise in a synchronous system. During a transient period associated with a deterministic event in the synchronous system, the technique uses a modified timing signal generated based on a normal timing signal as a timing signal for the synchronous system. Outside of the transient period, the technique uses the normal timing as the timing signal for the synchronous system. In some embodiments, the modified timing signal is generated by skipping a pattern of clock transitions in the normal timing signal.

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