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11. 发明授权

US08390120B2 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08390120B2
公开(公告)日：2013-03-05
申请号：US12913748
申请日：2010-10-27
申请人： Kwang-Jin Moon , Pil-Kyu Kang , Dae-Lok Bae , Gil-Heyun Choi , Byung-Lyul Park , Dong-Chan Lim , Deok-Young Jung
发明人： Kwang-Jin Moon , Pil-Kyu Kang , Dae-Lok Bae , Gil-Heyun Choi , Byung-Lyul Park , Dong-Chan Lim , Deok-Young Jung
IPC分类号： H01L23/48
CPC分类号： H01L25/0657 , H01L23/481 , H01L23/528 , H01L2224/16146 , H01L2225/06541 , H01L2924/01327 , H01L2924/00
摘要： A semiconductor device includes a via structure and a conductive structure. The via structure has a surface with a planar portion and a protrusion portion. The conductive structure is formed over at least part of the planar portion and not over at least part of the protrusion portion of the via structure. For example, the conductive structure is formed only onto the planar portion and not onto any of the protrusion portion for forming high quality connection between the conductive structure and the via structure.
摘要翻译：半导体器件包括通孔结构和导电结构。通孔结构具有平坦部分和突出部分的表面。导电结构形成在平面部分的至少一部分上，而不是在通孔结构的突出部分的至少一部分之上。例如，导电结构仅形成在平面部分上，而不形成在任何突出部分上，用于在导电结构和通孔结构之间形成高质量的连接。

12. 发明申请

US20130005141A1 SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130005141A1
公开(公告)日：2013-01-03
申请号：US13616910
申请日：2012-09-14
申请人： Jin-Ho Park , Gil-Heyun Choi , Byung-Lyul Park , Jong-Myeong Lee , Zung-Sun Choi , Hye-Kyung Jung
发明人： Jin-Ho Park , Gil-Heyun Choi , Byung-Lyul Park , Jong-Myeong Lee , Zung-Sun Choi , Hye-Kyung Jung
IPC分类号： H01L21/768
CPC分类号： H01L21/76846 , H01L21/28562 , H01L21/76856 , H01L23/53223 , H01L23/53238 , H01L23/53252 , H01L27/10855 , H01L27/11521 , H01L27/11524 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device can include an insulation layer on that is on a substrate on which a plurality of lower conductive structures are formed, where the insulation layer has an opening. A barrier layer is on a sidewall and a bottom of the opening of the insulation layer, where the barrier layer includes a first barrier layer in which a constituent of a first deoxidizing material is richer than a metal material in the first barrier layer and a second barrier layer in which a metal material in the second barrier layer is richer than a constituent of a second deoxidizing material. An interconnection is in the opening of which the sidewall and the bottom are covered with the barrier layer, the interconnection is electrically connected to the lower conductive structure.
摘要翻译：半导体器件可以包括在其上形成有多个下导电结构的基板上的绝缘层，其中绝缘层具有开口。阻挡层位于绝缘层的开口的侧壁和底部上，其中阻挡层包括第一阻挡层，第一脱氧材料的成分比第一阻挡层中的金属材料更富，第二阻隔层阻挡层，其中第二阻挡层中的金属材料比第二脱氧材料的成分更富。互连在其开口中，侧壁和底部被阻挡层覆盖，互连电连接到下导电结构。

13. 发明申请

US20100230824A1 Metal Interconnect of Semiconductor Device 有权
标题翻译：半导体器件的金属互连
公开(公告)号：US20100230824A1
公开(公告)日：2010-09-16
申请号：US12722643
申请日：2010-03-12
申请人： Jongmyeong Lee , Zungsun Choi , Gilheyun Choi , Byung-Lyul Park , Jinho Park , Hye Kyung Jung
发明人： Jongmyeong Lee , Zungsun Choi , Gilheyun Choi , Byung-Lyul Park , Jinho Park , Hye Kyung Jung
IPC分类号： H01L23/48
CPC分类号： H01L23/528 , H01L23/5226 , H01L23/53214 , H01L23/53228 , H01L2924/0002 , H01L2924/00
摘要： Provided are a metal interconnect of a semiconductor device and a method of fabricating the metal interconnect. The metal interconnect includes a metal line having a first end and a second end disposed on an opposite side to the first end, a via electrically connected to the metal line, and a non-active segment extending from the first end and including a void. Tensile stress is decreased to prevent a void from occurring under the via. Accordingly, line breakage due to electromigration is substantially prevented, thus improving electrical characteristics of the device.
摘要翻译：提供半导体器件的金属互连和制造金属互连的方法。金属互连包括金属线，其具有设置在与第一端相对的第一端和第二端，电连接到金属线的通孔和从第一端延伸并且包括空隙的非活性段。减小拉伸应力以防止孔下方发生空隙。因此，基本上防止了电迁移引起的线路断线，从而提高了器件的电气特性。

14. 发明授权

US06211082B1 Chemical vapor deposition of tungsten using nitrogen-containing gas 失效
标题翻译：使用含氮气体化学气相沉积钨
公开(公告)号：US06211082B1
公开(公告)日：2001-04-03
申请号：US09021462
申请日：1998-02-10
申请人： Bong-young Yoo , Byung-Lyul Park , Dae-hong Ko , Sang-in Lee
发明人： Bong-young Yoo , Byung-Lyul Park , Dae-hong Ko , Sang-in Lee
IPC分类号： H01L2144
CPC分类号： C23C16/08 , H01L21/28568
摘要： A tungsten or other metal layer is chemical vapor deposited using a source gas containing tungsten, a reducing gas and a nitrogen-containing gas. The nitrogen-containing gas can act as a surface roughness reducing gas that reduces the roughness of the tungsten layer compared to a tungsten layer that is chemical vapor deposited using the source gas containing tungsten and the reducing gas, but without using the surface roughness reducing gas. Viewed in another way, the nitrogen-containing gas acts as a growth rate controlling gas that produces uniform growth of the tungsten layer in a plurality of directions compared to a tungsten layer that is deposited using the source gas containing tungsten and the reducing gas, but without using the growth rate controlling gas.
摘要翻译：使用含有钨，还原气体和含氮气体的源气体化学气相沉积钨或其它金属层。与使用含有钨和还原气体的源气体进行化学气相沉积的钨层相比，含氮气体可以用作表面粗糙度降低气体，其降低钨层的粗糙度，但不使用表面粗糙度还原气体。以另一种方式看，与使用含钨和还原气体的源气体沉积的钨层相比，含氮气体充当生长速率控制气体，其产生钨层在多个方向上的均匀生长，但是而不用生长速率控制气体。

15. 发明申请

US20140021633A1 Integrated Circuit Device Having Through-Silicon-Via Structure and Method of Manufacturing the Same 有权
标题翻译：具有通硅结构的集成电路装置及其制造方法
公开(公告)号：US20140021633A1
公开(公告)日：2014-01-23
申请号：US13919580
申请日：2013-06-17
申请人： Do-Sun Lee , Kun-Sang Park , Byung-Lyul Park , Seong-min Son , Gil-heyun Choi
发明人： Do-Sun Lee , Kun-Sang Park , Byung-Lyul Park , Seong-min Son , Gil-heyun Choi
IPC分类号： H01L23/522
CPC分类号： H01L23/5226 , H01L21/2885 , H01L21/76898 , H01L23/3128 , H01L23/481 , H01L23/49827 , H01L25/0657 , H01L2224/0401 , H01L2224/05 , H01L2224/05009 , H01L2224/06181 , H01L2224/13 , H01L2224/16146 , H01L2224/73104 , H01L2924/13091 , H01L2924/1461 , H01L2924/00
摘要： An integrated circuit device including a through-silicon-via (TSV) structure and methods of manufacturing the same are provided. The integrated circuit device may include the TSV structure penetrating through a semiconductor structure. The TSV structure may include a first through electrode unit including impurities of a first concentration and a second through electrode unit including impurities of a second concentration greater than the first concentration.
摘要翻译：提供了一种包括贯穿硅通孔（TSV）结构的集成电路器件及其制造方法。集成电路器件可以包括穿透半导体结构的TSV结构。 TSV结构可以包括包括第一浓度的杂质的第一通过电极单元和包括大于第一浓度的第二浓度的杂质的第二通过电极单元。

16. 发明授权

US08546162B2 Method for forming light guide layer in semiconductor substrate 有权
标题翻译：在半导体衬底中形成导光层的方法
公开(公告)号：US08546162B2
公开(公告)日：2013-10-01
申请号：US13243763
申请日：2011-09-23
申请人： Dae-Lok Bae , Byung-Lyul Park , Pil-Kyu Kang , Gil-Heyun Choi , Kwang-Jin Moon
发明人： Dae-Lok Bae , Byung-Lyul Park , Pil-Kyu Kang , Gil-Heyun Choi , Kwang-Jin Moon
IPC分类号： H01L21/00
CPC分类号： G02B6/138 , G02B6/136
摘要： A method for forming a light guide layer with improved transmission reliability in a semiconductor substrate, the method including forming a trench in the semiconductor substrate, forming a cladding layer and a preliminary light guide layer in the trench such that only one of opposite side end portions of the preliminary light guide layer is in contact with an inner sidewall of the trench, and performing a thermal treatment on the substrate to change the preliminary light guide layer into the light guide layer.
摘要翻译：一种在半导体衬底中形成具有改善的透射可靠性的导光层的方法，所述方法包括在所述半导体衬底中形成沟槽，在所述沟槽中形成包覆层和预备导光层，使得只有一个相对侧端部所述预备光导层与所述沟槽的内侧壁接触，并对所述基板进行热处理，以将所述初步导光层改变为所述导光层。

17. 发明申请

US20120314991A1 SEMICONDUCTOR DEVICES HAVING OPTICAL TRANSCEIVER 有权
标题翻译：具有光学收发器的半导体器件
公开(公告)号：US20120314991A1
公开(公告)日：2012-12-13
申请号：US13412210
申请日：2012-03-05
申请人： Pil-Kyu Kang , Dae-Lok Bae , Byung-Lyul Park , Gil-Heyun Choi
发明人： Pil-Kyu Kang , Dae-Lok Bae , Byung-Lyul Park , Gil-Heyun Choi
IPC分类号： G02B6/12 , H01L29/06
CPC分类号： G02B6/124 , G02B6/136 , G02B6/4206 , G02B6/43
摘要： Semiconductor devices having an optical transceiver include a cladding on a substrate, a protrusion vertically extending trough the cladding and materially in continuity with the substrate, and a coupler on the cladding and the protrusion.
摘要翻译：具有光收发器的半导体器件包括在衬底上的包层，垂直延伸穿过覆层并与衬底物理连续的突起，以及在包层和突起上的耦合器。

18. 发明授权

US08319348B2 Metal interconnect of semiconductor device 有权
标题翻译：半导体器件的金属互连
公开(公告)号：US08319348B2
公开(公告)日：2012-11-27
申请号：US12722643
申请日：2010-03-12
申请人： Jongmyeong Lee , Zungsun Choi , Gilheyun Choi , Byung-Lyul Park , Jinho Park , Hye Kyung Jung
发明人： Jongmyeong Lee , Zungsun Choi , Gilheyun Choi , Byung-Lyul Park , Jinho Park , Hye Kyung Jung
IPC分类号： H01L23/48
CPC分类号： H01L23/528 , H01L23/5226 , H01L23/53214 , H01L23/53228 , H01L2924/0002 , H01L2924/00
摘要： Provided are a metal interconnect of a semiconductor device and a method of fabricating the metal interconnect. The metal interconnect includes a metal line having a first end and a second end disposed on an opposite side to the first end, a via electrically connected to the metal line, and a non-active segment extending from the first end and including a void. Tensile stress is decreased to prevent a void from occurring under the via. Accordingly, line breakage due to electromigration is substantially prevented, thus improving electrical characteristics of the device.
摘要翻译：提供半导体器件的金属互连和制造金属互连的方法。金属互连包括金属线，其具有设置在与第一端相对的第一端和第二端，电连接到金属线的通孔和从第一端延伸并且包括空隙的非活性段。减小拉伸应力以防止孔下方发生空隙。因此，基本上防止了电迁移引起的线路断线，从而提高了器件的电气特性。

19. 发明授权

US08278207B2 Methods of manufacturing semiconductor devices 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08278207B2
公开(公告)日：2012-10-02
申请号：US12688557
申请日：2010-01-15
申请人： Jin-Ho Park , Gil-Heyun Choi , Byung-Lyul Park , Jong-Myeong Lee , Zung-Sun Choi , Hye-Kyung Jung
发明人： Jin-Ho Park , Gil-Heyun Choi , Byung-Lyul Park , Jong-Myeong Lee , Zung-Sun Choi , Hye-Kyung Jung
IPC分类号： H01L21/4763
CPC分类号： H01L21/76846 , H01L21/28562 , H01L21/76856 , H01L23/53223 , H01L23/53238 , H01L23/53252 , H01L27/10855 , H01L27/11521 , H01L27/11524 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device can include an insulation layer on that is on a substrate on which a plurality of lower conductive structures are formed, where the insulation layer has an opening. A barrier layer is on a sidewall and a bottom of the opening of the insulation layer, where the barrier layer includes a first barrier layer in which a constituent of a first deoxidizing material is richer than a metal material in the first barrier layer and a second barrier layer in which a metal material in the second barrier layer is richer than a constituent of a second deoxidizing material. An interconnection is in the opening of which the sidewall and the bottom are covered with the barrier layer, the interconnection is electrically connected to the lower conductive structure.
摘要翻译：半导体器件可以包括在其上形成有多个下导电结构的基板上的绝缘层，其中绝缘层具有开口。阻挡层位于绝缘层的开口的侧壁和底部上，其中阻挡层包括第一阻挡层，第一脱氧材料的成分比第一阻挡层中的金属材料更富，第二阻隔层阻挡层，其中第二阻挡层中的金属材料比第二脱氧材料的成分更富。互连在其开口中，侧壁和底部被阻挡层覆盖，互连电连接到下导电结构。

20. 发明申请

US20120039564A1 Photoelectric Integrated Circuit Devices And Methods Of Forming The Same 审中-公开
标题翻译：光电集成电路器件及其形成方法
公开(公告)号：US20120039564A1
公开(公告)日：2012-02-16
申请号：US13191874
申请日：2011-07-27
申请人： Pil-Kyu Kang , GilHeyun Choi , Sukchul Bang , Daelok Bae , Byung-Lyul Park , KwangJin Moon , Dong-Chan Lim , Deok-Young Jung
发明人： Pil-Kyu Kang , GilHeyun Choi , Sukchul Bang , Daelok Bae , Byung-Lyul Park , KwangJin Moon , Dong-Chan Lim , Deok-Young Jung
IPC分类号： G02B6/12
CPC分类号： G02B6/131 , G02B6/132 , G02B6/136 , G02B2006/12061
摘要： A photoelectric integrated circuit device may include a substrate including an electronic device region and an on die optical input/output device region, the substrate having a trench in the on die optical input/output device region; a lower clad layer provided in the trench, the lower clad layer having an upper surface lower than a surface of the substrate; a core provided on the lower clad layer; an insulating pattern provided on the core; an optical detection pattern provided on the insulating pattern, the optical detection pattern having at least a portion provided in the trench; and at least one transistor provided on the substrate of the electronic device region.
摘要翻译：光电集成电路器件可以包括包括电子器件区域和裸片上的光输入/输出器件区域的衬底，所述衬底在管芯光输入/输出器件区域中具有沟槽; 设置在所述沟槽中的下包层，所述下包层具有比所述基板的表面低的上表面; 设置在下包层上的芯; 设置在芯上的绝缘图案; 设置在所述绝缘图案上的光学检测图案，所述光学检测图案具有设置在所述沟槽中的至少一部分; 以及设置在电子器件区域的衬底上的至少一个晶体管。

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