专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明申请

US20210390024A1 AGGREGATE GHASH-BASED MESSAGE AUTHENTICATION CODE (MAC) OVER MULTIPLE CACHELINES WITH INCREMENTAL UPDATES 有权
公开(公告)号：US20210390024A1
公开(公告)日：2021-12-16
申请号：US16902755
申请日：2020-06-16
申请人： Intel Corporation
发明人： David M. Durham , Karanvir S. Grewal , Sergej Deutsch , Michael E. Kounavis
IPC分类号： G06F11/27 , G06F11/07 , G06F11/10 , G06F11/14 , G06F11/30 , G06F12/14 , G06F7/72 , H04L9/32 , H04L9/06 , H04L9/08
摘要： Embodiments are directed to aggregate GHASH-based message authentication code (MAC) over multiple cachelines with incremental updates. An embodiment of a system includes a controller comprising circuitry, the controller to generate an error correction code for a memory line, the memory line comprising a plurality of first data blocks, generate a metadata block corresponding to the memory line, the metadata block comprising the error correction code for the memory line and at least one metadata bit, generate an aggregate GHASH corresponding to a region of memory comprising a cacheline set comprising at least the memory line, encode the first data blocks and the metadata block, encrypt the aggregate GHASH as an aggregate message authentication code (AMAC), provide the encoded first data blocks and the encoded metadata block for storage on a memory module comprising the memory line, and provide the AMAC for storage on a device separate from the memory module.

12. 发明申请

US20200167294A1 System, Apparatus and Method for Secure Monotonic Counter Operations in a Processor 审中-公开
公开(公告)号：US20200167294A1
公开(公告)日：2020-05-28
申请号：US16777956
申请日：2020-01-31
申请人： Intel Corporation
发明人： Prashant Dewan , Siddhartha Chhabra , David M. Durham , Karanvir S. Grewal , Alpa T. Narendra Trivedi
IPC分类号： G06F12/14 , G06F21/62 , G06F21/60 , G06F21/10 , G06F3/06 , G06F21/74
摘要： In one embodiment, an apparatus includes: at least one core to execute instructions, the at least one core formed on a semiconductor die; a first memory formed on the semiconductor die, the first memory comprising a non-volatile random access memory, the first memory to store a first entry to be a monotonic counter, the first entry including a value field and a status field; and a control circuit, wherein the control circuit is to enable access to the first entry if the apparatus is in a secure mode and otherwise prevent the access to the first entry. Other embodiments are described and claimed.

13. 发明申请

US20190102539A1 INSTALLING AND MANIPULATING A SECURE VIRTUAL MACHINE IMAGE THROUGH AN UNTRUSTED HYPERVISOR 审中-公开
公开(公告)号：US20190102539A1
公开(公告)日：2019-04-04
申请号：US15721553
申请日：2017-09-29
申请人： Intel Corporation
发明人： David M. Durham , Karanvir S. Grewal , Sergej Deutsch , Michael Lemay
IPC分类号： G06F21/53 , G06F9/455
CPC分类号： G06F21/53 , G06F9/45554 , G06F9/45558 , G06F21/57 , G06F2009/45562 , G06F2009/4557 , H04L63/062
摘要： Systems, apparatuses and methods may provide for technology that associates a key domain of a plurality of key domains with a customer boot image, receives the customer boot image from the customer, and verifies the integrity of the customer boot image that is to be securely installed at memory locations determined from an untrusted privileged entity (e.g., a virtual machine manager).

14. 发明授权

US10223528B2 Technologies for deterministic code flow integrity protection 有权
公开(公告)号：US10223528B2
公开(公告)日：2019-03-05
申请号：US15276895
申请日：2016-09-27
申请人： Intel Corporation
发明人： Michael E. Kounavis , David M. Durham , Ravi L. Sahita , Karanvir S. Grewal
IPC分类号： G06F21/00 , G06F21/54 , G06F21/56
摘要： Technologies for code flow integrity protection include a static analyzer that identifies a potential gadget in an atomic code path of a protected code. A marker instruction is inserted after the potential gadget with a parameter that corresponds to an address of the marker instruction, a hash evaluator instruction is inserted after an exit point of the atomic code path with a parameter that corresponds to the address of the marker instruction, and a compare evaluator instruction and a hash check instruction are inserted after the hash evaluator instruction. A target computing device executes the protected code and updates a path hash as a function of the parameter of the marker instruction, determines an expected hash value as a function of the parameter of the hash evaluator instruction, and generates an exception if the path hash and the expected hash value do not match. Other embodiments are described and claimed.

15. 发明授权

US09893897B2 Encrypted data inspection in a network environment 有权
公开(公告)号：US09893897B2
公开(公告)日：2018-02-13
申请号：US14929476
申请日：2015-11-02
申请人： Intel Corporation
发明人： Xiaoning Li , Karanvir S. Grewal , Geoffrey H. Cooper , John R. Guzik
IPC分类号： H04L9/32 , G06F11/30 , G06F21/00 , H04L29/06
CPC分类号： H04L9/3273 , G06F11/30 , G06F21/00 , H04L63/0227 , H04L63/0281 , H04L63/0428 , H04L63/0464 , H04L63/166 , H04L2209/24
摘要： Technologies are provided in example embodiments for analyzing an encrypted network flow. The technologies include monitoring the encrypted network flow between a first node and a second node, the network flow initiated from the first node; duplicating the encrypted network flow to form a copy of the encrypted network flow; decrypting the copy of the encrypted network flow using a shared secret, the shared secret associated with the first node and the second node; and scanning the network flow copy for targeted data.

16. 发明申请

US20170286672A1 System, Apparatus And Method For Filtering Memory Access Logging In A Processor 审中-公开
公开(公告)号：US20170286672A1
公开(公告)日：2017-10-05
申请号：US15088318
申请日：2016-04-01
申请人： Intel Corporation
发明人： Salmin Sultana , David M. Durham , Michael Lemay , Karanvir S. Grewal , Ravi L. Sahita
IPC分类号： G06F21/55 , G06F12/10 , G06F12/14 , G06F9/455 , G06F17/30
CPC分类号： G06F21/552 , G06F12/1009 , G06F12/145 , G06F17/30424 , G06F21/55 , G06F21/56 , G06F2009/45583 , G06F2009/45591 , G06F2212/1052 , G06F2212/65 , G06F2221/034
摘要： In one embodiment, a processor comprises: a first storage including a plurality of entries to store an address of a portion of a memory in which information has been modified; a second storage to store an identifier of a process for which information is to be stored into the first storage; and a first logic to identify a modification to a first portion of the memory and store a first address of the first portion of the memory in a first entry of the first storage, responsive to a determination that a current identifier of a current process corresponds to the identifier stored in the second storage. Other embodiments are described and claimed.

17. 发明授权

US09769123B2 Mitigating unauthorized access to data traffic 有权
公开(公告)号：US09769123B2
公开(公告)日：2017-09-19
申请号：US13863168
申请日：2013-04-15
申请人： Intel Corporation
发明人： Karanvir S. Grewal , Ravi L. Sahita , David Durham
IPC分类号： G06F21/60 , H04L29/06 , G06F21/52 , G06F21/53 , G06F21/78 , G06F21/85
CPC分类号： H04L63/0428 , G06F21/52 , G06F21/53 , G06F21/606 , G06F21/78 , G06F21/85
摘要： One particular example implementation of an apparatus for mitigating unauthorized access to data traffic, comprises: an operating system stack to allocate unprotected kernel transfer buffers; a hypervisor to allocate protected memory data buffers, where data is to be stored in the protected memory data buffers before being copied to the unprotected kernel transfer buffers; and an encoder module to encrypt the data stored in the protected memory data buffers, where the unprotected kernel transfer buffers receive a copy the encrypted data.

18. 发明申请

US20160173288A1 ENCRYPTED DATA INSPECTION IN A NETWORK ENVIRONMENT 有权
标题翻译：网络环境中的加密数据检查
公开(公告)号：US20160173288A1
公开(公告)日：2016-06-16
申请号：US14929476
申请日：2015-11-02
申请人： Intel Corporation
发明人： Xiaoning Li , Karanvir S. Grewal , Geoffrey H. Cooper , John R. Guzik
IPC分类号： H04L9/32 , H04L29/06
CPC分类号： H04L9/3273 , G06F11/30 , G06F21/00 , H04L63/0227 , H04L63/0281 , H04L63/0428 , H04L63/0464 , H04L63/166 , H04L2209/24
摘要： Technologies are provided in example embodiments for analyzing an encrypted network flow. The technologies include monitoring the encrypted network flow between a first node and a second node, the network flow initiated from the first node; duplicating the encrypted network flow to form a copy of the encrypted network flow; decrypting the copy of the encrypted network flow using a shared secret, the shared secret associated with the first node and the second node; and scanning the network flow copy for targeted data.
摘要翻译：在用于分析加密网络流的示例实施例中提供了技术。所述技术包括监视第一节点和第二节点之间的加密网络流，所述网络流从所述第一节点发起; 复制加密网络流以形成加密网络流的副本; 使用共享密钥解密加密网络流的副本，与第一节点和第二节点相关联的共享秘密; 并扫描目标数据的网络流拷贝。

19. 发明申请

US20150188702A1 EFFICIENT KEY DERIVATION FOR END-TO-END NETWORK SECURITY WITH TRAFFIC VISIBILITY 有权
标题翻译：有效交付可视性的端到端网络安全的有效关键
公开(公告)号：US20150188702A1
公开(公告)日：2015-07-02
申请号：US14557125
申请日：2014-12-01
申请人： Intel Corporation
发明人： Long Men , Jesse Walker , Karanvir S. Grewal
IPC分类号： H04L9/08 , H04L29/06
CPC分类号： H04L9/0866 , H04L9/0631 , H04L63/0428 , H04L63/06 , H04L2209/125
摘要： Both end-to-end security and traffic visibility may be achieved by a system using a controller that derives a cryptographic key that is different for each client based on a derivation key and a client identifier that is conveyed in each data packet. The controller distributes the derivation key to information technology monitoring devices and a server to provide traffic visibility. For large key sizes, the key may be derived using a derivation formula as follows: client_key_MSB=AES 128(base_key_1, client_ID), (1) client_key_LSB=AES 128(base_key_2, client_ID+pad), and (2) client_key=client_key_MSB∥client_key_LSB, where (1) and (2) are executed in parallel. The client key and a client identifier may be used so that end-to-end security may be achieved.
摘要翻译：端到端安全性和流量可见性可以由使用控制器的系统来实现，所述控制器基于在每个数据分组中传送的导出密钥和客户端标识符来导出每个客户端不同的密码密钥。控制器将派生密钥分发到信息技术监控设备和服务器，以提供流量可视性。对于较大的密钥大小，可以使用以下推导公式来导出密钥：client_key_MSB = AES 128（base_key_1，client_ID），（1）client_key_LSB = AES 128（base_key_2，client_ID + pad）和（2）client_key =client_key_MSB‖ client_key_LSB，其中（1）和（2）并行执行。可以使用客户端密钥和客户端标识符，以便可以实现端到端的安全性。

20. 发明公开

US20240333501A1 MULTI-KEY MEMORY ENCRYPTION PROVIDING EFFICIENT ISOLATION FOR MULTITHREADED PROCESSES 审中-公开
公开(公告)号：US20240333501A1
公开(公告)日：2024-10-03
申请号：US18194553
申请日：2023-03-31
申请人： Intel Corporation
发明人： David M. Durham , Michael LeMay , Salmin Sultana , Karanvir S. Grewal , Sergej Deutsch
IPC分类号： H04L9/14 , G06F21/60 , G06F21/62 , G06F21/78
CPC分类号： H04L9/14 , G06F21/602 , G06F21/6209 , G06F21/6218 , G06F21/78
摘要： In a technique of hardware thread isolation, a processor comprises a first core including a first hardware thread register. The core is to select a first key identifier stored in the first hardware thread register in response to receiving a first memory access request associated with a first hardware thread of a process. Memory controller circuitry coupled to the first core is to obtain a first encryption key associated with the first key identifier. The first key identifier may be selected from the first hardware thread register based, at least in part, on a first portion of a pointer of the first memory access request. The first key identifier selected from the first hardware thread register is to be appended to a physical address translated from a linear address at least partially included in the pointer.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式