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11. 发明申请

US20050079673A1 Method of manufacturing a semiconductor memory device 失效
标题翻译：制造半导体存储器件的方法
公开(公告)号：US20050079673A1
公开(公告)日：2005-04-14
申请号：US10954835
申请日：2004-09-29
申请人： Jung-woo Seo , Tae-hyuk Ahn , Jeong-sic Jeon
发明人： Jung-woo Seo , Tae-hyuk Ahn , Jeong-sic Jeon
IPC分类号： H01L21/28 , H01L21/336 , H01L21/768 , H01L21/8242 , H01L27/108
CPC分类号： H01L21/76895 , H01L21/76802 , H01L21/76831 , H01L27/10814 , H01L27/10855 , H01L27/10885 , H01L27/10888
摘要： Manufacturing a semiconductor memory by first forming a first insulating layer covering a conductive pad. Next forming and pattering a bit line conductive layer and a second insulating layer to expose a part of the first insulating layer. A third insulating layer covering the exposed surfaces of the first insulating layer is formed. Exposing an upper surface of the bit line conductive layer pattern and an upper surface of the third insulating layer. Removing part of the third insulating layer and first insulating layer to expose the conductive pad. Forming a spacer on the side walls of the bit line conductive layer pattern and the first insulating layer. An insulating layer pattern and a second spacer layer are respectively formed on the bit line conductive layer pattern and on a side wall of the first spacer and a conductive plug, which is in contact with the conductive pad is formed.
摘要翻译：通过首先形成覆盖导电垫的第一绝缘层来制造半导体存储器。接下来形成和图案位线导电层和第二绝缘层以暴露第一绝缘层的一部分。形成覆盖第一绝缘层的暴露表面的第三绝缘层。露出位线导电层图案的上表面和第三绝缘层的上表面。去除第三绝缘层和第一绝缘层的一部分以暴露导电焊盘。在位线导电层图案和第一绝缘层的侧壁上形成间隔物。分别在位线导电层图案和第一间隔物的侧壁上形成绝缘层图案和第二间隔层，并且形成与导电焊盘接触的导电插塞。

12. 发明授权

US07312121B2 Method of manufacturing a semiconductor memory device 失效
标题翻译：制造半导体存储器件的方法
公开(公告)号：US07312121B2
公开(公告)日：2007-12-25
申请号：US11155174
申请日：2005-06-16
申请人： Jung-woo Seo , Tae-hyuk Ahn , Jeong-sic Jeon
发明人： Jung-woo Seo , Tae-hyuk Ahn , Jeong-sic Jeon
IPC分类号： H01L21/8242
CPC分类号： H01L21/76895 , H01L21/76802 , H01L21/76831 , H01L27/10814 , H01L27/10855 , H01L27/10885 , H01L27/10888
摘要： Manufacturing a semiconductor memory by first forming a first insulating layer covering a conductive pad. Next forming and pattering a bit line conductive layer and a second insulating layer to expose a part of the first insulating layer. A third insulating layer covering the exposed surfaces of the first insulating layer is formed. Exposing an upper surface of the bit line conductive layer pattern and an upper surface of the third insulating layer. Removing part of the third insulating layer and first insulating layer to expose the conductive pad. Forming a spacer on the side walls of the bit line conductive layer pattern and the first insulating layer. An insulating layer pattern and a second spacer layer are respectively formed on the bit line conductive layer pattern and on a side wall of the first spacer and a conductive plug, which is in contact with the conductive pad is formed.
摘要翻译：通过首先形成覆盖导电垫的第一绝缘层来制造半导体存储器。接下来形成和图案位线导电层和第二绝缘层以暴露第一绝缘层的一部分。形成覆盖第一绝缘层的暴露表面的第三绝缘层。露出位线导电层图案的上表面和第三绝缘层的上表面。去除第三绝缘层和第一绝缘层的一部分以暴露导电焊盘。在位线导电层图案和第一绝缘层的侧壁上形成间隔物。分别在位线导电层图案和第一间隔物的侧壁上形成绝缘层图案和第二间隔层，并且形成与导电焊盘接触的导电插塞。

13. 发明申请

US20060186479A1 Semiconductor memory device having local etch stopper and method of manufacturing the same 有权
标题翻译：具有局部蚀刻停止器的半导体存储器件及其制造方法
公开(公告)号：US20060186479A1
公开(公告)日：2006-08-24
申请号：US11354175
申请日：2006-02-15
申请人： Jung-woo Seo , Jong-seo Hong , Tae-hyuk Ahn , Jeong-sic Jeon , Jun-sik Hong , Young-sun Cho
发明人： Jung-woo Seo , Jong-seo Hong , Tae-hyuk Ahn , Jeong-sic Jeon , Jun-sik Hong , Young-sun Cho
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L21/76895 , H01L21/76837 , H01L21/76885 , H01L21/76897 , H01L27/10855 , H01L27/10888 , H01L27/10894
摘要： A semiconductor memory device includes a semiconductor substrate in which a cell region and a core and peripheral region are defined. The device further comprises isolation layers formed in the semiconductor substrate to define active regions, a first gate electrode structure formed in the cell region and a second gate electrode structure formed in the core and peripheral region. Source and drain regions formed in the active regions on respective sides of each of the gate electrode structures and self-aligned contact pads are formed in the cell region in contact with the source and drain regions. An insulating interlayer is formed on the semiconductor substrate between the self-aligned contact pads, and etch stoppers are formed on the insulating interlayer between the self-aligned contact pads in the cell region.
摘要翻译：半导体存储器件包括其中限定了单元区域和芯和外围区域的半导体衬底。该器件还包括形成在半导体衬底中以限定有源区的隔离层，形成在单元区域中的第一栅电极结构和形成在芯和外围区中的第二栅电极结构。形成在每个栅电极结构和自对准接触焊盘的相应侧上的有源区中的源区和漏区形成在与源区和漏区接触的单元区域中。在自对准接触焊盘之间的半导体衬底上形成绝缘中间层，并且在电池区域中的自对准接触焊盘之间的绝缘中间层上形成蚀刻阻挡层。

14. 发明申请

US20050233505A1 Method of manufacturing a semiconductor memory device 失效
公开(公告)号：US20050233505A1
公开(公告)日：2005-10-20
申请号：US11155174
申请日：2005-06-16
申请人： Jung-woo Seo , Tae-hyuk Ahn , Jeong-sic Jeon
发明人： Jung-woo Seo , Tae-hyuk Ahn , Jeong-sic Jeon
IPC分类号： H01L21/28 , H01L21/336 , H01L21/768 , H01L21/8242 , H01L27/108
CPC分类号： H01L21/76895 , H01L21/76802 , H01L21/76831 , H01L27/10814 , H01L27/10855 , H01L27/10885 , H01L27/10888
摘要： Manufacturing a semiconductor memory by first forming a first insulating layer covering a conductive pad. Next forming and pattering a bit line conductive layer and a second insulating layer to expose a part of the first insulating layer. A third insulating layer covering the exposed surfaces of the first insulating layer is formed. Exposing an upper surface of the bit line conductive layer pattern and an upper surface of the third insulating layer. Removing part of the third insulating layer and first insulating layer to expose the conductive pad. Forming a spacer on the side walls of the bit line conductive layer pattern and the first insulating layer. An insulating layer pattern and a second spacer layer are respectively formed on the bit line conductive layer pattern and on a side wall of the first spacer and a conductive plug, which is in contact with the conductive pad is formed.

15. 发明授权

US07462899B2 Semiconductor memory device having local etch stopper and method of manufacturing the same 有权
标题翻译：具有局部蚀刻停止器的半导体存储器件及其制造方法
公开(公告)号：US07462899B2
公开(公告)日：2008-12-09
申请号：US11354175
申请日：2006-02-15
申请人： Jung-woo Seo , Jong-seo Hong , Tae-hyuk Ahn , Jeong-sic Jeon , Jun-sik Hong , Young-sun Cho
发明人： Jung-woo Seo , Jong-seo Hong , Tae-hyuk Ahn , Jeong-sic Jeon , Jun-sik Hong , Young-sun Cho
IPC分类号： H01L27/108
CPC分类号： H01L21/76895 , H01L21/76837 , H01L21/76885 , H01L21/76897 , H01L27/10855 , H01L27/10888 , H01L27/10894
摘要： A semiconductor memory device includes a semiconductor substrate in which a cell region and a core and peripheral region are defined. The device further comprises isolation layers formed in the semiconductor substrate to define active regions, a first gate electrode structure formed in the cell region and a second gate electrode structure formed in the core and peripheral region. Source and drain regions formed in the active regions on respective sides of each of the gate electrode structures and self-aligned contact pads are formed in the cell region in contact with the source and drain regions. An insulating interlayer is formed on the semiconductor substrate between the self-aligned contact pads, and etch stoppers are formed on the insulating interlayer between the self-aligned contact pads in the cell region.
摘要翻译：半导体存储器件包括其中限定了单元区域和芯和外围区域的半导体衬底。该器件还包括形成在半导体衬底中以限定有源区的隔离层，形成在单元区域中的第一栅电极结构和形成在芯和外围区中的第二栅电极结构。形成在每个栅电极结构和自对准接触焊盘的相应侧上的有源区中的源区和漏区形成在与源区和漏区接触的单元区域中。在自对准接触焊盘之间的半导体衬底上形成绝缘中间层，并且在电池区域中的自对准接触焊盘之间的绝缘中间层上形成蚀刻阻挡层。

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