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11. 发明授权

US09207750B2 Apparatus and method for reducing leakage power of a circuit 有权
标题翻译：减少电路漏电功率的装置和方法
公开(公告)号：US09207750B2
公开(公告)日：2015-12-08
申请号：US13715624
申请日：2012-12-14
申请人： Intel Corporation
发明人： Gururaj K. Shamanna , Stefan Rusu , Phani Kumar Kandula , Sankalan Prasad , Mandar R. Ranade , Narayanan Natarajan , Tessil Thomas
IPC分类号： G06F1/32
CPC分类号： G06F1/28 , G05F1/625 , G06F1/3275 , G06F1/3296 , Y02D10/14 , Y02D10/172
摘要： Described is a processor comprising: a plurality of transistors operable to provide dynamically adjustable transistor size, the plurality of transistors coupled at one end to a first power supply and coupled at another end to a second power supply; a circuit coupled to the second power supply, the second power supply to provide power to the circuit; and a power control unit (PCU) to monitor the level of the first power supply, and to dynamically adjust the transistor size of the plurality of transistors so that the second power supply is adjusted to keep the circuit operational.
摘要翻译：描述了一种处理器，包括：多个晶体管，其可操作以提供动态可调节的晶体管尺寸，所述多个晶体管的一端耦合到第一电源并在另一端耦合到第二电源; 耦合到所述第二电源的电路，所述第二电源向所述电路提供电力; 以及功率控制单元（PCU），用于监测第一电源的电平，并且动态地调整多个晶体管的晶体管尺寸，使得调节第二电源以保持电路的可操作性。

12. 发明申请

US20150188548A1 INTEGRATED CLOCK DIFFERENTIAL BUFFERING 有权
标题翻译：集成时钟差分缓冲
公开(公告)号：US20150188548A1
公开(公告)日：2015-07-02
申请号：US14513024
申请日：2014-10-13
申请人： Intel Corporation
发明人： Choupin Huang , Huang K. Boddu , Stefan Rusu , Nicholas B. Peterson
IPC分类号： H03L7/07
CPC分类号： H03L7/07 , G06F1/06 , G06F1/10 , G06F3/167 , H03L7/08 , H03L7/0891 , H03L2207/06
摘要： Integrated clock differential buffering. A first phase locked loop (PLL) circuit having a first clocking ratio is coupled to receive an input differential clock signal. The first PLL circuit generates a first reference clock signal. A second PLL circuit having a second clocking ratio is coupled to receive the input differential clock signal. The second PLL circuit to generate a second reference clock signal. A first set of clock signal output buffers are coupled to receive the first reference clock signal and to provide a first differential reference clock signal corresponding to the first reference clock signal. A second set of clock signal output buffers is coupled to receive the second reference clock signal and to provide a second differential reference clock signal corresponding to the second reference clock signal. The first PLL circuit, the second PLL circuit, the first set of output buffers and the second set of output buffers reside within an integrated circuit package also having a die to receive at least the first differential reference clock signal.
摘要翻译：集成时钟差分缓冲。具有第一时钟比率的第一锁相环（PLL）电路被耦合以接收输入差分时钟信号。第一PLL电路产生第一参考时钟信号。具有第二时钟比的第二PLL电路被耦合以接收输入差分时钟信号。第二个PLL电路产生第二个参考时钟信号。耦合第一组时钟信号输出缓冲器以接收第一参考时钟信号并提供对应于第一参考时钟信号的第一差分参考时钟信号。第二组时钟信号输出缓冲器被耦合以接收第二参考时钟信号并提供对应于第二参考时钟信号的第二差分参考时钟信号。第一PLL电路，第二PLL电路，第一组输出缓冲器和第二组输出缓冲器驻留在还具有至少接收第一差分参考时钟信号的管芯的集成电路封装中。

13. 发明授权

US10923463B2 Method and machine-readable medium for configuring processors with base dies having landing slots 有权
公开(公告)号：US10923463B2
公开(公告)日：2021-02-16
申请号：US16590057
申请日：2019-10-01
申请人： Intel Corporation
发明人： Stefan Rusu
IPC分类号： G06F15/76 , H01L25/18 , H01L25/065 , H01L23/48 , H01L23/544 , H01L25/00 , G06F12/1045
摘要： A method is described for configuring a custom server processor including a base die and related components. For example, one embodiment includes: providing a secure website to a user for configuring a custom server processor, the secure website including a graphical user interface (GUI); providing a first graphical element from which a user is to select a base die and an associated package; providing a second graphical element including a plurality of building block options selectable by the user to populate landing slots in the selected base die; providing a third graphical element including a visual representation of a user configuration that includes one or more building blocks selected by the user in the second graphical element and arranged on the base die selected by the user in the first graphical element; and performing a verification of the user configuration.

14. 发明授权

US10269417B2 Apparatus for adaptive write assist for memory 有权
公开(公告)号：US10269417B2
公开(公告)日：2019-04-23
申请号：US15115464
申请日：2014-03-05
申请人： Intel Corporation
发明人： Gururaj K. Shamanna , Stefan Rusu , Eric A. Karl , Zheng Guo
IPC分类号： G11C11/412 , G11C11/419 , G11C7/22 , G11C7/04 , G11C29/02
摘要： Described is an apparatus which comprises: a memory; a first power supply node to receive a first power supply; a second power supply node coupled to the memory to provide the memory with second power supply; a circuit coupled to the first and second power supply nodes, the circuit operable to dynamically modulate droop in the second power supply by adaptively adjusting signal characteristics of a write assist pulse.

15. 发明授权

US10013045B2 Apparatus, method, and system for adaptive compensation of reverse temperature dependence 有权
公开(公告)号：US10013045B2
公开(公告)日：2018-07-03
申请号：US15144332
申请日：2016-05-02
申请人： INTEL CORPORATION
发明人： Stefan Rusu
IPC分类号： G06F1/32 , G06F11/30 , G06F1/20
CPC分类号： G06F1/324 , G06F1/206 , G06F1/3206 , G06F1/3234 , Y02D10/126 , Y02D10/16
摘要： Described herein are an apparatus, method, and system for adaptive compensation for reverse temperature dependence in a processor. The apparatus comprises: a first sensor to determine operating temperature of a processor; a second sensor to determine behavior of the processor; and a control unit to determine a frequency of a clock signal for the processor and a power supply level for the processor according to the determined operating temperature and behavior of the processor, wherein the control unit to increase the power supply level from an existing power supply level, and/or reduce frequency of the clock signal from an existing frequency of the clock signal when the operating temperature is in a region of reverse temperature dependence (RTD).

16. 发明授权

US09805790B2 Memory cell with retention using resistive memory 有权
公开(公告)号：US09805790B2
公开(公告)日：2017-10-31
申请号：US15025229
申请日：2013-12-05
申请人： Intel Corporation
发明人： Nathaniel J. August , Pulkit Jain , Stefan Rusu , Fatih Hamzaoglu , Rangharajan Venkatesan , Muhammad Khellah , Charles Augustine , Carlos Tokunaga , James W. Tschanz , Yih Wang
IPC分类号： G11C13/00 , G11C14/00 , G11C11/16
CPC分类号： G11C13/0061 , G11C11/161 , G11C11/1657 , G11C11/1659 , G11C11/1675 , G11C11/1693 , G11C13/0011 , G11C13/0014 , G11C14/0081 , G11C14/009
摘要： Described is an apparatus including memory cell with retention using resistive memory. The apparatus comprises: memory element including a first inverting device cross-coupled to a second inverting device; a restore circuit having at least one resistive memory element, the restore circuit coupled to an output of the first inverting device; a third inverting device coupled to the output of the first inverting device; a fourth inverting device coupled to an output of the third inverting device; and a save circuit having at least one resistive memory element, the save circuit coupled to an output of the third inverting device.

17. 发明申请

US20170019112A1 APPARATUS AND METHOD FOR CLOCK SYNCHRONIZATION FOR INTER-DIE SYNCHRONIZED DATA TRANSFER 审中-公开
标题翻译：用于内部同步数据传输的时钟同步的装置和方法
公开(公告)号：US20170019112A1
公开(公告)日：2017-01-19
申请号：US15214364
申请日：2016-07-19
申请人： Intel Corporation
发明人： Shenggao Li , Stefan Rusu
IPC分类号： H03L7/07 , G06F13/40 , H03L7/081 , G06F1/12 , H01L23/48 , H03L7/091
CPC分类号： H03L7/00 , G06F1/12 , G06F13/4027 , H01L23/481 , H01L25/0657 , H01L2224/48137 , H01L2224/49175 , H01L2225/06541 , H03L7/07 , H03L7/0814 , H03L7/091 , H04L7/0012 , H04L7/0025 , Y02D10/14 , Y02D10/151
摘要： Described is an apparatus for clock synchronization. The apparatus comprises a pair of interconnects; a first die including a first phase interpolator having an output coupled to one of the interconnects; and a second die, wherein the pair of interconnects is to couple the first die to the second die.
摘要翻译：描述了一种用于时钟同步的装置。该装置包括一对互连; 包括具有耦合到所述互连中的一个的输出的第一相位内插器的第一管芯; 以及第二管芯，其中所述一对互连件将所述第一管芯连接到所述第二管芯。

18. 发明授权

US09335803B2 Calculating a dynamically changeable maximum operating voltage value for a processor based on a different polynomial equation using a set of coefficient values and a number of current active cores 有权
标题翻译：使用一系列系数值和当前活动核心数量，基于不同的多项式方程计算处理器的动态可变最大工作电压值
公开(公告)号：US09335803B2
公开(公告)日：2016-05-10
申请号：US13768633
申请日：2013-02-15
申请人： Intel Corporation
发明人： Zhiguo Wang , David J. Ayers , Srikanth Balasubramanian , Sukirti Gupta , Stefan Rusu , Stephen M. Ramey
IPC分类号： G06F1/00 , G06F1/26 , G06F1/32 , G06F1/20 , G06F9/50
CPC分类号： G06F1/26 , G06F1/206 , G06F1/32 , G06F1/3206 , G06F1/3296 , G06F9/50 , G06F9/5094 , Y02D10/172
摘要： In an embodiment, a processor includes voltage calculation logic to calculate a plurality of maximum operating voltage values each associated with a number of active cores of the plurality of cores, based at least in part on a plurality of coefficient values. In this way, the processor can operate at different maximum operating voltages dependent on the number of active cores. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括电压计算逻辑以至少部分地基于多个系数值来计算与多个核的多个活动核心数量相关联的多个最大工作电压值。以这种方式，处理器可以根据活动核心的数量在不同的最大工作电压下工作。描述和要求保护其他实施例。

19. 发明授权

US11031288B2 Passive components in vias in a stacked integrated circuit package 有权
公开(公告)号：US11031288B2
公开(公告)日：2021-06-08
申请号：US16252420
申请日：2019-01-18
申请人： Intel Corporation
发明人： Sujit Sharan , Ravindranath Mahajan , Stefan Rusu , Donald S. Gardner
IPC分类号： H01L21/78 , H01L23/48 , H01L23/522 , H01L25/16 , H01L49/02 , H01L23/538
摘要： Integrated passive components in a stacked integrated circuit package are described. In one embodiment an apparatus has a substrate, a first die coupled to the substrate over the substrate, the first die including a power supply circuit coupled to the substrate to receive power, a second die having a processing core and coupled to the first die over the first die, the first die being coupled to the power supply circuit to power the processing core, a via through the first die, and a passive device formed in the via of the first die and coupled to the power supply circuit.

20. 发明授权

US10560104B2 Clock synchronization apparatus and method 有权
公开(公告)号：US10560104B2
公开(公告)日：2020-02-11
申请号：US16184794
申请日：2018-11-08
申请人： Intel Corporation
发明人： Shenggao Li , Stefan Rusu
IPC分类号： H03L7/00 , H03L7/091 , H01L23/48 , G06F13/40 , H04L7/00 , H03L7/081 , H01L25/065 , G06F1/12
摘要： Described is an apparatus for clock synchronization. The apparatus comprises a pair of interconnects; a first die including a first phase interpolator having an output coupled to one of the interconnects; and a second die, wherein the pair of interconnects is to couple the first die to the second die.

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