专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US4427516A Apparatus and method for plasma-assisted etching of wafers 失效
标题翻译：用于等离子体辅助蚀刻晶片的装置和方法
公开(公告)号：US4427516A
公开(公告)日：1984-01-24
申请号：US471901
申请日：1983-03-04
申请人： Hyman J. Levinstein , Frederick Vratny
发明人： Hyman J. Levinstein , Frederick Vratny
IPC分类号： H01J37/32 , H01J37/34 , H01L21/311 , C23C15/00
CPC分类号： H01J37/32559 , H01J37/34 , H01L21/31116 , H01J2237/20 , Y10S156/914 , Y10S156/917
摘要： In a plasma-assisted etching apparatus and method designed to pattern silicon dioxide in a plasma derived from a mixture of trifluoromethane and ammonia, surfaces in the reaction chamber are coated with a layer of silicon. Contamination of wafers during the etching process is thereby substantially reduced. In practice, this leads to a significant increase in the yield of acceptable chips per wafer.
摘要翻译：在等离子体辅助蚀刻装置和设计用于在三氟甲烷和氨的混合物中产生的等离子体中排列二氧化硅的方法，反应室中的表面涂覆有一层硅。因此，在蚀刻过程中晶片的污染因此显着降低。在实践中，这导致每个晶片可接受的芯片的产量显着增加。

12. 发明授权

US4253029A Mask structure for x-ray lithography 失效
标题翻译： X射线光刻的掩模结构
公开(公告)号：US4253029A
公开(公告)日：1981-02-24
申请号：US41730
申请日：1979-05-23
申请人： Martin P. Lepselter , Hyman J. Levinstein , Dan Maydan
发明人： Martin P. Lepselter , Hyman J. Levinstein , Dan Maydan
IPC分类号： G03F1/22 , H01L21/30 , B01J17/00 , G02B5/00 , G21F5/04
CPC分类号： G03F1/22 , Y10S430/167
摘要： A mask substrate for use in an x-ray lithographic system comprises a boron nitride member (32, FIG. 2) coated with a polyimide layer (20) whose thickness is approximately the same as that of the boron nitride member. The substrate is mechanically strong and both optically and x-ray transparent. Mask patterns formed on the substrate are characterized by low distortion and a low defect density.
摘要翻译：用于x射线光刻系统的掩模基板包括涂覆有厚度与氮化硼构件的厚度大致相同的聚酰亚胺层（20）的氮化硼构件（32，图2）。基材机械性强，光学和X射线透明。形成在基板上的掩模图案的特征在于低失真和低缺陷密度。

13. 发明授权

US4208241A Device fabrication by plasma etching 失效
标题翻译：通过等离子体蚀刻的器件制造
公开(公告)号：US4208241A
公开(公告)日：1980-06-17
申请号：US929549
申请日：1978-07-31
申请人： William R. Harshbarger , Hyman J. Levinstein , Cyril J. Mogab , Roy A. Porter
发明人： William R. Harshbarger , Hyman J. Levinstein , Cyril J. Mogab , Roy A. Porter
IPC分类号： H01L21/302 , C23F4/00 , H01L21/3065 , H01L21/3213 , H01L21/306
CPC分类号： H01L21/32136 , C23F4/00 , H01L21/3065 , H01L21/32137
摘要： High density fine-line integrated structure fabrication is expedited by use of plasma etching systems which assure straight vertical walls (absence of undercutting). Critical to the sytems is choice of appropriate plasma chemistry. Appropriate systems are characterized by inclusion of recombination centers, as well as active etchant species. Recombination centers which effectively terminate etchant species lifetime in the immediate vicinity of resist walls afford means for controlling etching anisotropy. Use is foreseen in large scale integrated circuitry (LSI) and is expected to be of particular interest for extremely fine design rules, i.e., in Very Large Scale Integrated circuitry.
摘要翻译：通过使用等离子体蚀刻系统加速了高密度细线集成结构的制造，确保了直立的垂直壁（没有底切）。系统的关键是选择合适的等离子体化学。合适的系统的特征在于包含重组中心以及活性蚀刻剂物质。在抗蚀剂壁附近有效地终止蚀刻剂物质寿命的重组中心提供控制蚀刻各向异性的手段。预期在大规模集成电路（LSI）中的使用，并且预期对于非常精细的设计规则，即在超大规模集成电路中是特别有意义的。

14. 发明授权

US4555842A Method of fabricating VLSI CMOS devices having complementary threshold voltages 失效
标题翻译：制造具有互补阈值电压的VLSI CMOS器件的方法
公开(公告)号：US4555842A
公开(公告)日：1985-12-03
申请号：US591274
申请日：1984-03-19
申请人： Hyman J. Levinstein , Sheila Vaidya
发明人： Hyman J. Levinstein , Sheila Vaidya
IPC分类号： H01L29/78 , H01L21/28 , H01L21/8234 , H01L21/8238 , H01L27/088 , H01L27/092 , H01L29/49 , H01L21/265 , H01L21/22
CPC分类号： H01L21/823842 , H01L29/4916 , H01L29/4933 , H01L27/0928 , Y10S148/082
摘要： For optimal performance, the threshold voltages V.sub.TP and V.sub.TN of the p- and n-channel transistors in a CMOS device should be the respective complements of each other. In polysilicon-gate devices, this can be achieved by adjusting the corresponding gate-metal work function utilizing p.sup.+ and n.sup.+ polysilicon for the respective gates of the p- and n-channel transistors. However, when a refractory metal silicide-over-polysilicon gate structure is employed in a VLSI CMOS device in which the gates of a pair of adjacent complementary transistors are connected together, an anomalously large negative V.sub.TP is measured.The invention is a unique process sequence that achieves substantially complementary p- and n-channel transistor thresholds in a high-speed VLSI CMOS device that includes silicide-over-polysilicon gates.
摘要翻译：为了获得最佳性能，CMOS器件中p沟道晶体管和n沟道晶体管的阈值电压VTP和VTN应相互补充。在多晶硅栅极器件中，这可以通过利用p +和n +多晶硅来调整p型和n型多晶硅的相应栅极金属功函数来实现，用于p沟道晶体管和n沟道晶体管的各个栅极。然而，当在一对相邻互补晶体管的栅极连接在一起的VLSI CMOS器件中采用难熔金属硅化物多晶硅栅极结构时，测量异常大的负VTP。本发明是在包括硅化物多晶硅栅极的高速VLSI CMOS器件中实现基本上互补的p沟道和n沟道晶体管阈值的独特工艺序列。

15. 发明授权

US4472237A Reactive ion etching of tantalum and silicon 失效
标题翻译：钽和硅的反应离子蚀刻
公开(公告)号：US4472237A
公开(公告)日：1984-09-18
申请号：US449441
申请日：1982-12-13
申请人： Jean S. Deslauriers , Hyman J. Levinstein
发明人： Jean S. Deslauriers , Hyman J. Levinstein
IPC分类号： H01L21/28 , H01L21/3213 , H01L21/308
CPC分类号： H01L21/32137 , H01L21/28061 , Y10S148/10 , Y10S148/105
摘要： A method for fabricating a device which includes a tantalum silicide structure, and which is essentially free of conductive etch residues, is disclosed. The method includes the steps of depositing tantalum and silicon onto a substrate, patterning the tantalum and silicon, and then sintering the patterned tantalum and silicon to form a patterned layer of tantalum silicide.
摘要翻译：公开了一种制造包括硅化钽结构并且基本上不含导电蚀刻残留物的器件的方法。该方法包括以下步骤：将钽和硅沉积到衬底上，图案化钽和硅，然后烧结图案化的钽和硅以形成图案化的硅化钽层。

16. 发明授权

US4343677A Method for patterning films using reactive ion etching thereof 失效
标题翻译：使用其反应离子蚀刻来图案化膜的方法
公开(公告)号：US4343677A
公开(公告)日：1982-08-10
申请号：US246690
申请日：1981-03-23
申请人： Eliezer Kinsbron , Hyman J. Levinstein , William E. Willenbrock, Jr.
发明人： Eliezer Kinsbron , Hyman J. Levinstein , William E. Willenbrock, Jr.
IPC分类号： H01L21/302 , C23F4/00 , H01L21/02 , H01L21/3065 , H01L21/311 , H01L21/3213 , B44C1/22 , C03C15/00 , C23F1/02 , H01L21/306
CPC分类号： H01L21/02071 , C23F4/00 , H01L21/31133 , Y10S438/963
摘要： In the patterning of an organic layer on a VLSI wafer by means of reactive oxygen (or other) ion anisotropic etching, build-ups of oxides (or other compounds) on the sidewalls of apertures formed in the organic layer are removed prior to etching the material, typically aluminum, of the VLSI wafer located at the bottom of these apertures, using the patterned organic layer as an etch mask.
摘要翻译：在通过活性氧（或其他）离子各向异性蚀刻在VLSI晶片上图案化有机层时，在蚀刻之前除去在有机层中形成的孔的侧壁上的氧化物（或其它化合物）的积聚使用图案化的有机层作为蚀刻掩模的位于这些孔的底部的VLSI晶片的材料（通常为铝）。

17. 发明授权

US4341818A Method for producing silicon dioxide/polycrystalline silicon interfaces 失效
标题翻译：二氧化硅/多晶硅界面的制造方法
公开(公告)号：US4341818A
公开(公告)日：1982-07-27
申请号：US159865
申请日：1980-06-16
申请人： Arthur C. Adams , Hyman J. Levinstein
发明人： Arthur C. Adams , Hyman J. Levinstein
IPC分类号： C04B41/52 , C04B41/89 , H01L21/316 , H01L21/3205 , B05D5/12
CPC分类号： C04B41/009 , C04B41/52 , C04B41/89 , H01L21/02238 , H01L21/02255 , H01L21/31662 , H01L21/32055
摘要： The efficient production of sequential layers of silicon dioxide and polycrystalline silicon is possible using a specific set of reaction steps. This set of reaction steps includes the oxidation of silicon at low oxygen pressure and at temperatures of the magnitude of 900 degrees C., followed by the deposition of polycrystalline silicon at substantially the same temperature utilizing a dichloride silane chemical vapor deposition (CVD) process.
摘要翻译：使用特定的一组反应步骤可以有效地生产二氧化硅和多晶硅的连续层。这组反应步骤包括在低氧压力和900℃的温度下氧化硅，随后使用二氯硅烷化学气相沉积（CVD）工艺在基本上相同的温度下沉积多晶硅。

18. 发明授权

US06217655B1 Stand-off pad for supporting a wafer on a substrate support chuck 失效
标题翻译：用于在基板支撑卡盘上支撑晶片的支撑垫
公开(公告)号：US06217655B1
公开(公告)日：2001-04-17
申请号：US08791941
申请日：1997-01-31
申请人： Ananda H. Kumar , Shamouil Shamouilian , Hyman J. Levinstein , Vijay Parkhe
发明人： Ananda H. Kumar , Shamouil Shamouilian , Hyman J. Levinstein , Vijay Parkhe
IPC分类号： B05C1300
CPC分类号： H01L21/6833 , H01L21/6875
摘要： A stand-off pad, and method of fabricating the same, for supporting a workpiece in a spaced apart relation to a workpiece support chuck. More specifically, the wafer stand-off pad is fabricated of a polymeric material, such as polyimide, which is disposed upon the support surface of the chuck. The stand-off pad maintains a wafer, or other workpiece, in a spaced apart relation to the support surface of the chuck. The distance between the underside surface of the wafer and the chuck is defined by the thickness of the stand-off pad. This distance should be larger than the expected diameter of contaminant particles that may lie on the surface of the chuck. In this manner, the contaminant particles do not adhere to the underside of the wafer during processing and the magnitude of the chucking voltage is maintained between the workpiece and the chuck.
摘要翻译：支撑垫及其制造方法，用于以与工件支撑卡盘间隔开的关系支撑工件。更具体地说，晶片支座由诸如聚酰亚胺的聚合材料制成，其设置在卡盘的支撑表面上。支座将保持晶片或其它工件与卡盘的支撑表面间隔开。晶片的下表面和卡盘之间的距离由支座的厚度限定。该距离应大于可能位于卡盘表面上的污染物颗粒的预期直径。以这种方式，污染物颗粒在处理期间不粘附到晶片的下侧，并且夹持电压的幅度保持在工件和卡盘之间。

19. 发明授权

US5986875A Puncture resistant electrostatic chuck 失效
标题翻译：耐刺穿静电卡盘
公开(公告)号：US5986875A
公开(公告)日：1999-11-16
申请号：US015802
申请日：1998-01-29
申请人： Arik Donde , Hyman J. Levinstein , Robert W. Wu , Andreas Hegedus , Edwin C. Weldon , Shamouil Shamouilian , Jon T. Clinton , Surinder S. Bedi
发明人： Arik Donde , Hyman J. Levinstein , Robert W. Wu , Andreas Hegedus , Edwin C. Weldon , Shamouil Shamouilian , Jon T. Clinton , Surinder S. Bedi
IPC分类号： B23Q3/15 , H01L21/683 , H02N13/00
CPC分类号： H01L21/6831 , H01L21/6833 , H02N13/00 , Y10T279/23
摘要： A puncture resistant electrostatic chuck (20) is described. The chuck (20) comprises at least one electrode (25); and a composite insulator (30) covering the electrode. The composite insulator comprises a matrix material having a conformal holding surface (50) capable of conforming to the substrate (35) under application of an electrostatic force generated by the electrode to reduce leakage of heat transfer fluid held between the substrate and the holding surface. A hard puncture resistant layer, such a layer of fibers or an aromatic polyamide layer, is positioned below the holding surface (50) and is sufficiently hard to increase the puncture resistance of the composite insulator.
摘要翻译：描述了一种抗穿刺静电卡盘（20）。卡盘（20）包括至少一个电极（25）; 和覆盖电极的复合绝缘体（30）。复合绝缘体包括具有能够在施加电极产生的静电力的同时保持基板（35）的共形保持表面（50）的基体材料，以减少保持在基板和保持表面之间的传热流体的泄漏。这种纤维层或芳香族聚酰胺层的耐穿刺层位于保持面（50）的下方，并且足够难以提高复合绝缘子的抗穿刺性。

20. 发明授权

US5745331A Electrostatic chuck with conformal insulator film 失效
标题翻译：带保形绝缘膜的静电吸盘
公开(公告)号：US5745331A
公开(公告)日：1998-04-28
申请号：US381786
申请日：1995-01-31
申请人： Shamouil Shamouilian , Sasson Somekh , Hyman J. Levinstein , Manoocher Birang , Semyon Sherstinsky , John F. Cameron
发明人： Shamouil Shamouilian , Sasson Somekh , Hyman J. Levinstein , Manoocher Birang , Semyon Sherstinsky , John F. Cameron
IPC分类号： B23Q3/15 , H01L21/683 , H02N13/00
CPC分类号： H01L21/6831 , H01L21/6833 , H02N13/00
摘要： An electrostatic chuck (20) for holding a substrate (75) comprises (i) a base (80) having an upper surface (95) with grooves (85) therein, the grooves (85) sized and distributed for holding coolant for cooling a substrate (75), and (ii) a substantially continuous insulator film (45) conformal to the grooves (85) on upper surface (95) of the base (80). The base (80) can be electrically conductive and capable of serving as the electrode (50) of the chuck (20), or the electrode (50) can be embedded in the insulator film (45). The insulator film (45) has a dielectric breakdown strength sufficiently high that when a substrate (75) placed on the chuck (20) and electrically biased with respect to the electrode (50), electrostatic charge accumulates in the substrate (75) and in the electrode (50) forming an electrostatic force that attracts and holds the substrate (75) to the chuck (20). Preferably the chuck (20) is fabricated using a pressure forming process, and more preferably using a pressure differential process.
摘要翻译：用于保持基板（75）的静电卡盘（20）包括（i）具有在其中具有凹槽（85）的上表面（95）的基部（80），所述凹槽（85）的尺寸和分布以保持用于冷却的冷却剂衬底（75），和（ii）与基座（80）的上表面（95）上的凹槽（85）共形的基本上连续的绝缘膜（45）。基座（80）可以是导电的并且能够用作卡盘（20）的电极（50），或者电极（50）可以嵌入绝缘膜（45）中。绝缘体膜（45）具有足够高的绝缘击穿强度，当放置在卡盘（20）上并相对于电极（50）电偏置的基板（75）时，静电电荷积聚在基板（75）中所述电极（50）形成吸引并保持所述基板（75）到所述卡盘（20）的静电力。优选地，使用压力成形方法制造卡盘（20），更优选使用压差法。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式