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11. 发明授权

US07791125B2 Semiconductor devices having dielectric layers and methods of forming the same 有权
标题翻译：具有电介质层的半导体器件及其形成方法
公开(公告)号：US07791125B2
公开(公告)日：2010-09-07
申请号：US11881562
申请日：2007-07-27
申请人： Hoon-Sang Choi , Jong-Cheol Lee , Ki-Vin Im , Jae-Hyun Yeo , Eun-Ae Chung , Sang-Yeol Kang
发明人： Hoon-Sang Choi , Jong-Cheol Lee , Ki-Vin Im , Jae-Hyun Yeo , Eun-Ae Chung , Sang-Yeol Kang
IPC分类号： H01L27/108
CPC分类号： H01L21/02194 , H01L21/0228 , H01L21/02318 , H01L21/31604 , H01L21/31641 , H01L21/31645 , H01L28/91
摘要： A method of forming a semiconductor device includes loading a semiconductor substrate into a reaction chamber, and providing metal organic precursors including hafnium and zirconium into the reaction chamber to form hafnium-zirconium oxide (HfxZr1-xO; 0
摘要翻译：一种形成半导体器件的方法包括将半导体衬底加载到反应室中，并向反应室中提供包括铪和锆的金属有机前体以形成铪锆氧化物（Hf x Zr 1-x O; 0

12. 发明申请

US20080258271A1 Multi-dielectric films for semiconductor devices and methods of fabricating multi-dielectric films 有权
标题翻译：用于半导体器件的多电介质膜和制造多介电膜的方法
公开(公告)号：US20080258271A1
公开(公告)日：2008-10-23
申请号：US12079757
申请日：2008-03-28
申请人： Jong-Cheol Lee , Sang-Yeol Kang , Ki-Vin Lim , Hoon-Sang Choi , Eun-Ae Chung
发明人： Jong-Cheol Lee , Sang-Yeol Kang , Ki-Vin Lim , Hoon-Sang Choi , Eun-Ae Chung
IPC分类号： H01L29/51 , H01L21/31
CPC分类号： H01L21/022 , H01L21/02178 , H01L21/02192 , H01L21/02194 , H01L21/31641 , H01L21/31645 , H01L27/10852 , H01L28/56 , H01L29/511
摘要： A multi-dielectric film including at least one first dielectric film that is a composite film made of zirconium-hafnium-oxide and at least one second dielectric film that is a metal oxide film made of amorphous metal oxide. Adjacent ones of the dielectric films are made of different materials.
摘要翻译：一种多介电膜，其包括至少一个作为由锆 - 铪氧化物构成的复合膜的第一电介质膜和至少一个作为由非晶态金属氧化物构成的金属氧化物膜的第二电介质膜。相邻的电介质膜由不同的材料制成。

13. 发明授权

US09484219B2 Methods of fabricating memory devices using wet etching and dry etching 有权
标题翻译：使用湿蚀刻和干蚀刻制造存储器件的方法
公开(公告)号：US09484219B2
公开(公告)日：2016-11-01
申请号：US14826845
申请日：2015-08-14
申请人： Young-Geun Park , Wook-Yeol Yi , Sang-Yeol Kang , Dong-Chan Kim , Chang-Mu An , Bong-Hyun Kim , Han-Jin Lim
发明人： Young-Geun Park , Wook-Yeol Yi , Sang-Yeol Kang , Dong-Chan Kim , Chang-Mu An , Bong-Hyun Kim , Han-Jin Lim
IPC分类号： H01L21/8242 , H01L21/311 , H01L27/108
CPC分类号： H01L21/31144 , H01L21/31111 , H01L21/31116 , H01L27/10852 , H01L27/10855
摘要： A method of fabricating semiconductor devices may include forming a mold structure on a lower layer, the mold structure including an etch stop layer doped at a first impurity concentration, a lower mold layer doped at a second impurity concentration, and an undoped upper mold layer. The method may include forming a trench exposing the lower layer in the mold structure using dry etching, extending a width of the trench in the etch stop layer using wet etching, and forming a first conductive pattern in the extended width trench, wherein an etch rate of the etch stop layer with respect to the dry etching may be smaller than an etch rate of the lower mold layer with respect to the dry etching, and an etch rate of the etch stop layer with respect to the wet etching may be proportional to the first impurity concentration.
摘要翻译：制造半导体器件的方法可以包括在下层上形成模具结构，所述模具结构包括以第一杂质浓度掺杂的蚀刻停止层，以第二杂质浓度掺杂的下模层和未掺杂的上模层。该方法可以包括使用干蚀刻形成在模具结构中暴露下层的沟槽，使用湿蚀刻在蚀刻停止层中延伸沟槽的宽度，以及在扩展宽度沟槽中形成第一导电图案，其中蚀刻速率相对于干蚀刻的蚀刻停止层的蚀刻速度可以小于相对于干蚀刻的下模层的蚀刻速率，并且蚀刻停止层相对于湿蚀刻的蚀刻速率可以与第一杂质浓度。

14. 发明申请

US20130244445A1 Method of Fabricating Semiconductor Device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20130244445A1
公开(公告)日：2013-09-19
申请号：US13775595
申请日：2013-02-25
申请人： Min-Young Park , Youn-Soo Kim , Sang-Yeol Kang , Cha-Young Yoo , Jae-Soon Lim , Jae-Hyoung Choi
发明人： Min-Young Park , Youn-Soo Kim , Sang-Yeol Kang , Cha-Young Yoo , Jae-Soon Lim , Jae-Hyoung Choi
IPC分类号： H01L21/02
CPC分类号： H01L21/02104 , C23C16/045 , C23C16/405 , C23C16/45527 , H01L21/28282 , H01L28/40
摘要： Methods of fabricating a semiconductor device include forming a deposited film on a semiconductor substrate in a process chamber by repeatedly forming unit layers on the semiconductor substrate. The unit layer is formed by forming a preliminary unit layer on the semiconductor substrate by supplying a process material including a precursor material and film-control material into the process chamber, purging the process chamber, forming a unit layer from the preliminary unit layer, and again purging the process chamber. The precursor material includes a central atom and a ligand bonded to the central atom, and the film-control material includes a hydride of the ligand.
摘要翻译：制造半导体器件的方法包括通过在半导体衬底上重复形成单位层，在处理室中的半导体衬底上形成沉积膜。单元层通过在半导体基板上形成预备单元层而形成，该方法是将包括前体材料和薄膜控制材料的处理材料供应到处理室中，从处理室中清除处理室，从预备单元层形成单位层，以及再次清洗处理室。前体材料包括中心原子和与中心原子键合的配体，膜控制材料包括配体的氢化物。

15. 发明申请

US20110102968A1 MULTILAYER STRUCTURE, CAPACITOR INCLUDING THE MULTILAYER STRUCTURE AND METHOD OF FORMING THE SAME 审中-公开
标题翻译：多层结构，包括多层结构的电容器及其形成方法
公开(公告)号：US20110102968A1
公开(公告)日：2011-05-05
申请号：US12838296
申请日：2010-07-16
申请人： Jae-Hyoung CHOI , Youn-Soo Kim , Jung-Hyeon Kim , Wan-Don Kim , Jae-Soon Lim , Sang-Yeol Kang
发明人： Jae-Hyoung CHOI , Youn-Soo Kim , Jung-Hyeon Kim , Wan-Don Kim , Jae-Soon Lim , Sang-Yeol Kang
IPC分类号： H01G4/008 , B32B9/04 , B05D5/12 , C23C14/34
CPC分类号： H01L23/5223 , H01L23/53261 , H01L28/56 , H01L28/91 , H01L29/40114 , H01L29/40117 , H01L29/518 , H01L2924/0002 , H01L2924/00
摘要： In a multilayer structure and a method of forming the same, a conductive layer including a metal nitride and a dielectric layer positioned on a surface of the conductive layer and having a high dielectric constant. The metal nitride comprises one of niobium, vanadium and compositions thereof. Thus, the EOT and leakage current of the multilayer structure may be sufficiently improved.
摘要翻译：在多层结构及其形成方法中，包括位于导电层表面上并具有高介电常数的金属氮化物和电介质层的导电层。金属氮化物包括铌，钒及其组合物中的一种。因此，可以充分提高多层结构的EOT和漏电流。

16. 发明申请

US20070148933A1 Nonvolatile memory device and method of fabricating the same 审中-公开
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20070148933A1
公开(公告)日：2007-06-28
申请号：US11512658
申请日：2006-08-30
申请人： Jin-Il Lee , Choong-Man Lee , Sung-Lae Cho , Ran-Ju Jung , Sang-Yeol Kang , Young-Lim Park
发明人： Jin-Il Lee , Choong-Man Lee , Sung-Lae Cho , Ran-Ju Jung , Sang-Yeol Kang , Young-Lim Park
IPC分类号： H01L21/20
CPC分类号： H01L21/32051 , H01L21/28562 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/16
摘要： A method of fabricating a phase-change random-access memory (RAM) device includes forming a chalcogenide material on a substrate. A bottom contact is formed under the chalcogenide material, the bottom contact comprising TiAlN. Forming the bottom contact includes performing an atomic layer deposition (ALD) process, the ALD process including introducing an NH3 source gas into a chamber in which the ALD process is being carried out, a flow amount of the NH3 gas being such that the resulting bottom contact has a chlorine content of less than 1 at %. The bottom contact can include TiAlN having a crystallinity in terms of full-width half-maximum (FWHM) of less than about 0.65 degree.
摘要翻译：制造相变随机存取存储器（RAM）器件的方法包括在衬底上形成硫族化物材料。在硫族化物材料下形成底部接触，底部接触包含TiAlN。形成底部接触包括执行原子层沉积（ALD）工艺，ALD工艺包括将NH 3源气体引入到其中进行ALD工艺的室中，流动量为 NH 3气体使得所得底部接触物的氯含量小于1原子％。底部接触可以包括具有小于约0.65度的全宽度半最大值（FWHM）的结晶度的TiAlN。

17. 发明申请

US20110151639A1 SEMICONDUCTOR DEVICE, METHOD OF FABRICATING THE SAME, SEMICONDUCTOR MODULE, ELECTRONIC CIRCUIT BOARD, AND ELECTRONIC SYSTEM INCLUDING THE DEVICE 审中-公开
标题翻译：半导体器件，其制造方法，半导体器件，电子电路板和包括器件的电子系统
公开(公告)号：US20110151639A1
公开(公告)日：2011-06-23
申请号：US12855191
申请日：2010-08-12
申请人： Jae-Soon Lim , Youn-Soo Kim , Jae-Hyoung Choi , Sang-Yeol Kang , Suk-Jin Chung
发明人： Jae-Soon Lim , Youn-Soo Kim , Jae-Hyoung Choi , Sang-Yeol Kang , Suk-Jin Chung
IPC分类号： H01L21/02
CPC分类号： H01L28/40 , C01G23/047 , C01G25/02 , C01P2002/72 , C01P2004/03 , C01P2006/40
摘要： Provided are a semiconductor device, a method of fabricating the same, and a semiconductor module, an electronic circuit board, and an electronic system including the device. The semiconductor device includes a lower electrode, a rutile state lower vanadium dioxide layer on the lower electrode, a rutile state titanium oxide on the lower vanadium dioxide layer, and an upper electrode on the titanium oxide layer.
摘要翻译：提供一种半导体器件及其制造方法，以及半导体模块，电子电路板和包括该器件的电子系统。半导体器件包括下电极，下电极上的金红石状态较低二氧化钒层，下二氧化钒层上的金红石型氧化钛，以及氧化钛层上的上电极。

18. 发明授权

US07939872B2 Multi-dielectric films for semiconductor devices and methods of fabricating multi-dielectric films 有权
标题翻译：用于半导体器件的多电介质膜和制造多介电膜的方法
公开(公告)号：US07939872B2
公开(公告)日：2011-05-10
申请号：US12079757
申请日：2008-03-28
申请人： Jong-Cheol Lee , Sang-Yeol Kang , Ki-Vin Lim , Hoon-Sang Choi , Eun-Ae Chung
发明人： Jong-Cheol Lee , Sang-Yeol Kang , Ki-Vin Lim , Hoon-Sang Choi , Eun-Ae Chung
IPC分类号： H01L29/51
CPC分类号： H01L21/022 , H01L21/02178 , H01L21/02192 , H01L21/02194 , H01L21/31641 , H01L21/31645 , H01L27/10852 , H01L28/56 , H01L29/511
摘要： A multi-dielectric film including at least one first dielectric film that is a composite film made of zirconium-hafnium-oxide and at least one second dielectric film that is a metal oxide film made of amorphous metal oxide. Adjacent ones of the dielectric films are made of different materials.
摘要翻译：一种多介电膜，其包括至少一个作为由锆 - 铪氧化物构成的复合膜的第一电介质膜和至少一个作为由非晶态金属氧化物构成的金属氧化物膜的第二电介质膜。相邻的电介质膜由不同的材料制成。

19. 发明申请

US20100134950A1 CAPACITOR 有权
标题翻译：电容器
公开(公告)号：US20100134950A1
公开(公告)日：2010-06-03
申请号：US12628598
申请日：2009-12-01
申请人： Hoon-Sang Choi , Ki-Vin Im , Se-Hoon Oh , Sang-Yeol Kang , Cha-Young Yoo
发明人： Hoon-Sang Choi , Ki-Vin Im , Se-Hoon Oh , Sang-Yeol Kang , Cha-Young Yoo
IPC分类号： H01G4/30 , H01L29/92
CPC分类号： H01G4/33 , H01G4/01 , H01L27/10817 , H01L27/10852 , H01L28/91
摘要： A capacitor includes a substrate, a plurality of first storage electrodes, a plurality of second storage electrodes, a first supporting layer pattern, a dielectric layer and a plate electrode. A plurality of contact pads is formed I the substrate. The first storage electrodes are arranged along lines parallel with a first direction and electrically connected to the contact pads, respectively. The second storage electrodes are respectively stacked on the first storage electrodes. The first supporting layer pattern extends in a direction parallel with the first direction between adjacent second storage electrodes and makes contact with the adjacent second storage electrodes to support the second storage electrodes. The dielectric layer is formed on the first and second storage electrodes. The plate electrode is formed on the dielectric layer.
摘要翻译：电容器包括基板，多个第一存储电极，多个第二存储电极，第一支撑层图案，电介质层和平板电极。在基板上形成多个接触焊盘。第一存储电极沿着与第一方向平行的线分别布置并且电连接到接触垫。第二存储电极分别堆叠在第一存储电极上。第一支撑层图案在与相邻的第二存储电极之间的第一方向平行的方向上延伸，并与相邻的第二存储电极接触以支撑第二存储电极。介电层形成在第一和第二存储电极上。在电介质层上形成平板电极。

20. 发明申请

US20080087930A1 Capicitor Using Binary Metal Electrode, Semiconductor Device Having The Capacitor And Method of Fabricating The Same 审中-公开
标题翻译：使用二元金属电极的电容器，具有电容器的半导体器件及其制造方法
公开(公告)号：US20080087930A1
公开(公告)日：2008-04-17
申请号：US11733943
申请日：2007-04-11
申请人： Jong-Cheol Lee , Ki-Vin Im , Hoon-Sang Choi , Eun-Ae Chung , Sang-Yeol Kang
发明人： Jong-Cheol Lee , Ki-Vin Im , Hoon-Sang Choi , Eun-Ae Chung , Sang-Yeol Kang
IPC分类号： H01L27/108 , H01G4/008 , H01L21/20
CPC分类号： H01L28/60 , H01G4/005 , H01G4/10 , H01G4/33 , H01L27/10852
摘要： A capacitor includes a first electrode having a conductive pattern and an anti-oxidation pattern contacting the conductive pattern and a second electrode overlapping the first electrode. The capacitor further includes a capacitor dielectric layer disposed between the first and second electrodes, and having a blanket dielectric layer and a partial dielectric layer. The blanket dielectric layer is disposed between the first and second electrodes, and the partial dielectric layer is disposed between the blanket dielectric layer and the anti-oxidation pattern.
摘要翻译：电容器包括具有导电图案的第一电极和与导电图案接触的抗氧化图案和与第一电极重叠的第二电极。电容器还包括设置在第一和第二电极之间的电容器介质层，并且具有覆盖介电层和部分电介质层。覆盖介电层设置在第一和第二电极之间，并且部分电介质层设置在覆盖电介质层和抗氧化图案之间。

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