专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明申请

US20120112288A1 ISOLATION STRUCTURE, METHOD FOR MANUFACTURING THE SAME, AND SEMICONDUCTOR DEVICE HAVING THE STRUCTURE 有权
标题翻译：隔离结构，其制造方法和具有结构的半导体器件
公开(公告)号：US20120112288A1
公开(公告)日：2012-05-10
申请号：US13142378
申请日：2011-03-02
申请人： Zhijiong Luo , Haizhou Yin , Huilong Zhu , Huicai Zhong
发明人： Zhijiong Luo , Haizhou Yin , Huilong Zhu , Huicai Zhong
IPC分类号： H01L27/04 , H01L21/762
CPC分类号： H01L21/76232 , H01L21/823481
摘要： The present invention provides an isolation structure for a semiconductor substrate and a method for manufacturing the same, as well as a semiconductor device having the structure. The present invention relates to the field of semiconductor manufacture. The isolation structure comprises: a trench embedded in a semiconductor substrate; an oxide layer covering the bottom and sidewalls of the trench, and isolation material in the trench and on the oxide layer, wherein a portion of the oxide layer on an upper portion of the sidewalls of the trench comprises lanthanum-rich oxide. By the trench isolation structure according to the present invention, metal lanthanum in the lanthanum-rich oxide can diffuse into corners of the oxide layer of the gate stack, thus alleviating the impact of the narrow channel effect and making the threshold voltage adjustable.
摘要翻译：本发明提供一种用于半导体衬底的隔离结构及其制造方法，以及具有该结构的半导体器件。本发明涉及半导体制造领域。隔离结构包括：嵌入在半导体衬底中的沟槽; 覆盖沟槽的底部和侧壁的氧化物层，以及沟槽和氧化物层上的隔离材料，其中沟槽侧壁上部的氧化物层的一部分包括富镧氧化物。通过根据本发明的沟槽隔离结构，富镧氧化物中的金属镧可以扩散到栅极堆叠的氧化物层的角部，从而减轻窄沟道效应的影响并使阈值电压可调。

12. 发明授权

US09048286B2 Substrate for integrated circuit and method for forming the same 有权
标题翻译：集成电路基板及其形成方法
公开(公告)号：US09048286B2
公开(公告)日：2015-06-02
申请号：US13159351
申请日：2011-06-13
申请人： Huicai Zhong , Qingqing Liang , Haizhou Yin , Zhijiong Luo
发明人： Huicai Zhong , Qingqing Liang , Haizhou Yin , Zhijiong Luo
IPC分类号： H01L21/76 , H01L21/762
CPC分类号： H01L21/76232 , H01L21/7624 , H01L21/76283
摘要： The present invention relates to substrates for ICs and method for forming the same. The method comprises the steps of: forming a hard mask layer on the bulk silicon material; etching the hard mask layer and the bulk silicon material to form a first part for shallow trench isolation of at least one trench; forming a dielectric film on the sidewall of the at least one trench; further etching the bulk silicon material to deepen the at least one trench so as to form a second part of the at least one trench; completely oxidizing or nitridizing parts of the bulk silicon material which are between the second parts of the trenches, and parts of the bulk silicon material which are between the second parts of the trenches and side surfaces of the bulk silicon substrate; filling dielectric materials in the first and second parts of the at least one trench; and removing the hard mask layer.
摘要翻译：本发明涉及IC的基板及其制造方法。该方法包括以下步骤：在体硅材料上形成硬掩模层; 蚀刻硬掩模层和体硅材料以形成用于至少一个沟槽的浅沟槽隔离的第一部分; 在所述至少一个沟槽的侧壁上形成电介质膜; 进一步蚀刻体硅材料以加深所述至少一个沟槽，以便形成所述至少一个沟槽的第二部分; 在沟槽的第二部分之间的体硅材料的部分和沟槽的第二部分和体硅衬底的侧表面之间的体硅材料的部分完全氧化或氮化; 在所述至少一个沟槽的第一和第二部分中填充介电材料; 并除去硬掩模层。

13. 发明申请

US20120132923A1 SUBSTRATE FOR INTEGRATED CIRCUIT AND METHOD FOR FORMING THE SAME 有权
标题翻译：用于集成电路的基板及其形成方法
公开(公告)号：US20120132923A1
公开(公告)日：2012-05-31
申请号：US13159351
申请日：2011-06-13
申请人： Huicai Zhong , Qingqing Liang , Haizhou Yin , Zhijiong Luo
发明人： Huicai Zhong , Qingqing Liang , Haizhou Yin , Zhijiong Luo
IPC分类号： H01L29/161 , H01L29/20 , H01L21/76
CPC分类号： H01L21/76232 , H01L21/7624 , H01L21/76283
摘要： The present invention relates to substrates for ICs and method for forming the same. The method comprises the steps of: forming a hard mask layer on the bulk silicon material; etching the hard mask layer and the bulk silicon material to form a first part for shallow trench isolation of at least one trench; forming a dielectric film on the sidewall of the at least one trench; further etching the bulk silicon material to deepen the at least one trench so as to form a second part of the at least one trench; completely oxidizing or nitridizing parts of the bulk silicon material which are between the second parts of the trenches, and parts of the bulk silicon material which are between the second parts of the trenches and side surfaces of the bulk silicon substrate; filling dielectric materials in the first and second parts of the at least one trench; and removing the hard mask layer.
摘要翻译：本发明涉及IC的基板及其制造方法。该方法包括以下步骤：在体硅材料上形成硬掩模层; 蚀刻硬掩模层和体硅材料以形成用于至少一个沟槽的浅沟槽隔离的第一部分; 在所述至少一个沟槽的侧壁上形成电介质膜; 进一步蚀刻体硅材料以加深所述至少一个沟槽，以便形成所述至少一个沟槽的第二部分; 在沟槽的第二部分之间的体硅材料的部分和沟槽的第二部分和体硅衬底的侧表面之间的体硅材料的部分完全氧化或氮化; 在所述至少一个沟槽的第一和第二部分中填充介电材料; 并除去硬掩模层。

14. 发明申请

US20120193798A1 SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件结构及其制造方法
公开(公告)号：US20120193798A1
公开(公告)日：2012-08-02
申请号：US13129321
申请日：2011-02-26
申请人： Huicai Zhong , Qingqing Liang , Zhijiong Luo , Huilong Zhu
发明人： Huicai Zhong , Qingqing Liang , Zhijiong Luo , Huilong Zhu
IPC分类号： H01L23/48 , H01L23/482 , H01L21/768
CPC分类号： H01L23/53276 , H01L21/76807 , H01L21/76843 , H01L21/76846 , H01L21/76847 , H01L21/76877 , H01L2221/1094 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to a semiconductor device structure and a method for manufacturing the same; the structure comprises: a semiconductor substrate on which a device structure is formed thereon; an interlayer dielectric layer formed on the device structure, wherein a trench is formed in the interlayer dielectric layer, the trench comprises an incorporated via trench and a conductive wiring trench, and the conductive wiring trench is positioned on the via trench; and a conductive layer filled in the trench, wherein the conductive layer is electrically connected with the device structure; wherein the conductive layer comprises a conductive material and a nanotube/wire layer surrounded by the conductive material. Wherein, the conductive layer comprises a conductive material and a nanotube/wire layer surrounded by the conductive material. The conductive layer of the structure has better thermal conductivity, conductivity and high anti-electromigration capability, thus is able to effectively prevent metal ions from diffusing outwards.
摘要翻译：半导体器件结构及其制造方法技术领域本发明涉及半导体器件结构及其制造方法。该结构包括：其上形成有器件结构的半导体衬底; 在所述器件结构上形成的层间电介质层，其中在所述层间介质层中形成沟槽，所述沟槽包括并入的通孔沟槽和导电布线沟槽，并且所述导电布线沟槽位于所述通孔沟槽上; 以及填充在所述沟槽中的导电层，其中所述导电层与所述器件结构电连接; 其中所述导电层包括由所述导电材料包围的导电材料和纳米管/线层。其中，导电层包括由导电材料包围的导电材料和纳米管/线层。该结构的导电层具有较好的导热性，导电性和较高的抗电迁移能力，能有效防止金属离子向外扩散。

15. 发明授权

US08269307B2 Shallow trench isolation structure and method for forming the same 有权
标题翻译：浅沟隔离结构及其形成方法
公开(公告)号：US08269307B2
公开(公告)日：2012-09-18
申请号：US13119004
申请日：2011-01-27
申请人： Huicai Zhong , Haizhou Yin , Qingqing Liang , Huilong Zhu
发明人： Huicai Zhong , Haizhou Yin , Qingqing Liang , Huilong Zhu
IPC分类号： H01L29/15
CPC分类号： H01L29/7846 , H01L21/76224
摘要： The invention provides a STI structure and a method for manufacturing the same. The STI includes a semiconductor substrate; a first trench formed on the upper surface of the semiconductor substrate and filled with an epitaxial layer, wherein the upper surface of the epitaxial layer is higher than that of the semiconductor substrate; and a second trench formed on the epitaxial layer and filled with a first dielectric layer, wherein the upper surface of the first dielectric layer is flush with that of the epitaxial layer, and the width of the second trench is smaller than that of the first trench. The invention reduces the influences of divots on performance of the semiconductor device.
摘要翻译：本发明提供一种STI结构及其制造方法。 STI包括半导体衬底; 形成在所述半导体衬底的上表面上并填充有外延层的第一沟槽，其中所述外延层的上表面高于所述半导体衬底的所述外表面; 以及形成在所述外延层上并且填充有第一介电层的第二沟槽，其中所述第一电介质层的上表面与所述外延层的上表面齐平，并且所述第二沟槽的宽度小于所述第一沟槽的宽度。本发明减少了对于半导体器件性能的影响。

16. 发明申请

US20120187496A1 SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME 有权
标题翻译：半导体器件及其形成方法
公开(公告)号：US20120187496A1
公开(公告)日：2012-07-26
申请号：US13266555
申请日：2011-04-19
申请人： Huicai Zhong , Qingqing Liang , Haizhou Yin , Huilong Zhu
发明人： Huicai Zhong , Qingqing Liang , Haizhou Yin , Huilong Zhu
IPC分类号： H01L27/088 , H01L21/302
CPC分类号： H01L29/66636 , H01L21/76224 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L29/165 , H01L29/517 , H01L29/66545 , H01L29/78 , H01L29/7848
摘要： A method for forming a semiconductor device comprises: forming at least one gate stack structure and an interlayer material layer between the gate stack structures on a semiconductor substrate; defining isolation regions and removing a portion of the interlayer material layer and a portion of the semiconductor substrate which has a certain height in the regions, so as to form trenches; removing portions of the semiconductor substrate which carry the gate stack structures, in the regions; and filling the trenches with an insulating material. A semiconductor device is also provided. The area of the isolation regions may be reduced.
摘要翻译：一种用于形成半导体器件的方法包括：在半导体衬底上的栅堆叠结构之间形成至少一个栅叠层结构和层间材料层; 限定隔离区域并去除在该区域中具有一定高度的层间材料层和半导体衬底的一部分，以形成沟槽; 在所述区域中移除携带所述栅堆叠结构的所述半导体衬底的部分; 并用绝缘材料填充沟槽。还提供了半导体器件。可以减小隔离区域的面积。

17. 发明授权

US08637935B2 Semiconductor device including embedded isolation regions and method for forming the same 有权
标题翻译：包括嵌入式隔离区的半导体器件及其形成方法
公开(公告)号：US08637935B2
公开(公告)日：2014-01-28
申请号：US13266555
申请日：2011-04-19
申请人： Huicai Zhong , Qingqing Liang , Haizhou Yin , Huilong Zhu
发明人： Huicai Zhong , Qingqing Liang , Haizhou Yin , Huilong Zhu
IPC分类号： H01L29/76 , H01L21/8238
CPC分类号： H01L29/66636 , H01L21/76224 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L29/165 , H01L29/517 , H01L29/66545 , H01L29/78 , H01L29/7848
摘要： A method for forming a semiconductor device comprises: forming at least one gate stack structure and an interlayer material layer between the gate stack structures on a semiconductor substrate; defining isolation regions and removing a portion of the interlayer material layer and a portion of the semiconductor substrate which has a certain height in the regions, so as to form trenches; removing portions of the semiconductor substrate which carry the gate stack structures, in the regions; and filling the trenches with an insulating material. A semiconductor device is also provided. The area of the isolation regions may be reduced.
摘要翻译：一种用于形成半导体器件的方法包括：在半导体衬底上的栅堆叠结构之间形成至少一个栅叠层结构和层间材料层; 限定隔离区域并去除在该区域中具有一定高度的层间材料层和半导体衬底的一部分，以形成沟槽; 在所述区域中移除携带所述栅堆叠结构的所述半导体衬底的部分; 并用绝缘材料填充沟槽。还提供了半导体器件。可以减小隔离区域的面积。

18. 发明申请

US20120126244A1 SHALLOW TRENCH ISOLATION STRUCTURE AND METHOD FOR FORMING THE SAME 有权
标题翻译：浅层分离结构及其形成方法
公开(公告)号：US20120126244A1
公开(公告)日：2012-05-24
申请号：US13119004
申请日：2011-01-27
申请人： Huicai Zhong , Haizhou Yin , Qingqing Liang , Huilong Zhu
发明人： Huicai Zhong , Haizhou Yin , Qingqing Liang , Huilong Zhu
IPC分类号： H01L29/12 , H01L29/16 , H01L21/761 , H01L27/04 , H01L21/762
CPC分类号： H01L29/7846 , H01L21/76224
摘要： The invention provides a STI structure and a method for manufacturing the same. The STI includes a semiconductor substrate; a first trench formed on the upper surface of the semiconductor substrate and filled with an epitaxial layer, wherein the upper surface of the epitaxial layer is higher than that of the semiconductor substrate; and a second trench formed on the epitaxial layer and filled with a first dielectric layer, wherein the upper surface of the first dielectric layer is flush with that of the epitaxial layer, and the width of the second trench is smaller than that of the first trench. The invention reduces the influences of divots on performance of the semiconductor device.
摘要翻译：本发明提供一种STI结构及其制造方法。 STI包括半导体衬底; 形成在所述半导体衬底的上表面上并填充有外延层的第一沟槽，其中所述外延层的上表面高于所述半导体衬底的所述外表面; 以及形成在所述外延层上并且填充有第一介电层的第二沟槽，其中所述第一电介质层的上表面与所述外延层的上表面齐平，并且所述第二沟槽的宽度小于所述第一沟槽的宽度。本发明减少了对于半导体器件性能的影响。

19. 发明授权

US08410609B2 Semiconductor device having carbon nanotube interconnects contact deposited with different orientation and method for manufacturing the same 有权
标题翻译：具有不同取向沉积的碳纳米管互连的半导体器件及其制造方法
公开(公告)号：US08410609B2
公开(公告)日：2013-04-02
申请号：US13129321
申请日：2011-02-26
申请人： Huicai Zhong , Qingqing Liang , Zhijiong Luo , Huilong Zhu
发明人： Huicai Zhong , Qingqing Liang , Zhijiong Luo , Huilong Zhu
IPC分类号： H01L29/40 , H01L21/00
CPC分类号： H01L23/53276 , H01L21/76807 , H01L21/76843 , H01L21/76846 , H01L21/76847 , H01L21/76877 , H01L2221/1094 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to a semiconductor device structure and a method for manufacturing the same; the structure comprises: a semiconductor substrate on which a device structure is formed thereon; an interlayer dielectric layer formed on the device structure, wherein a trench is formed in the interlayer dielectric layer, the trench comprises an incorporated via trench and a conductive wiring trench, and the conductive wiring trench is positioned on the via trench; and a conductive layer filled in the trench, wherein the conductive layer is electrically connected with the device structure; wherein the conductive layer comprises a conductive material and a nanotube/wire layer surrounded by the conductive material. Wherein, the conductive layer comprises a conductive material and a nanotube/wire layer surrounded by the conductive material. The conductive layer of the structure has better thermal conductivity, conductivity and high anti-electromigration capability, thus is able to effectively prevent metal ions from diffusing outwards.
摘要翻译：半导体器件结构及其制造方法技术领域本发明涉及半导体器件结构及其制造方法。该结构包括：其上形成有器件结构的半导体衬底; 在所述器件结构上形成的层间电介质层，其中在所述层间介质层中形成沟槽，所述沟槽包括并入的通孔沟槽和导电布线沟槽，并且所述导电布线沟槽位于所述通孔沟槽上; 以及填充在所述沟槽中的导电层，其中所述导电层与所述器件结构电连接; 其中所述导电层包括由所述导电材料包围的导电材料和纳米管/线层。其中，导电层包括由导电材料包围的导电材料和纳米管/线层。该结构的导电层具有较好的导热性，导电性和较高的抗电迁移能力，能有效防止金属离子向外扩散。

20. 发明授权

US08716095B2 Manufacturing method of gate stack and semiconductor device 有权
标题翻译：栅极堆叠和半导体器件的制造方法
公开(公告)号：US08716095B2
公开(公告)日：2014-05-06
申请号：US12997625
申请日：2010-09-19
申请人： Huicai Zhong , Zhijiong Luo , Qingqing Liang
发明人： Huicai Zhong , Zhijiong Luo , Qingqing Liang
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/513 , H01L21/28176 , H01L29/517 , H01L29/6653 , H01L29/66545 , H01L29/66553 , H01L29/6656 , H01L29/78
摘要： A manufacturing method of a gate stack with sacrificial oxygen-scavenging metal spacers includes: forming a gate stack structure consisting of an interfacial oxide layer, a high-K dielectric layer and a metal gate electrode, on a semiconductor substrate; conformally depositing a metal layer covering the semiconductor substrate and the gate stack structure; and selectively etching the metal layer to remove the portions of the metal layer covering the top surface of the gate stack structure and the semiconductor substrate, so as to only keep the sacrificial oxygen-scavenging metal spacers surrounding the gate stack structure in the outer periphery of the gate stack structure. A semiconductor device manufactured by this process.
摘要翻译：具有牺牲氧清除金属间隔物的栅极堆叠的制造方法包括：在半导体衬底上形成由界面氧化物层，高K电介质层和金属栅电极组成的栅叠层结构; 保形地沉积覆盖半导体衬底和栅极堆叠结构的金属层; 并且选择性地蚀刻金属层以去除覆盖栅极堆叠结构和半导体衬底的顶表面的金属层的部分，以便仅将围绕栅极堆叠结构的牺牲氧清除金属间隔物保持在外部周边门堆栈结构。通过该方法制造的半导体器件。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式