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11. 发明授权

US06368969B1 Chemical-mechanical polishing methods 失效
标题翻译：化学机械抛光方法
公开(公告)号：US06368969B1
公开(公告)日：2002-04-09
申请号：US09607350
申请日：2000-06-30
申请人： Laertis Economikos , Fen Fen Jamin
发明人： Laertis Economikos , Fen Fen Jamin
IPC分类号： H01L21302
CPC分类号： H01L21/3212
摘要： The polishing uniformity of a material on a substrate is improved by using a polishing method where an applied pressure on the backside of the substrate is changed during the polishing process. The method is especially useful for polishing thin material layers requiring precise control of polishing across the substrate, e.g., for TaSiN layers used in the formation of gate stacks and stacked capacitors.
摘要翻译：通过使用在抛光处理中改变衬底背面施加的压力而改变衬底的材料的抛光均匀性得到改善。该方法对于抛光需要精确控制衬底上的抛光的薄材料层是特别有用的，例如用于形成栅叠层和叠层电容器的TaSiN层。

12. 发明授权

US06319794B1 Structure and method for producing low leakage isolation devices 失效
标题翻译：用于生产低泄漏隔离装置的结构和方法
公开(公告)号：US06319794B1
公开(公告)日：2001-11-20
申请号：US09172697
申请日：1998-10-14
申请人： Hiroyuki Akatsu , Tze-Chiang Chen , Laertis Economikos , Herbert L. Ho , Richard Kleinhenz , Jack A. Mandelman , Wesley C. Natzle
发明人： Hiroyuki Akatsu , Tze-Chiang Chen , Laertis Economikos , Herbert L. Ho , Richard Kleinhenz , Jack A. Mandelman , Wesley C. Natzle
IPC分类号： H01L2176
CPC分类号： H01L21/76232
摘要： A shallow trench isolation structure for a semiconductor device and the method for manufacturing the shallow trench isolation device within a semiconductor substrate. The shallow trench isolation structure is divot-free and includes un-annealed dielectric material as the trench fill material. The intersection of the structure and the semiconductor surface in which it is formed, is free of silicon nitride, but the isolation structure may include a silicon nitride liner which is within the trench and recessed below the semiconductor surface.
摘要翻译：一种用于半导体器件的浅沟槽隔离结构和用于在半导体衬底内制造浅沟槽隔离器件的方法。浅沟槽隔离结构是无凹槽的，并且包括未退火的介电材料作为沟槽填充材料。其结构与其形成的半导体表面的交叉点不含氮化硅，但是隔离结构可以包括位于沟槽内并凹陷在半导体表面下方的氮化硅衬垫。

13. 发明授权

US06294470B1 Slurry-less chemical-mechanical polishing 有权
标题翻译：无浆化学机械抛光
公开(公告)号：US06294470B1
公开(公告)日：2001-09-25
申请号：US09469922
申请日：1999-12-22
申请人： Laertis Economikos , Alexander Simpson
发明人： Laertis Economikos , Alexander Simpson
IPC分类号： H01L21302
CPC分类号： H01L21/31053
摘要： The invention provides slurry-less chemical-mechanical polishing processes which are effective in planarizing oxide materials, especially siliceous oxides, even where the starting oxide layer has significant topographical variation. The processes of the invention are preferably characterized by the use of a fixed abrasive polishing element and by use of an aqueous liquid medium containing a polyelectrolyte for at least a portion of the polishing process involving reduction in the amount of topographic variation (height differential) across the oxide material on the substrate. The method reduces or eliminates the transfer of topographic variations to levels below the desired planarization level. The processes enable elimination of special endpoint detection techniques. The processes are also especially suitable for polishing interlevel dielectrics.
摘要翻译：本发明提供无浆化学机械抛光方法，其有效平坦化氧化物材料，特别是硅氧化物，即使起始氧化物层具有显着的形貌变化。本发明的方法优选的特征在于使用固定的研磨抛光元件，并且通过使用含有聚电解质的含水液体介质，用于抛光过程的至少一部分，包括减少跨越的地形变化量（高差）衬底上的氧化物材料。该方法减少或消除了地形变化的转移到低于期望的平坦化水平的水平。这些过程能够消除特殊的端点检测技术。该工艺也特别适用于抛光层间电介质。

14. 发明授权

US6030881A High throughput chemical vapor deposition process capable of filling high aspect ratio structures 失效
标题翻译：能够填充高纵横比结构的高通量化学气相沉积工艺
公开(公告)号：US6030881A
公开(公告)日：2000-02-29
申请号：US72759
申请日：1998-05-05
申请人： George D. Papasouliotis , Ashima B. Chakravarti , Richard A. Conti , Laertis Economikos , Patrick A. Van Cleemput
发明人： George D. Papasouliotis , Ashima B. Chakravarti , Richard A. Conti , Laertis Economikos , Patrick A. Van Cleemput
IPC分类号： C23C16/04 , C23C16/40 , C23C16/56 , H01L21/762
CPC分类号： H01L21/76224 , C23C16/045 , C23C16/401 , C23C16/56
摘要： A method is provided for filling high aspect ratio gaps without void formation by using a high density plasma (HDP) deposition process with a sequence of deposition and etch steps having varying etch rate-to-deposition rate (etch/dep) ratios. The first step uses an etch/dep ratio less than one to quickly fill the gap. The first step is interrupted before the opening to the gap is closed. The second step uses an etch/dep ratio greater than one to widen the gap. The second step is stopped before corners of the elements forming the gaps are exposed. These steps can be repeated until the aspect ratio of the gap is reduced so that void-free gap-fill is possible. The etch/dep ratio and duration of each step can be optimized for high throughput and high aspect ratio gap-fill capacity.
摘要翻译：提供了一种通过使用具有不同蚀刻速率 - 沉积速率（蚀刻/去除）比率的沉积和蚀刻步骤顺序的高密度等离子体（HDP）沉积工艺来填充高纵横比间隙而无空隙形成的方法。第一步使用小于1的蚀刻/剥离比快速填充间隙。第一步在打开间隙之前中断。第二步使用大于1的蚀刻/剥离比来扩大间隙。在形成间隙的元件的角部暴露之前停止第二步骤。可以重复这些步骤，直到间隙的纵横比减小，使得无空隙间隙填充成为可能。可以优化每个步骤的蚀刻/剥离比和持续时间，以实现高通量和高纵横比填充间隙。

15. 发明授权

US5904868A Mounting and/or removing of components using optical fiber tools 失效
标题翻译：使用光纤工具安装和/或拆卸部件
公开(公告)号：US5904868A
公开(公告)日：1999-05-18
申请号：US927159
申请日：1997-09-11
申请人： Laertis Economikos , Robert Hannon , Charles Joseph Hendricks , Richard Philip Surprenant
发明人： Laertis Economikos , Robert Hannon , Charles Joseph Hendricks , Richard Philip Surprenant
IPC分类号： B23K1/005 , B23K26/06 , H05K13/04 , B23K26/00
CPC分类号： H05K13/0486 , B23K1/0056 , B23K26/06 , B23K26/064
摘要： A laser tool for securing or removing a component from a semiconductor substrate includes a light-transmissive bonding tip having an opening to accommodate a central portion of the component inner and outer walls of the tip being coated with a light reflective material, a portion of the end of the tip being coated with a light absorptive material, so that peripheral areas of the component are locally heated by the tip to mount or remove the component.
摘要翻译：用于从半导体衬底固定或去除部件的激光工具包括具有开口的透光结合尖端，该开口用于容纳尖端的内壁和外壁的部件的中心部分，其被涂覆有光反射材料，一部分尖端的端部涂覆有光吸收材料，使得部件的外围区域被尖端局部加热以安装或移除部件。

16. 发明申请

US20080248643A1 SOLDER CONNECTOR STRUCTURE AND METHOD 有权
标题翻译：焊接连接器结构与方法
公开(公告)号：US20080248643A1
公开(公告)日：2008-10-09
申请号：US12138482
申请日：2008-06-13
申请人： Mukta G. Farooq , Laertis Economikos , Ian D. Melville , Kevin S. Petrarca , Richard P. Volant
发明人： Mukta G. Farooq , Laertis Economikos , Ian D. Melville , Kevin S. Petrarca , Richard P. Volant
IPC分类号： H01L21/44
CPC分类号： H01L24/10 , H01L24/13 , H01L2224/05001 , H01L2224/05009 , H01L2224/05022 , H01L2224/05026 , H01L2224/05027 , H01L2224/05085 , H01L2224/05147 , H01L2224/05166 , H01L2224/05171 , H01L2224/05572 , H01L2224/05624 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/05671 , H01L2224/05684 , H01L2224/13 , H01L2224/13099 , H01L2924/01006 , H01L2924/01013 , H01L2924/01018 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/00 , H01L2924/00014 , H01L2924/013
摘要： Disclosed are embodiments of a far back end of the line solder connector and a method of forming the connector that eliminates the use aluminum, protects the integrity of the ball limiting metallurgy (BLM) layers and promotes adhesion of the BLM layers by incorporating a thin conformal conductive liner into the solder connector structure. This conductive liner coats the top of the via filling in any divots in order to create a uniform surface for BLM deposition and to, thereby, protect the integrity of the BLM layers. The liner further coats the dielectric sidewalls of the well in which the BLM layers are formed in order to enhance adhesion of the BLM layers to the well.
摘要翻译：公开了线焊料连接器的远端的实施例以及形成连接器的方法，其消除了使用铝，保护了球限制冶金（BLM）层的完整性，并且通过并入薄的保形膜来促进BLM层的粘附导电衬里进入焊接接头结构。该导电衬里以通孔填充物的顶部涂覆任何刻痕，以便产生用于BLM沉积的均匀表面，从而保护BLM层的完整性。衬垫还涂覆在其中形成BLM层的阱的电介质侧壁，以便增强BLM层与阱的粘合性。

17. 发明申请

US20080076331A1 DETECTION OF DIAMOND CONTAMINATION IN POLISHING PAD AND RECONDITIONING SYSTEM THEREFOR 失效
标题翻译：检测抛光垫中的金刚石污染及其重建系统
公开(公告)号：US20080076331A1
公开(公告)日：2008-03-27
申请号：US11951616
申请日：2007-12-06
申请人： Laertis Economikos , John Fitzsimmons
发明人： Laertis Economikos , John Fitzsimmons
IPC分类号： B24B1/00
CPC分类号： B24B53/017
摘要： Methods for reconditioning a polishing pad and detecting diamond contamination of the polishing pad are disclosed. In particular, the methods include the step of exposing the reconditioned polishing pad to an energy source to induce the diamond contamination to fluoresce. Detection of the diamond contamination is then made by detecting the fluorescence. Removal of the diamond contamination results in an improved reconditioned polishing pad. A reconditioning system for reconditioning a damaged polishing pad is also disclosed. The reconditioning system includes a reconditioning disk including a plurality of diamonds for reconditioning the polishing pad, wherein each diamond fluoresces when exposed to an energy source.
摘要翻译：公开了用于修补抛光垫并检测抛光垫的金刚石污染的方法。特别地，所述方法包括将修复后的抛光垫暴露于能量源以引起金刚石污染物发荧光的步骤。然后通过检测荧光来检测金刚石污染物。去除金刚石污染导致改进的修复抛光垫。还公开了一种用于修复损坏的抛光垫的修复系统。修复系统包括修复盘，其包括用于修复抛光垫的多个金刚石，其中当暴露于能量源时，每个金刚石发荧光。

18. 发明申请

US20060079159A1 Chemical mechanical polish with multi-zone abrasive-containing matrix 审中-公开
标题翻译：化学机械抛光带多区含磨料的基体
公开(公告)号：US20060079159A1
公开(公告)日：2006-04-13
申请号：US10961670
申请日：2004-10-08
申请人： Markus Naujok , Laertis Economikos
发明人： Markus Naujok , Laertis Economikos
IPC分类号： B24B29/00 , B24D11/00
CPC分类号： B24B37/245 , B24D7/14
摘要： Chemical mechanical polish (CMP) devices, CMP systems, methods of CMP, and methods of manufacturing CMP devices. A CMP device comprises a plurality of zones, with each zone having a matrix of fixed abrasive features disposed therein. The abrasive-containing matrix within each zone has material removal properties that differ from the material removal properties of the abrasive-containing matrixes of the other zones. The material removal property differences of the abrasive-containing matrixes of the zones may achieved by using different abrasive materials, densities, heights, or shapes, or combinations thereof, of the fixed abrasive features within the zones, or by using physical or chemical conditioning. When the novel CMP device is used to planarize a semiconductor wafer, a substantially planar surface with an improved CMP profile results.
摘要翻译：化学机械抛光（CMP）器件，CMP系统，CMP方法和制造CMP器件的方法。 CMP设备包括多个区域，每个区域具有设置在其中的固定研磨特征的矩阵。每个区域内含磨料的基质具有与其它区域的含磨料基质的材料去除性能不同的材料去除性能。通过使用区域内的固定磨料特征的不同研磨材料，密度，高度或形状或其组合，或通过使用物理或化学调节来实现区域中含磨料基质的材料去除性能差异。当使用新颖的CMP器件来平坦化半导体晶片时，得到具有改进的CMP轮廓的基本平坦的表面。

19. 发明授权

US06869860B2 Filling high aspect ratio isolation structures with polysilazane based material 失效
标题翻译：用聚硅氮烷基材料填充高纵横比隔离结构
公开(公告)号：US06869860B2
公开(公告)日：2005-03-22
申请号：US10250092
申请日：2003-06-03
申请人： Michael P. Belyansky , Rama Divakaruni , Laertis Economikos , Rajarao Jammy , Kenneth T. Settlemeyer, Jr. , Padraic C. Shafer
发明人： Michael P. Belyansky , Rama Divakaruni , Laertis Economikos , Rajarao Jammy , Kenneth T. Settlemeyer, Jr. , Padraic C. Shafer
IPC分类号： H01L21/76 , H01L21/762 , H01L21/8242 , H01L27/108
CPC分类号： H01L21/76229
摘要： Isolation trenches and capacitor trenches containing vertical FETs (or any prior levels p-n junctions or dissimilar material interfaces) having an aspect ratio up to 60 are filled with a process comprising: applying a spin-on material based on silazane and having a low molecular weight; pre-baking the applied material in an oxygen ambient at a temperature below about 450 deg C.; converting the stress in the material by heating at an intermediate temperature between 450 deg C. and 800 deg C. in an H2O ambient; and heating again at an elevated temperature in an O2 ambient, resulting in a material that is stable up to 1000 deg C., has a compressive stress that may be tuned by variation of the process parameters, has an etch rate comparable to oxide dielectric formed by HDP techniques, and is durable enough to withstand CMP polishing.
摘要翻译：包含具有高达60的纵横比的垂直FET（或任何先前级别的p-n结或异种材料界面）的隔离沟槽和电容器沟槽被填充了一种方法，其包括：施加基于硅氮烷并且具有低分子量的旋涂材料; 在低于约450℃的温度下在氧环境中预烘烤施加的材料; 通过在H 2 O环境中在450摄氏度和800摄氏度之间的中间温度下加热来转化材料中的应力; 并且在高温下再次在O 2环境中加热，得到稳定至高达1000℃的材料，具有可通过工艺参数变化调节的压缩应力，具有与形成的氧化物电介质相当的蚀刻速率通过HDP技术，并且耐用性足以承受CMP抛光。

20. 发明申请

US20050042877A1 Carbonation of pH controlled KOH solution for improved polishing of oxide films on semiconductor wafers 失效
标题翻译：碳酸化pH控制的KOH溶液，以改善对半导体晶片上的氧化膜的抛光
公开(公告)号：US20050042877A1
公开(公告)日：2005-02-24
申请号：US10825849
申请日：2004-04-16
申请人： Joseph Salfelder , Wayne Swart , Gopalakrishna Prabhu , Srinivas Mirmira , Laertis Economikos , Fen Jamin , Donald Delehanty , Daniel Heenan , Joseph Danza
发明人： Joseph Salfelder , Wayne Swart , Gopalakrishna Prabhu , Srinivas Mirmira , Laertis Economikos , Fen Jamin , Donald Delehanty , Daniel Heenan , Joseph Danza
IPC分类号： H01L21/3105 , H01L21/302 , H01L21/461
CPC分类号： H01L21/31053
摘要： A method and polishing system for planarizing a substrate having one or more materials formed thereon. The method generally includes positioning the substrate in proximity with a polishing pad, dispensing a polishing fluid to the polishing pad, the polishing fluid being subjected to carbonation prior to being dispensed to the polishing pad, and polishing the substrate. The polishing system generally includes a polishing platen having a polishing pad disposed thereon and in proximity to the substrate, a controller configured to cause the polishing pad to contact the substrate, and a polishing fluid delivery system to deliver a polishing fluid to the polishing pad, the polishing fluid delivery system including a carbonation system.
摘要翻译：一种用于平坦化其上形成有一种或多种材料的基板的方法和抛光系统。该方法通常包括将衬底定位在抛光垫附近，将抛光流体分配到抛光垫，抛光流体在分配到抛光垫之前进行碳酸化，并抛光衬底。抛光系统通常包括具有设置在其上并且靠近基板的抛光垫的抛光台板，配置成使抛光垫与基板接触的控制器和抛光流体输送系统以将抛光流体输送到抛光垫，抛光液输送系统包括碳酸化系统。

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