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11. 发明授权

US07580306B2 Semiconductor memory apparatus 有权
标题翻译：半导体存储装置
公开(公告)号：US07580306B2
公开(公告)日：2009-08-25
申请号：US11637758
申请日：2006-12-13
申请人： Ho Youb Cho
发明人： Ho Youb Cho
IPC分类号： G11C7/02 , G11C5/14 , G11C7/00
CPC分类号： G11C7/065 , G11C7/08 , G11C2207/065
摘要： A semiconductor memory apparatus includes a sense amplifier that receives a driving voltage through a sense amplifier power supply input terminal and detects and amplifies a difference between signals that are supplied to two input lines, a sense amplifier voltage supply unit that supplies a driving voltage and an overdriving voltage higher than the driving voltage to the sense amplifier through the sense amplifier power supply input terminal using a power supply voltage, and a driving voltage control unit that maintains a driving voltage level of the sense amplifier power supply input terminal in response to the level of the power supply voltage, after a voltage of the sense amplifier power supply input terminal is elevated to a power supply level responding to the overdriving voltage in order to perform the overdriving operation.
摘要翻译：半导体存储装置包括读出放大器，其通过读出放大器电源输入端子接收驱动电压，并检测并放大提供给两条输入线的信号之间的差异;提供驱动电压的读出放大器电压供给单元，通过使用电源电压的感测放大器电源输入端子将高于通过感测放大器的驱动电压的过驱动电压，以及驱动电压控制单元，其响应于电平维持感测放大器电源输入端子的驱动电压电平的电源电压，在感测放大器电源输入端子的电压升高到响应过驱动电压的电源电平以执行过驱动操作之后。

12. 发明申请

US20070201291A1 Semiconductor memory apparatus 有权
标题翻译：半导体存储装置
公开(公告)号：US20070201291A1
公开(公告)日：2007-08-30
申请号：US11637758
申请日：2006-12-13
申请人： Ho Youb Cho
发明人： Ho Youb Cho
IPC分类号： G11C7/00 , G11C7/02
CPC分类号： G11C7/065 , G11C7/08 , G11C2207/065
摘要： A semiconductor memory apparatus includes a sense amplifier that receives a driving voltage through a sense amplifier power supply input terminal and detects and amplifies a difference between signals that are supplied to two input lines, a sense amplifier voltage supply unit that supplies a driving voltage and an overdriving voltage higher than the driving voltage to the sense amplifier through the sense amplifier power supply input terminal using a power supply voltage, and a driving voltage control unit that maintains a driving voltage level of the sense amplifier power supply input terminal in response to the level of the power supply voltage, after a voltage of the sense amplifier power supply input terminal is elevated to a power supply level responding to the overdriving voltage in order to perform the overdriving operation.
摘要翻译：半导体存储装置包括读出放大器，其通过读出放大器电源输入端子接收驱动电压，并检测并放大提供给两条输入线的信号之间的差异;提供驱动电压的读出放大器电压供给单元，通过使用电源电压的感测放大器电源输入端子将高于通过感测放大器的驱动电压的过驱动电压，以及驱动电压控制单元，其响应于电平维持感测放大器电源输入端子的驱动电压电平的电源电压，在感测放大器电源输入端子的电压升高到响应过驱动电压的电源电平以执行过驱动操作之后。

13. 发明授权

US07161856B2 Circuit for generating data strobe signal of semiconductor memory device 有权
公开(公告)号：US07161856B2
公开(公告)日：2007-01-09
申请号：US11115351
申请日：2005-04-27
申请人： Sung Joo Ha , Ho Youb Cho
发明人： Sung Joo Ha , Ho Youb Cho
IPC分类号： G11C7/00
CPC分类号： G11C7/222 , G11C7/22 , G11C8/18 , G11C11/4076
摘要： A circuit for generating a data strobe signal of a semiconductor memory device comprises a plurality of internal clock delay units, a selecting control unit and a pulse generating unit. The plurality of internal clock delay units delay an internal clock signal in response to a plurality of CAS latency signal. The selecting control unit logically combines a data latch control signal to latch input data with output signals from the plurality of internal clock delay units. The pulse generating unit generates the data strobe signal having a predetermined pulse in response to an output signal from the selecting control unit. In the circuit, a tDQSS margin is regulated depending on change of tCK of an operating frequency in response to a CAS latency signal.

14. 发明授权

US06850444B2 Data input device of a DDR SDRAM 有权
标题翻译： DDR SDRAM的数据输入设备
公开(公告)号：US06850444B2
公开(公告)日：2005-02-01
申请号：US10670613
申请日：2003-09-25
申请人： Ho Youb Cho
发明人： Ho Youb Cho
IPC分类号： G11C11/40 , G11C5/00 , G11C7/10 , G11C7/22 , G11C11/4096
CPC分类号： G11C7/1087 , G11C7/1042 , G11C7/1066 , G11C7/1078 , G11C7/1093 , G11C11/4096
摘要： A data input device of a DDR SDRAM includes at least a clock pulse generator (for outputting a data-in-strobe signal based on internal clock), first and second data buffers (being controlled by the data-in-strobe signal and having output lines corresponding to first and second global input-output lines, respectively). When a second control signal is low, the first data is directly applied to the first data buffer for transfer to the first global input/output line, and the second data is directly applied to the second data buffer for transfer to the second global input/output line. When the second control signal is high, the first data is directly applied to the second data buffer for transfer to the second global input/output line, and the second data is directly applied to the first data buffer for transfer to the first global input/output line. The time for the write operation is reduced by directly applying the write-in-strobe signal to the data buffers.
摘要翻译： DDR SDRAM的数据输入装置至少包括时钟脉冲发生器（用于输出基于内部时钟的数据选通信号），第一和第二数据缓冲器（由数据选通信号控制并具有输出分别对应于第一和第二全局输入 - 输出线的线）。当第二控制信号为低时，将第一数据直接施加到第一数据缓冲器以传送到第一全局输入/输出线，并且将第二数据直接应用于第二数据缓冲器以传送到第二全局输入/ 输出线。当第二控制信号为高时，将第一数据直接施加到第二数据缓冲器以传送到第二全局输入/输出线，并且将第二数据直接应用于第一数据缓冲器以传送到第一全局输入/ 输出线。通过将写入选通信号直接应用于数据缓冲器来减少写操作的时间。

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