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    • 16. 发明授权
    • Clock signal extracting circuit
    • 时钟信号提取电路
    • US4435825A
    • 1984-03-06
    • US352379
    • 1982-02-25
    • Keiji Tomooka
    • Keiji Tomooka
    • H04L7/027H03K5/1532H03K7/02H04L7/02H04L7/033H04L7/04
    • H04L7/007H03K5/1532H04L7/0331
    • A clock extractor is disclosed in which an input data signal is sampled and held in accordance with a sampling frequency, the input data signal thus processed is subjected to equalization and amplification, a difference in voltage (namely, height) is detected between those portions of a waveform obtained after the equalization and amplification which appear before and after a time when the waveform has a maximum voltage amplitude, a phase of that portion of the waveform which has the maximum voltage amplitude, is determined by making the above-mentioned difference equal to zero, and a clock signal synchronized with the portion having the maximum voltage amplitude is extracted and reproduced from the input data signal.
    • 公开了一种时钟提取器,其中根据采样频率对输入数据信号进行采样和保持,对这样处理的输入数据信号进行均衡和放大,在这些部分之间检测到电压差(即高度) 在波形具有最大电压振幅的时间之前和之后出现均衡和放大后获得的波形,具有最大电压振幅的波形部分的相位是通过使上述差值等于 并且从输入数据信号提取并再现与具有最大电压幅度的部分同步的时钟信号。