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11. 发明授权

US07005839B2 Reference power supply circuit for semiconductor device 失效
标题翻译：半导体器件参考电源电路
公开(公告)号：US07005839B2
公开(公告)日：2006-02-28
申请号：US10803934
申请日：2004-03-19
申请人： Masaharu Wada
发明人： Masaharu Wada
IPC分类号： G05F3/16
CPC分类号： G05F3/30
摘要： A first PN junction and first current supply are connected between a first potential and a second potential. A second PN junction, first resistive element and second current supply are connected between the first potential and the second potential, the size of the second PN junction being different from that of the first PN junction. A second resistive element is connected in parallel with the first resistive element and second PN junction. A differential amplifier is configured to receive, at an inverting input terminal, a potential between a first current supply and the first PN junction and, at a non-inverting input terminal, a potential on a connection point between a second current supply and the first resistor and to control the first, second and third current supplies by a potential difference between the inverting input and the non-inverting input.
摘要翻译：第一PN结和第一电流源连接在第一电势和第二电位之间。第二PN结，第一电阻元件和第二电流源连接在第一电位和第二电位之间，第二PN结的大小与第一PN结的尺寸不同。第二电阻元件与第一电阻元件和第二PN结并联连接。差分放大器被配置为在反相输入端处接收第一电流源和第一PN结之间的电势，并且在非反相输入端处接收第二电流源与第一PN结之间的连接点上的电位并且通过反相输入和非反相输入之间的电位差来控制第一，第二和第三电流源。

12. 发明授权

US5949109A Semiconductor device having input protection circuit 失效
标题翻译：具有输入保护电路的半导体器件
公开(公告)号：US5949109A
公开(公告)日：1999-09-07
申请号：US790804
申请日：1997-01-30
申请人： Mitsuru Shimizu , Syuso Fujii , Kenji Numata , Masaharu Wada
发明人： Mitsuru Shimizu , Syuso Fujii , Kenji Numata , Masaharu Wada
IPC分类号： H01L27/02 , H01L23/62
CPC分类号： H01L27/0251
摘要： According to this invention, a well region is formed on a semiconductor substrate. An n.sup.+ -type first semiconductor region is formed in the well region, and an input pad for receiving an external signal is connected near the first semiconductor region. This input pad is connected to an input circuit of an integrated circuit constituted by an inverter circuit and to an external terminal for receiving an external signal. N.sup.+ -type second semiconductor regions are formed in the well region located on both sides of the first semiconductor region. A ground potential Vss is applied to these second semiconductor regions. A p.sup.+ -type third semiconductor region is formed around these second semiconductor regions in the well region. The ground potential is applied to the third semiconductor region. Therefore, a parallel circuit formed by a parasitic transistor and a parasitic diode is formed between the input pad and the ground potential. The parasitic transistor is turned on upon electrostatic discharge, and the parasitic diode is turned on when a negative potential for test is applied to the input pad, thereby preventing an erroneous operation of a transistor arranged on the semiconductor substrate.
摘要翻译：根据本发明，在半导体衬底上形成阱区。在阱区中形成n +型第一半导体区，并且用于接收外部信号的输入焊盘连接在第一半导体区附近。该输入焊盘连接到由逆变器电路构成的集成电路的输入电路和用于接收外部信号的外部端子。在位于第一半导体区域的两侧的阱区中形成N +型第二半导体区域。对这些第二半导体区域施加接地电位Vss。在阱区中围绕这些第二半导体区域形成p +型第三半导体区域。接地电位施加到第三半导体区域。因此，在输入焊盘和接地电位之间形成由寄生晶体管和寄生二极管形成的并联电路。寄生晶体管在静电放电时导通，当向输入焊盘施加用于测试的负电位时，寄生二极管导通，从而防止布置在半导体衬底上的晶体管的错误操作。

13. 发明授权

US07944242B2 Semiconductor integrated circuit having insulated gate field effect transistors 失效
标题翻译：具有绝缘栅场效应晶体管的半导体集成电路
公开(公告)号：US07944242B2
公开(公告)日：2011-05-17
申请号：US12703924
申请日：2010-02-11
申请人： Masaharu Wada , Takehiko Hojo
发明人： Masaharu Wada , Takehiko Hojo
IPC分类号： H03K19/096 , H03K3/356
CPC分类号： H03K5/1504 , G11C19/00 , G11C19/28 , H03K5/133 , H03K19/00384 , H03K2005/00136 , H03M1/502
摘要： A semiconductor integrated circuit includes a multiplexer, a signal generating circuit, a control circuit, m inverters, n two-input NOR circuits, and cascade connected n two-shift registers. The control circuit generates a control signal in the disable state in a normal operation in which the clock signal is supplied. The control circuit generates a control signal in an enable state in the other-than-normal operation in which a higher voltage source voltage is supplied while the clock signal is not supplied. The multiplexer receives the clock signal and a low-frequency signal outputted from the signal generating circuit. The multiplexer supplies the clock signal to the sequence of the inverters upon receipt of the control signal in the disable state, and supplies the low-frequency signal to the sequence of the inverters upon receipt of the control signal in the enable state.
摘要翻译：半导体集成电路包括多路复用器，信号发生电路，控制电路，m个反相器，n个双输入NOR电路和级联的n个双移位寄存器。控制电路在提供时钟信号的正常操作中产生处于禁止状态的控制信号。控制电路在不提供时钟信号的情况下，在提供较高的电压源电压的正常以外的操作中产生使能状态的控制信号。多路复用器接收时钟信号和从信号发生电路输出的低频信号。在接收到处于禁用状态的控制信号时，多路复用器将时钟信号提供给逆变器的序列，并且在使能状态下接收到控制信号时，将低频信号提供给逆变器的序列。

14. 发明授权

US06977828B2 DC-DC converter applied to semiconductor device 失效
标题翻译： DC-DC转换器应用于半导体器件
公开(公告)号：US06977828B2
公开(公告)日：2005-12-20
申请号：US10601538
申请日：2003-06-24
申请人： Masaharu Wada
发明人： Masaharu Wada
IPC分类号： H02M1/14 , H02M3/07 , H02M3/18
CPC分类号： H02M3/073 , H02M1/14 , H02M2003/072
摘要： An oscillator produces a signal. A voltage generating circuit is responsive to the output signal of the oscillator to generate a second voltage different from a first voltage. A voltage detecting circuit detects the output voltage of the voltage generating circuit and outputs an output voltage corresponding to the second voltage. A comparator makes a comparison between the output voltage of the voltage detecting circuit and a reference voltage with each cycle of the output signal of the oscillator and controls the operation of the voltage generating circuit.
摘要翻译：振荡器产生信号。电压产生电路响应振荡器的输出信号以产生不同于第一电压的第二电压。电压检测电路检测电压产生电路的输出电压，并输出对应于第二电压的输出电压。比较器在振荡器的输出信号的每个周期之间比较电压检测电路的输出电压和参考电压，并且控制电压产生电路的操作。

15. 发明申请

US20050127889A1 Reference power supply circuit for semiconductor device 失效
标题翻译：半导体器件参考电源电路
公开(公告)号：US20050127889A1
公开(公告)日：2005-06-16
申请号：US10803934
申请日：2004-03-19
申请人： Masaharu Wada
发明人： Masaharu Wada
IPC分类号： G05F3/24 , G05F1/44 , G05F3/30
CPC分类号： G05F3/30
摘要： A first PN junction and first current supply are connected between a first potential and a second potential. A second PN junction, first resistive element and second current supply are connected between the first potential and the second potential, the size of the second PN junction being different from that of the first PN junction. A second resistive element is connected in parallel with the first resistive element and second PN junction. A differential amplifier is configured to receive, at an inverting input terminal, a potential between a first current supply and the first PN junction and, at a non-inverting input terminal, a potential on a connection point between a second current supply and the first resistor and to control the first, second and third current supplies by a potential difference between the inverting input and the non-inverting input.
摘要翻译：第一PN结和第一电流源连接在第一电势和第二电位之间。第二PN结，第一电阻元件和第二电流源连接在第一电位和第二电位之间，第二PN结的大小与第一PN结的尺寸不同。第二电阻元件与第一电阻元件和第二PN结并联连接。差分放大器被配置为在反相输入端处接收第一电流源和第一PN结之间的电势，并且在非反相输入端处接收第二电流源与第一PN结之间的连接点上的电位并且通过反相输入和非反相输入之间的电位差来控制第一，第二和第三电流源。

16. 发明授权

US06888384B2 Power-on detector, and power-on reset circuit using the same 失效
标题翻译：上电检测器和使用其的上电复位电路
公开(公告)号：US06888384B2
公开(公告)日：2005-05-03
申请号：US10601623
申请日：2003-06-24
申请人： Masaharu Wada
发明人： Masaharu Wada
IPC分类号： H03K17/22
CPC分类号： H03K17/223
摘要： A power-on detector includes a reference potential generation circuit which generates a reference potential, and a comparator which compares the first voltage generated on the basis of the reference potential output from the reference potential generation circuit and the potential of the first potential supply source, and the second voltage generated on the basis of the reference potential and the potential of the second potential supply source different from the potential of the first potential supply source. Power-on is detected when the potential difference between the potentials of the first and second potential supply sources upon power-on becomes larger than the sum of the first and second voltages.
摘要翻译：上电检测器包括产生参考电位的参考电位产生电路和比较器，其比较基于从参考电位产生电路输出的参考电位产生的第一电压和第一电位供给源的电位，并且基于参考电位产生的第二电压和与第一电位供给源的电位不同的第二电位源的电位。当上电时第一和第二电位电位的电位之间的电势差大于第一和第二电压之和时，检测到上电。

17. 发明授权

US5594265A Input protection circuit formed in a semiconductor substrate 失效
标题翻译：形成在半导体衬底中的输入保护电路
公开(公告)号：US5594265A
公开(公告)日：1997-01-14
申请号：US799342
申请日：1991-11-27
申请人： Mitsuru Shimizu , Syuso Fujii , Kenji Numata , Masaharu Wada
发明人： Mitsuru Shimizu , Syuso Fujii , Kenji Numata , Masaharu Wada
IPC分类号： H01L27/02 , H01L23/62
CPC分类号： H01L27/0251
摘要： According to the invention, a well region is formed on a semiconductor substrate. An n.sup.+ -type first semiconductor region is formed in the well region, and an input pad for receiving an external signal is connected near the first semiconductor region. This input pad is connected to an input circuit of an integrated circuit constituted by an inverter circuit and to an external terminal for receiving an external signal. N.sup.+ -type second semiconductor regions are formed in the well region located on both sides of the first semiconductor region. A ground potential Vss is applied to these second semiconductor regions. A p.sup.+ -type third semiconductor region is formed around these second semiconductor regions in the well region. The ground potential is applied to the third semiconductor region. Therefore, a parallel circuit formed by a parasitic transistor and a parasitic diode is formed between the input pad and the ground potential. The parasitic transistor is turned on upon electrostatic discharge, and the parasitic diode is turned on when a negative potential for test is applied to the input pad, thereby preventing an erroneous operation of a transistor arranged on the semiconductor substrate.
摘要翻译：根据本发明，在半导体衬底上形成阱区。在阱区中形成n +型第一半导体区，并且用于接收外部信号的输入焊盘连接在第一半导体区附近。该输入焊盘连接到由逆变器电路构成的集成电路的输入电路和用于接收外部信号的外部端子。在位于第一半导体区域的两侧的阱区中形成N +型第二半导体区域。对这些第二半导体区域施加接地电位Vss。在阱区中围绕这些第二半导体区域形成p +型第三半导体区域。接地电位施加到第三半导体区域。因此，在输入焊盘和接地电位之间形成由寄生晶体管和寄生二极管形成的并联电路。寄生晶体管在静电放电时导通，当向输入焊盘施加用于测试的负电位时，寄生二极管导通，从而防止布置在半导体衬底上的晶体管的错误操作。

18. 发明申请

US20130051167A1 SEMICONDUCTOR MEMORY DEVICE AND DEFECTIVE CELL RELIEVING METHOD 有权
标题翻译：半导体存储器件和缺陷细胞消除方法
公开(公告)号：US20130051167A1
公开(公告)日：2013-02-28
申请号：US13425364
申请日：2012-03-20
申请人： Takayuki Iwai , Makoto Takahashi , Masaharu Wada , Mariko Iizuka , Kimimasa Imai
发明人： Takayuki Iwai , Makoto Takahashi , Masaharu Wada , Mariko Iizuka , Kimimasa Imai
IPC分类号： G11C29/00 , G11C8/00 , G11C8/10 , G11C17/16
CPC分类号： G11C29/702 , G11C29/785 , G11C2029/0401 , G11C2029/4402
摘要： A memory cell array of a first semiconductor chip includes a normal cell array and a spare cell array. A first defect address data output circuit outputs first defect address data indicating an address of a defective memory cell in the memory cell array. A first comparison circuit compares address data with the first defect address data and outputs a first match signal in case of matching. A second defect address data output circuit outputs second defect address data indicating an address of a defective memory cell in the memory cell array. A second comparison circuit compares the address data with the second defect address data and outputs a second match signal in case of matching.
摘要翻译：第一半导体芯片的存储单元阵列包括正常单元阵列和备用单元阵列。第一缺陷地址数据输出电路输出指示存储单元阵列中缺陷存储单元地址的第一缺陷地址数据。第一比较电路将地址数据与第一缺陷地址数据进行比较，并在匹配的情况下输出第一匹配信号。第二缺陷地址数据输出电路输出指示存储单元阵列中缺陷存储单元的地址的第二缺陷地址数据。第二比较电路将地址数据与第二缺陷地址数据进行比较，并在匹配的情况下输出第二匹配信号。

19. 发明授权

US06483756B2 Sequence circuit and semiconductor device using sequence circuit 有权
公开(公告)号：US06483756B2
公开(公告)日：2002-11-19
申请号：US09984270
申请日：2001-10-29
申请人： Atsushi Takeuchi , Masaharu Wada
发明人： Atsushi Takeuchi , Masaharu Wada
IPC分类号： G11C1604
CPC分类号： G11C5/143 , G11C8/08
摘要： A semiconductor device includes a word line that is reset to a negative voltage when the word line is unselected. The semiconductor device further includes a sequence circuit that clamps the word line to a first fixed voltage, until a fixed power-supply voltage that is supplied to a memory cell connected to the word line reaches a second fixed voltage, at a time of starting power supply. Thus, the semiconductor device can prevent a negative power-supply voltage used for resetting the word line from rising, and can reduce consumed energy.

20. 发明授权

US5982680A Semiconductor memory 失效
标题翻译：半导体存储器
公开(公告)号：US5982680A
公开(公告)日：1999-11-09
申请号：US181976
申请日：1998-10-29
申请人： Masaharu Wada
发明人： Masaharu Wada
IPC分类号： G11C11/401 , G11C29/00 , G11C29/04 , G11C7/00
CPC分类号： G11C29/80 , G11C29/808
摘要： A memory cell array is composed of N (1.ltoreq.N.ltoreq.Nmax) blocks. A redundancy memory is always composed of Nmax blocks. A block decoder selects one of the N blocks of the memory cell array based on a block address signal. A redundancy memory decoder selects one of the Nmax blocks of the redundancy memory based on a redundancy memory selection address signal. When the number of blocks of the memory cell array and the number of blocks of the redundancy memory are different from each other, the N blocks of the memory cell array are in a one to one correspondence with N blocks of the Nmax blocks of the redundancy memory and the redundancy memory decoder selects one of the N blocks of the redundancy memory. The other blocks than the N blocks of the redundancy memory are left unused.
摘要翻译：存储单元阵列由N（1≤N≤Nmax）个块组成。冗余存储器总是由Nmax块组成。块解码器基于块地址信号选择存储单元阵列的N个块中的一个。冗余存储器解码器基于冗余存储器选择地址信号来选择冗余存储器的Nmax个块中的一个。当存储单元阵列的块数和冗余存储器的块的数量彼此不同时，存储单元阵列的N个块与冗余的Nmax个块的N个块一一对应存储器和冗余存储器解码器选择冗余存储器的N个块中的一个。除冗余存储器的N个块之外的其他块不被使用。

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