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11. 发明授权

US07054403B2 Phase-Locked Loop 失效
标题翻译：锁相环
公开(公告)号：US07054403B2
公开(公告)日：2006-05-30
申请号：US09979254
申请日：2001-03-21
申请人： Hideyuki Nosaka , Hiroyuki Fukuyama , Hideki Kamitsuna
发明人： Hideyuki Nosaka , Hiroyuki Fukuyama , Hideki Kamitsuna
IPC分类号： H03D3/24
CPC分类号： H03L7/10 , H03L7/087
摘要： A phase lock circuit has a signal path to which a phase comparator, a loop filter and a voltage control oscillator are connected in series, the phase comparator being adapted to compare the phase of an input signal VIN with the phase in the output signal of the voltage control oscillator and to output its result of comparison, the loop filter being adapted to receive the output signal of the phase comparator and to output a DC voltage; the voltage control oscillator being adapted to control the output oscillation frequency depending on the DC output voltage of the loop filter, the phase lock circuit further comprising voltage tracking means for adding, to the voltage of the signal path, a signal causing the average voltage in the output voltage of the phase comparator to coincide with a predetermined reference voltage, whereby the voltage tracking means can enlarge the lock range in the phase lock circuit.
摘要翻译：锁相电路具有相位比较器，环路滤波器和压控振荡器串联连接的信号路径，该相位比较器适于将输入信号V IN IN的相位与电压控制振荡器的输出信号的相位并输出其比较结果，环路滤波器适于接收相位比较器的输出信号并输出直流电压; 所述电压控制振荡器适于根据所述环路滤波器的直流输出电压来控制所述输出振荡频率，所述锁相电路还包括电压跟踪装置，用于将所述信号路径的电压加到所述信号路径的电压中，相位比较器的输出电压与预定的参考电压一致，由此电压跟踪装置可以扩大锁相电路中的锁定范围。

12. 发明授权

US08493257B2 Current-switching cell and digital-to-analog converter 有权
标题翻译：电流开关单元和数模转换器
公开(公告)号：US08493257B2
公开(公告)日：2013-07-23
申请号：US13145782
申请日：2010-01-28
申请人： Munehiko Nagatani , Hideyuki Nosaka , Shogo Yamanaka , Kimikazu Sano , Koichi Murata
发明人： Munehiko Nagatani , Hideyuki Nosaka , Shogo Yamanaka , Kimikazu Sano , Koichi Murata
IPC分类号： H03M1/66
CPC分类号： H03M1/662 , H03M1/742
摘要： Two D flip-flops (D-FFMA, D-FFMB) output two half-rate signals (DMR-A, DMR-B) by dividing a digital input signal (DM) into two signals and retiming them based on a clock signal (CLK) and a negative-phase clock signal (CLKB). First and second switches (SM1, SM2) are driven by the two half-rate signals (DMR-A, DMR-B). Third and fourth switches (SM3, SM4) are driven by a select signal SW and a negative-phase select signal SWB that have the same frequency as that of the clock signal (CLK) but a different phase from that of the clock signal (CLK). The current supplied from a current source (1) to a load (4) thus becomes a current signal corresponding to a conversion frequency twice the frequency of the clock signal (CLK).
摘要翻译：两个D触发器（D-FFMA，D-FFMB）通过将数字输入信号（DM）分成两个信号并基于时钟信号重新定时（DMR-A，D-FFMB）输出两个半速率信号 CLK）和负相位时钟信号（CLKB）。第一和第二开关（SM1，SM2）由两个半速率信号（DMR-A，DMR-B）驱动。第三和第四开关（SM3，SM4）由与时钟信号（CLK）频率相同的频率的选择信号SW和负相位选择信号SWB驱动，但与时钟信号（CLK ）。因此，从电流源（1）提供给负载（4）的电流成为与时钟信号（CLK）的频率的两倍的转换频率相对应的电流信号。

13. 发明授权

US09143110B2 Automatic gain control circuit 有权
标题翻译：自动增益控制电路
公开(公告)号：US09143110B2
公开(公告)日：2015-09-22
申请号：US14114519
申请日：2012-06-29
申请人： Kimikazu Sano , Hiroyuki Fukuyama , Makoto Nakamura , Hideyuki Nosaka , Miwa Mutoh , Koichi Murata
发明人： Kimikazu Sano , Hiroyuki Fukuyama , Makoto Nakamura , Hideyuki Nosaka , Miwa Mutoh , Koichi Murata
IPC分类号： H03G3/10 , H03F1/08 , H03G3/30
CPC分类号： H03G3/30 , H03G3/3084
摘要： An automatic gain control circuit (5a) includes a peak detector circuit (10) that detects the peak voltage of the output signal from a variable gain amplifier (3), an average value detection and output amplitude setting circuit (11) that detects the average voltage of the output signals from the variable gain amplifier (3) and adds a voltage ½ the desired output amplitude of the variable gain amplifier (3) to the average voltage, and a high gain amplifier (12) that amplifies the difference between the output voltage of the peak detector circuit (10) and the output voltage of the average value detection and output amplitude setting circuit (11) and controls the gain of the variable gain amplifier (3) using the amplification result as a gain control signal. The peak detector circuit (10) includes transistors (Q1, Q2, Q3), a current source (I1), and a filter circuit. The filter circuit includes a series connection of a resistor (Ra) and a capacitor (C1).
摘要翻译：自动增益控制电路（5a）包括检测来自可变增益放大器（3）的输出信号的峰值电压的峰值检测电路（10），检测平均值的平均值检测和输出幅度设定电路（11）来自可变增益放大器（3）的输出信号的电压，并将可变增益放大器（3）的期望输出幅度的电压½加到平均电压上;以及高增益放大器（12），放大输出峰值检测器电路（10）的电压和平均值检测和输出幅度设置电路（11）的输出电压，并且使用放大结果来控制可变增益放大器（3）的增益作为增益控制信号。峰值检测器电路（10）包括晶体管（Q1，Q2，Q3），电流源（I1）和滤波器电路。滤波电路包括电阻（Ra）和电容器（C1）的串联连接。

14. 发明授权

US08687968B2 Vector sum phase shifter, optical transceiver, and control circuit 有权
标题翻译：矢量和移相器，光收发器和控制电路
公开(公告)号：US08687968B2
公开(公告)日：2014-04-01
申请号：US13059226
申请日：2009-08-12
申请人： Hideyuki Nosaka , Munehiko Nagatani , Shogo Yamanaka , Kimikazu Sano , Koichi Murata , Kiyomitsu Onodera , Takatomo Enoki
发明人： Hideyuki Nosaka , Munehiko Nagatani , Shogo Yamanaka , Kimikazu Sano , Koichi Murata , Kiyomitsu Onodera , Takatomo Enoki
IPC分类号： H04B10/00
CPC分类号： H03H11/20 , H03H2007/0192 , H03H2011/0494 , H04B10/505 , H04B2210/517
摘要： A vector sum phase shifter includes a 90° phase shifter (1) which generates an in-phase signal (VINI) and a quadrature signal (VINQ) from an input signal (VIN), a four-quadrant multiplier (2I) which changes the amplitude of the in-phase signal (VINI) based on a control signal (CI), a four-quadrant multiplier (2Q) which changes the amplitude of the quadrature signal (VINQ) based on a control signal (CQ), a combiner (3) which combines the in-phase signal (VINI) and the quadrature signal (VINQ), and a control circuit (4). The control circuit (4) includes a voltage generator which generates a reference voltage, and a differential amplifier which outputs the difference signal between a control voltage (VC) and the reference voltage as the control signal (CI, CQ). The differential amplifier performs an analog operation of converting the control voltage (VC) into the control signal (CI, CQ) similar to a sine wave or a cosine wave.
摘要翻译：矢量和移相器包括从输入信号（VIN）产生同相信号（VINI）和正交信号（VINQ）的90°移相器（1），四象限乘法器（2I），其改变基于控制信号（CI）的同相信号（VINI）的幅度，基于控制信号（CQ）改变正交信号（VINQ）的幅度的四象限乘法器（2Q），组合器 3），其组合了同相信号（VINI）和正交信号（VINQ），以及控制电路（4）。控制电路（4）包括产生参考电压的电压发生器和输出控制电压（VC）和基准电压之间的差分信号作为控制信号（CI，CQ）的差分放大器。差分放大器进行与正弦波或余弦波相似的将控制电压（VC）转换为控制信号（CI，CQ）的模拟操作。

15. 发明申请

US20120326782A1 AUTOMATIC GAIN CONTROL CIRCUIT 有权
标题翻译：自动增益控制电路
公开(公告)号：US20120326782A1
公开(公告)日：2012-12-27
申请号：US13527512
申请日：2012-06-19
申请人： Kimikazu Sano , Hiroyuki Fukuyama , Hideyuki Nosaka , Makoto Nakamura , Koichi Murata , Masatoshi Tobayashi , Yasunobu Inabe , Eisuke Tsuchiya
发明人： Kimikazu Sano , Hiroyuki Fukuyama , Hideyuki Nosaka , Makoto Nakamura , Koichi Murata , Masatoshi Tobayashi , Yasunobu Inabe , Eisuke Tsuchiya
IPC分类号： H03G3/20
CPC分类号： H03G1/0023
摘要： In an automatic gain control circuit, a peak detection circuit detects and outputs the peak voltage of an output signal from a variable gain circuit. An average value detection/output amplitude setting circuit detects the average value voltage of an output signal from the variable gain circuit, and outputs a calculated voltage. An amplification circuit controls the gain of the variable gain circuit by amplifying the difference between the output voltages of the peak detection circuit and average value detection/output amplitude setting circuit. The number of base-emitter junctions of transistors on a path in the peak detection circuit from input ports which receive output signals from the variable gain circuit to an output port which outputs a voltage to the amplification circuit is equal to the number of base-emitter junctions of transistors on a path in the average value detection/output amplitude setting circuit.
摘要翻译：在自动增益控制电路中，峰值检测电路检测并输出来自可变增益电路的输出信号的峰值电压。平均值检测/输出振幅设定电路检测来自可变增益电路的输出信号的平均值电压，并输出计算出的电压。放大电路通过放大峰值检测电路的输出电压和平均值检测/输出幅度设定电路之间的差来控制可变增益电路的增益。从输入端口接收峰值检测电路中的路径上的晶体管的基极 - 发射极结数量，该输入端口从可变增益电路接收输出到放大电路的电压的输出端口等于基极 - 发射极在平均值检测/输出幅度设置电路中的路径上的晶体管的结。

16. 发明申请

US20120319766A1 SIGNAL OUTPUT CIRCUIT 有权
标题翻译：信号输出电路
公开(公告)号：US20120319766A1
公开(公告)日：2012-12-20
申请号：US13527510
申请日：2012-06-19
申请人： Kimikazu Sano , Hiroyuki Fukuyama , Hideyuki Nosaka , Makoto Nakamura , Koichi Murata , Masatoshi Tobayashi , Eisuke Tsuchiya
发明人： Kimikazu Sano , Hiroyuki Fukuyama , Hideyuki Nosaka , Makoto Nakamura , Koichi Murata , Masatoshi Tobayashi , Eisuke Tsuchiya
IPC分类号： G05F3/02
CPC分类号： H03K19/017545
摘要： In a signal output circuit, an input buffer externally receives a single-phase switching instruction signal to switch a state of the output circuit a shutdown disable state or a shutdown enable state, and converts and outputs the single-phase switching instruction signal into a differential switching instruction signal. A generation control circuit outputs a generation control signal for controlling generation of a control voltage in the control voltage generation circuit based on the differential switching instruction signal. A control voltage generation circuit outputs the control voltage upon changing a value of the control voltage in accordance with a logic of the single-phase switching instruction signal. An output circuit externally receives a differential input signal, outputs a differential output signal upon impedance-converting the differential input signal, and switches between the shutdown disable state and the shutdown enable state of the differential input signal.
摘要翻译：在信号输出电路中，输入缓冲器从外部接收单相开关指令信号，以将输出电路的状态切换到关闭禁止状态或关断使能状态，并将单相切换指令信号转换并输出到差分切换指令信号。一代控制电路根据差动切换指示信号输出用于控制控制电压产生电路中的控制电压产生的发电控制信号。控制电压产生电路根据单相切换指令信号的逻辑改变控制电压的值来输出控制电压。输出电路从外部接收差分输入信号，通过对差分输入信号进行阻抗转换来输出差分输出信号，并在差分输入信号的关断禁止状态和关断使能状态之间切换。

17. 发明申请

US20120106618A1 METHOD FOR RECEIVING FREQUENCY DOMAIN MULTIPLEXED SIGNAL AND DEVICE FOR RECEIVING FREQUENCY DOMAIN MULTIPLEXED SIGNAL 有权
标题翻译：用于接收频域多路信号的方法和用于接收频域多路信号的装置
公开(公告)号：US20120106618A1
公开(公告)日：2012-05-03
申请号：US13381114
申请日：2010-07-15
申请人： Riichi Kudo , Takayuki Kobayashi , Koichi Ishihara , Yasushi Takatori , Hideyuki Nosaka , Munehiro Matsui , Masato Mizoguchi , Tadao Nakagawa , Etsushi Yamazaki , Akihide Sano , Yutaka Miyamoto , Eiji Yoshida
发明人： Riichi Kudo , Takayuki Kobayashi , Koichi Ishihara , Yasushi Takatori , Hideyuki Nosaka , Munehiro Matsui , Masato Mizoguchi , Tadao Nakagawa , Etsushi Yamazaki , Akihide Sano , Yutaka Miyamoto , Eiji Yoshida
IPC分类号： H04L27/06 , H04L27/01
CPC分类号： H04L27/2672 , H04L25/03159 , H04L27/2633 , H04L27/265 , H04L27/266 , H04L2025/03414
摘要： A frequency domain multiplexed signal receiving method which decodes received signals that are multiplexed in a frequency domain, includes: a digital signal acquisition step of acquiring digital signals from the received signals that are multiplexed in the frequency domain; an offset discrete Fourier transform step of applying an offset discrete Fourier transform to odd discrete point numbers based on the acquired digital signals; and a decode step of decoding frequency domain digital signals in the frequency domain obtained by the offset discrete Fourier transform, and that are the frequency domain digital signals of one or more frequency channels.
摘要翻译：一种频域复用信号接收方法，对在频域中被复用的接收信号进行解码，包括：数字信号获取步骤，从在频域中复用的接收信号中获取数字信号; 偏移离散傅立叶变换步骤，基于所获取的数字信号将偏移离散付里叶变换应用于奇数离散点数; 以及解码步骤，对通过偏移离散付里叶变换获得的频域中的频域数字信号进行解码，并且其是一个或多个频率信道的频域数字信号。

18. 发明申请

US20110273317A1 CURRENT-SWITCHING CELL AND DIGITAL-TO-ANALOG CONVERTER 有权
标题翻译：电流切换单元和数字到模拟转换器
公开(公告)号：US20110273317A1
公开(公告)日：2011-11-10
申请号：US13145782
申请日：2010-01-28
申请人： Munehiko Nagatani , Hideyuki Nosaka , Shogo Yamanaka , Kimikazu Sano , Koichi Murata
发明人： Munehiko Nagatani , Hideyuki Nosaka , Shogo Yamanaka , Kimikazu Sano , Koichi Murata
IPC分类号： H03M1/66 , H03K17/60 , H03K17/687
CPC分类号： H03M1/662 , H03M1/742
摘要： Two D flip-flops (D-FFMA, D-FFMB) output two half-rate signals (DMR-A, DMR-B) by dividing a digital input signal (DM) into two signals and retiming them based on a clock signal (CLK) and a negative-phase clock signal (CLKB). First and second switches (SM1, SM2) are driven by the two half-rate signals (DMR-A, DMR-B). Third and fourth switches (SM3, SM4) are driven by a select signal SW and a negative-phase select signal SWB that have the same frequency as that of the clock signal TO (CLK) but a different phase from that of the clock signal (CLK). The current supplied from a current source (1) to a load (4) thus becomes a current signal corresponding to a conversion frequency twice the frequency of the clock signal (CLK).
摘要翻译：两个D触发器（D-FFMA，D-FFMB）通过将数字输入信号（DM）分成两个信号并基于时钟信号重新定时（DMR-A，D-FFMB）输出两个半速率信号 CLK）和负相位时钟信号（CLKB）。第一和第二开关（SM1，SM2）由两个半速率信号（DMR-A，DMR-B）驱动。第三和第四开关（SM3，SM4）由与时钟信号TO（CLK）的频率相同的频率的选择信号SW和负相位选择信号SWB驱动，但是与时钟信号 CLK）。因此，从电流源（1）提供给负载（4）的电流成为与时钟信号（CLK）的频率的两倍的转换频率相对应的电流信号。

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