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11. 发明授权

US07759763B2 Semiconductor device and a method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07759763B2
公开(公告)日：2010-07-20
申请号：US12116193
申请日：2008-05-06
申请人： Keiichi Yoshizumi , Kazuhisa Higuchi , Takayuki Nakaji , Masami Koketsu , Hideki Yasuoka
发明人： Keiichi Yoshizumi , Kazuhisa Higuchi , Takayuki Nakaji , Masami Koketsu , Hideki Yasuoka
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/82
CPC分类号： H01L27/0629 , H01L21/823462 , H01L21/823857 , H01L28/20 , H01L28/40
摘要： A semiconductor device which, in spite of the existence of a dummy active region, eliminates the need for a larger chip area and improves the surface flatness of the semiconductor substrate. In the process of manufacturing it, a thick gate insulating film for a high voltage MISFET is formed over an n-type buried layer as an active region and a resistance element IR of an internal circuit is formed over the gate insulating film. Since the thick gate insulating film lies between the n-type buried layer and the resistance element IR, the coupling capacitance produced between the substrate (n-type buried layer) and the resistance element IR is reduced.
摘要翻译：尽管存在虚拟有源区，半导体器件不需要更大的芯片面积并且提高半导体衬底的表面平坦度。在其制造过程中，在n型掩埋层上形成用于高电压MISFET的厚栅极绝缘膜作为有源区，并且在栅极绝缘膜上形成内部电路的电阻元件IR。由于厚栅极绝缘膜位于n型掩埋层和电阻元件IR之间，所以在衬底（n型掩埋层）和电阻元件IR之间产生的耦合电容减小。

12. 发明授权

US07592669B2 Semiconductor device with MISFET that includes embedded insulating film arranged between source/drain regions and channel 有权
标题翻译：具有MISFET的半导体器件包括布置在源极/漏极区域和沟道之间的嵌入绝缘膜
公开(公告)号：US07592669B2
公开(公告)日：2009-09-22
申请号：US11776380
申请日：2007-07-11
申请人： Hideki Yasuoka , Keiichi Yoshizumi , Masami Koketsu
发明人： Hideki Yasuoka , Keiichi Yoshizumi , Masami Koketsu
IPC分类号： H01L29/78
CPC分类号： H01L29/66659 , H01L21/76229 , H01L21/823412 , H01L21/823418 , H01L21/823481 , H01L29/0653 , H01L29/456 , H01L29/7835
摘要： With the objective of suppressing or preventing a kink effect in the operation of a semiconductor device having a high breakdown voltage field effect transistor, n+ type semiconductor regions, each having a conduction type opposite to p+ type semiconductor regions for a source and drain of a high breakdown voltage pMIS, are disposed in a boundary region between each of trench type isolation portions at both ends, in a gate width direction, of a channel region of the high breakdown voltage pMIS and a semiconductor substrate at positions spaced away from p− type semiconductor regions, each having a field relaxing function, of the high breakdown voltage pMIS, so as not to contact the p− type semiconductor regions (on the drain side, in particular). The n+ type semiconductor regions extend to positions deeper than the trench type isolation portions.
摘要翻译：为了抑制或防止在具有高击穿电压场效应晶体管的半导体器件的操作中的扭结效应的目的，n +型半导体区域具有与p +型半导体区域相反的导通类型，用于源极和漏极的高电压击穿电压pMIS设置在高击穿电压pMIS的沟道区域的两端，栅极宽度方向的沟槽型隔离部分之间的边界区域以及与p-型半导体隔开的位置处的半导体衬底具有高的击穿电压pMIS的场弛豫功能的区域，以便不与p型半导体区域（特别是在漏极侧）接触。 n +型半导体区域延伸到比沟槽型隔离部分更深的位置。

13. 发明授权

US07514749B2 Semiconductor device and a method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07514749B2
公开(公告)日：2009-04-07
申请号：US12122717
申请日：2008-05-18
申请人： Kunihiko Kato , Masami Koketsu , Shigeya Toyokawa , Keiichi Yoshizumi , Hideki Yasuoka , Yasuhiro Takeda
发明人： Kunihiko Kato , Masami Koketsu , Shigeya Toyokawa , Keiichi Yoshizumi , Hideki Yasuoka , Yasuhiro Takeda
IPC分类号： H01L23/62
CPC分类号： H01L21/823857 , H01L21/823814 , H01L21/823878 , H01L27/0629 , H01L28/40
摘要： A method of manufacturing a semiconductor integrated circuit device having on the same substrate both a high breakdown voltage MISFET and a low breakdown voltage MISFET is provided. An element isolation trench is formed in advance so that the width thereof is larger than the sum of the thickness of a polycrystalline silicon film serving as a gate electrode of a low breakdown voltage, the thickness of a gate insulating film and an alignment allowance in processing of a gate electrode in a direction orthogonal to the extending direction of the gate electrode and is larger than the thickness of the polycrystalline silicon film in a planar region not overlapping the gate electrode. It is possible to decrease the number of manufacturing steps for the semiconductor integrated circuit device.
摘要翻译：提供一种制造半导体集成电路器件的方法，该半导体集成电路器件在相同的衬底上具有高击穿电压MISFET和低击穿电压MISFET。预先形成元件隔离沟槽，使得其宽度大于用作低击穿电压的栅电极的多晶硅膜的厚度，栅绝缘膜的厚度和处理中的对准余量之和在与栅电极的延伸方向正交的方向上的栅电极大于不与栅电极重叠的平面区域中的多晶硅膜的厚度。可以减少半导体集成电路器件的制造步骤的数量。

14. 发明申请

US20080258236A1 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20080258236A1
公开(公告)日：2008-10-23
申请号：US11776380
申请日：2007-07-11
申请人： Hideki Yasuoka , Keiichi Yoshizumi , Masami Koketsu
发明人： Hideki Yasuoka , Keiichi Yoshizumi , Masami Koketsu
IPC分类号： H01L27/088
CPC分类号： H01L29/66659 , H01L21/76229 , H01L21/823412 , H01L21/823418 , H01L21/823481 , H01L29/0653 , H01L29/456 , H01L29/7835
摘要： With the objective of suppressing or preventing a kink effect in the operation of a semiconductor device having a high breakdown voltage field effect transistor, n+ type semiconductor regions, each having a conduction type opposite to p+ type semiconductor regions for a source and drain of a high breakdown voltage pMIS, are disposed in a boundary region between each of trench type isolation portions at both ends, in a gate width direction, of a channel region of the high breakdown voltage pMIS and a semiconductor substrate at positions spaced away from p− type semiconductor regions, each having a field relaxing function, of the high breakdown voltage pMIS, so as not to contact the p− type semiconductor regions (on the drain side, in particular). The n+ type semiconductor regions extend to positions deeper than the trench type isolation portions.
摘要翻译：为了抑制或防止具有高击穿电压场效应晶体管的半导体器件的操作中的扭结效应，n + +型半导体区域具有与p < 用于高击穿电压pMIS的源极和漏极的+ 型半导体区域设置在高频沟道区域的栅极宽度方向的两端的沟槽型隔离部分之间的边界区域中击穿电压pMIS和半导体衬底在高击穿电压pMIS的每个具有场弛豫功能的位置间隔开的位置处，以便不接触p型 - 型半导体区域（特别是在漏极侧）。 n + +型半导体区域延伸到比沟槽型隔离部分更深的位置。

15. 发明授权

US4616405A Semiconductor device and manufacturing method thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US4616405A
公开(公告)日：1986-10-14
申请号：US691061
申请日：1985-01-14
申请人： Hideki Yasuoka
发明人： Hideki Yasuoka
IPC分类号： H01L29/78 , H01L21/331 , H01L21/8249 , H01L27/06 , H01L29/06 , H01L29/08 , H01L29/73 , H01L29/735 , H01L21/90
CPC分类号： H01L27/0623 , H01L27/06 , H01L29/735 , Y10S148/01 , Y10S148/011
摘要： A semiconductor device which comprises a semiconductor area having one principal surface, an emitter area and a collector area formed selectively and apart each other on the principal surface of said semiconductor area, a base area formed on said one principal surface between the emittor area and the collector area, an insulating film formed on said base area, and a high fusing point metallic film formed on said insulating film and covering said base area.
摘要翻译：一种半导体器件，包括在所述半导体区域的主表面上选择性地且彼此分离形成的一个主表面，发射极区域和集电极区域的半导体区域，形成在所述发射体区域和所述发光体区域之间的所述一个主表面上的基极区域集电体区域，形成在所述基底区域上的绝缘膜，以及形成在所述绝缘膜上并覆盖所述基底区域的高熔点点金属膜。

16. 发明授权

US08169047B2 Semiconductor device comprising a schottky barrier diode 有权
标题翻译：包括肖特基势垒二极管的半导体器件
公开(公告)号：US08169047B2
公开(公告)日：2012-05-01
申请号：US12205622
申请日：2008-09-05
申请人： Kunihiko Kato , Hideki Yasuoka , Masatoshi Taya , Masami Koketsu
发明人： Kunihiko Kato , Hideki Yasuoka , Masatoshi Taya , Masami Koketsu
IPC分类号： H01L29/66
CPC分类号： H01L29/872 , H01L27/0629 , H01L29/0692 , H01L29/417
摘要： The present invention aims to enhance the reliability of a semiconductor device equipped with a Schottky barrier diode within the same chip, and its manufacturing technology. The semiconductor device includes an n-type n-well region formed over a p-type semiconductor substrate, an n-type cathode region formed in part thereof and higher in impurity concentration than the n-well region, a p-type guard ring region formed so as to surround the n-type cathode region, an anode conductor film formed so as to integrally cover the n-type cathode region and the p-type guard ring region and to be electrically coupled thereto, n-type cathode conduction regions formed outside the p-type guard ring region with each separation portion left therebetween, and a cathode conductor film formed so as to cover the n-type cathode conduction regions and to be electrically coupled thereto. The anode conductor film and the n-type cathode region are Schottky-coupled to each other.
摘要翻译：本发明旨在提高在同一芯片内配备肖特基势垒二极管的半导体器件及其制造技术的可靠性。半导体器件包括在p型半导体衬底上形成的n型n阱区，部分形成并且杂质浓度高于n阱区的n型阴极区，p型保护环区形成为包围n型阴极区域的阳极导体膜，形成为一体地覆盖n型阴极区域和p型保护环区域并与其电耦合，形成n型阴极导电区域在其间留有各个分离部分的p型保护环区域外部，以及形成为覆盖n型阴极导电区域并与其电耦合的阴极导体膜。阳极导体膜和n型阴极区彼此肖特基耦合。

17. 发明申请

US20100244137A1 SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100244137A1
公开(公告)日：2010-09-30
申请号：US12813144
申请日：2010-06-10
申请人： Keiichi YOSHIZUMI , Kazuhisa Higuchi , Takayuki Nakaji , Masami Koketsu , Hideki Yasuoka
发明人： Keiichi YOSHIZUMI , Kazuhisa Higuchi , Takayuki Nakaji , Masami Koketsu , Hideki Yasuoka
IPC分类号： H01L27/06 , H01L23/60
CPC分类号： H01L27/0629 , H01L21/823462 , H01L21/823857 , H01L28/20 , H01L28/40
摘要： A semiconductor device which, in spite of the existence of a dummy active region, eliminates the need for a larger chip area and improves the surface flatness of the semiconductor substrate. In the process of manufacturing it, a thick gate insulating film for a high voltage MISFET is formed over an n-type buried layer as an active region and a resistance element IR of an internal circuit is formed over the gate insulating film. Since the thick gate insulating film lies between the n-type buried layer and the resistance element IR, the coupling capacitance produced between the substrate (n-type buried layer) and the resistance element IR is reduced.
摘要翻译：尽管存在虚拟有源区，半导体器件不需要更大的芯片面积并且提高半导体衬底的表面平坦度。在其制造过程中，在n型掩埋层上形成用于高电压MISFET的厚栅极绝缘膜作为有源区，并且在栅极绝缘膜上形成内部电路的电阻元件IR。由于厚栅极绝缘膜位于n型掩埋层和电阻元件IR之间，所以在衬底（n型掩埋层）和电阻元件IR之间产生的耦合电容减小。

18. 发明授权

US07393737B2 Semiconductor device and a method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07393737B2
公开(公告)日：2008-07-01
申请号：US11500381
申请日：2006-08-08
申请人： Keiichi Yoshizumi , Kazuhisa Higuchi , Takayuki Nakaji , Masami Koketsu , Hideki Yasuoka
发明人： Keiichi Yoshizumi , Kazuhisa Higuchi , Takayuki Nakaji , Masami Koketsu , Hideki Yasuoka
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/82
CPC分类号： H01L27/0629 , H01L21/823462 , H01L21/823857 , H01L28/20 , H01L28/40
摘要： A semiconductor device which, in spite of the existence of a dummy active region, eliminates the need for a larger chip area and improves the surface flatness of the semiconductor substrate. In the process of manufacturing it, a thick gate insulating film for a high voltage MISFET is formed over an n-type buried layer as an active region and a resistance element IR of an internal circuit is formed over the gate insulating film. Since the thick gate insulating film lies between the n-type buried layer and the resistance element IR, the coupling capacitance produced between the substrate (n-type buried layer) and the resistance element IR is reduced.
摘要翻译：尽管存在虚拟有源区，半导体器件不需要更大的芯片面积并且提高半导体衬底的表面平坦度。在其制造过程中，在n型掩埋层上形成用于高电压MISFET的厚栅极绝缘膜作为有源区，并且在栅极绝缘膜上形成内部电路的电阻元件IR。由于厚栅极绝缘膜位于n型掩埋层和电阻元件IR之间，所以在衬底（n型掩埋层）和电阻元件IR之间产生的耦合电容减小。

19. 发明授权

US07064090B2 Method of manufacturing a semiconductor integrated circuit device 失效
标题翻译：制造半导体集成电路器件的方法
公开(公告)号：US07064090B2
公开(公告)日：2006-06-20
申请号：US10942860
申请日：2004-09-17
申请人： Shinichi Minami , Yoshiaki Kamigaki , Hideki Yasuoka , Fukuo Owada
发明人： Shinichi Minami , Yoshiaki Kamigaki , Hideki Yasuoka , Fukuo Owada
IPC分类号： H01L21/00
CPC分类号： H01L27/11526 , H01L27/0629 , H01L27/105 , H01L27/1052 , H01L27/11521 , H01L27/11546 , Y10S438/983
摘要： A manufacturing technique for a zener diode which includes forming a first semiconductor region in a region such as a well region at a primary face of a semiconductor substrate and then forming a second semiconductor region of opposite conductivity type thereover. The second semiconductor region covers an area greater than the underlying first semiconductor region. The method further calls for forming an insulating film on the primary face of the substrate followed by the forming connection holes in the insulating film to expose an upper part of the second semiconductor region located outside the area covered by the junction affected between the first and second semiconductor regions. This is followed by the formation of a wire at the upper part of the insulating film in which an electrical connection is affected between the wire and the second semiconductor region through the plural connection holes which are distributively arranged.
摘要翻译：一种用于齐纳二极管的制造技术，其包括在半导体衬底的初级面的诸如阱区域的区域中形成第一半导体区域，然后在其上形成相反导电类型的第二半导体区域。第二半导体区域覆盖大于下面的第一半导体区域的面积。该方法还要求在衬底的主面上形成绝缘膜，然后在绝缘膜中形成连接孔，以暴露第二半导体区域的上部，该第二半导体区域的上部位于由第一和第二半导体区域。接着在绝缘膜的上部形成通过分布布置的多个连接孔在电线和第二半导体区域之间形成电连接的导线。

20. 发明申请

US20050104098A1 Method of manufacturing a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20050104098A1
公开(公告)日：2005-05-19
申请号：US10986896
申请日：2004-11-15
申请人： Hideki Yasuoka , Keiichi Yoshizumi , Masami Koketsu
发明人： Hideki Yasuoka , Keiichi Yoshizumi , Masami Koketsu
IPC分类号： H01L21/76 , H01L21/336 , H01L21/762 , H01L21/8234 , H01L21/8238 , H01L27/04 , H01L27/08 , H01L27/092 , H01L29/45 , H01L29/78 , H01L27/01 , H01L29/94 , H01L31/0392
CPC分类号： H01L29/66659 , H01L21/76229 , H01L21/823412 , H01L21/823418 , H01L21/823481 , H01L29/0653 , H01L29/456 , H01L29/7835
摘要： With the objective of suppressing or preventing a kink effect in the operation of a semiconductor device having a high breakdown voltage field effect transistor, n+ type semiconductor regions, each having a conduction type opposite to p+ type semiconductor regions for a source and drain of a high breakdown voltage pMIS, are disposed in a boundary region between each of trench type isolation portions at both ends, in a gate width direction, of a channel region of the high breakdown voltage pMIS and a semiconductor substrate at positions aced away from p− type semiconductor regions, each having a field relaxing function, of the high breakdown voltage pMIS, so as not to contact the p− type semiconductor regions (on the drain sides in particular). The n+ type semiconductor regions extend to positions deeper than the trench type isolation portions.
摘要翻译：为了抑制或防止具有高击穿电压场效应晶体管的半导体器件的操作中的扭结效应，n + +型半导体区域具有与p < 用于高击穿电压pMIS的源极和漏极的+ 型半导体区域设置在高频沟道区域的栅极宽度方向的两端的沟槽型隔离部分之间的边界区域中击穿电压pMIS和半导体衬底在远离p型 - 半导体区域的位置处，每个具有高的击穿电压pMIS的场弛豫功能，以便不接触p型 - 型半导体区域（特别是在漏极侧）。 n + +型半导体区域延伸到比沟槽型隔离部分更深的位置。

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