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    • 15. 发明授权
    • Method for countervailing clock skew and core logic circuit using the same
    • 反向时钟偏移的方法和使用其的核心逻辑电路
    • US08397098B2
    • 2013-03-12
    • US11923192
    • 2007-10-24
    • Paul Su
    • Paul Su
    • G06F1/12G06F11/00H03D13/00
    • G06F1/12
    • A method for countervailing clock skew between a first clock signal and a second clock signal in a core logic circuit. The second clock signal is sampled based on the first clock signal in a sampling cycle to obtain a sampling result. When the sampling result indicates a non-compliant pattern, the phase of at least one of the first clock signal and the second clock signal is adjusted. Desirably, the core logic circuit keeps on working with the current first and second clock signals while continuing the sampling procedure of the second clock signal based on the first clock signal when the sampling result indicates a compliant pattern.
    • 一种用于在核心逻辑电路中抵消第一时钟信号和第二时钟信号之间的时钟偏移的方法。 基于采样周期中的第一时钟信号对第二时钟信号进行采样以获得采样结果。 当采样结果指示不兼容模式时,调整第一时钟信号和第二时钟信号中的至少一个的相位。 理想地,当采样结果指示顺从模式时,核心逻辑电路继续使用当前的第一和第二时钟信号,同时基于第一时钟信号继续第二时钟信号的采样过程。