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11. 发明申请

US20100023900A1 ANALYSIS OF STRESS IMPACT ON TRANSISTOR PERFORMANCE 有权
公开(公告)号：US20100023900A1
公开(公告)日：2010-01-28
申请号：US12510185
申请日：2009-07-27
申请人： Victor Moroz , Dipankar Pramanik
发明人： Victor Moroz , Dipankar Pramanik
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5022 , G06F17/5081
摘要： Roughly described, a method for approximating stress-induced mobility enhancement in a channel region in an integrated circuit layout, including approximating the stress at each of a plurality of sample points in the channel, converting the stress approximation at each of the sample points to a respective mobility enhancement value, and averaging the mobility enhancement values at all the sample points. The method enables integrated circuit stress analysis that takes into account stresses contributed by multiple stress generation mechanisms, stresses having vector components other than along the length of the channel, and stress contributions (including mitigations) due to the presence of other structures in the neighborhood of the channel region under study, other than the nearest STI interfaces. The method also enables stress analysis of large layout regions and even full-chip layouts, without incurring the computation costs of a full TCAD simulation.

12. 发明申请

US20100019317A1 Managing Integrated Circuit Stress Using Stress Adjustment Trenches 审中-公开
标题翻译：使用应力调整沟槽管理集成电路应力
公开(公告)号：US20100019317A1
公开(公告)日：2010-01-28
申请号：US12573308
申请日：2009-10-05
申请人： Victor Moroz , Dipankar Pramanik , Xi-Wei Lin
发明人： Victor Moroz , Dipankar Pramanik , Xi-Wei Lin
IPC分类号： H01L29/78 , H01L29/06
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L29/7846 , H01L29/7848
摘要： Roughly described, methods and systems for improving integrated circuit layouts and fabrication processes in order to better account for stress effects. Dummy features can be added to a layout either in order to improve uniformity, or to relax known undesirable stress, or to introduce known desirable stress. The dummy features can include dummy diffusion regions added to relax stress, and dummy trenches added either to relax or enhance stress. A trench can relax stress by filling it with a stress-neutral material or a tensile strained material. A trench can increase stress by filling it with a compressive strained material. Preferably dummy diffusion regions and stress relaxation trenches are disposed longitudinally to at least the channel regions of N-channel transistors, and transversely to at least the channel regions of both N-channel and P-channel transistors. Preferably stress enhancement trenches are disposed longitudinally to at least the channel regions of P-channel transistors.
摘要翻译：大致描述了改进集成电路布局和制造工艺的方法和系统，以便更好地解决应力影响。为了改善均匀性或放松已知的不良应力或引入已知的所需应力，可将虚拟特征添加到布局中。虚拟特征可以包括添加以放松应力的虚拟扩散区域，并且添加虚拟沟槽以放松或增强应力。沟槽可以通过用应力中性材料或拉伸应变材料填充来缓解应力。沟槽可以通过用压缩应变材料填充来增加应力。优选地，虚拟扩散区域和应力松弛沟槽纵向设置在N沟道晶体管的至少沟道区域上，并横向于N沟道和P沟道晶体管的至少沟道区域。优选地，应力增强沟槽纵向设置在至少P沟道晶体管的沟道区域上。

13. 发明申请

US20090307649A1 SYSTEM AND METHOD FOR MODIFYING A DATA SET OF A PHOTOMASK 有权
标题翻译：用于修改光电子数据集的系统和方法
公开(公告)号：US20090307649A1
公开(公告)日：2009-12-10
申请号：US12136277
申请日：2008-06-10
申请人： Dipankar Pramanik , Michiel Victor Paul Kruger , Roy V. Prasad , Abdurrahman Sezginer
发明人： Dipankar Pramanik , Michiel Victor Paul Kruger , Roy V. Prasad , Abdurrahman Sezginer
IPC分类号： G06F17/50
CPC分类号： G06F17/50 , G03F1/144 , G03F1/36
摘要： The present invention provides a method for compensating, infidelities of a process that transfers a pattern to a layer of an integrated circuit, by minimizing, with respect to a photomask pattern, a cost function that quantifies the deviation between designed and simulated values of circuit parameters of the pattern formed on a semiconductor wafer.
摘要翻译：本发明提供了一种用于通过使关于光掩模图案最小化量化电路参数的设计值和模拟值之间的偏差的成本函数来补偿将图案转移到集成电路层的过程的不忠形成在半导体晶片上的图案。

14. 发明申请

US20090113368A1 FILLER CELLS FOR DESIGN OPTIMIZATION IN A PLACE-AND-ROUTE SYSTEM 有权
标题翻译：用于设计优化的填充电池在路线和路线系统中
公开(公告)号：US20090113368A1
公开(公告)日：2009-04-30
申请号：US11924738
申请日：2007-10-26
申请人： Xi-Wei Lin , Jyh-Chwen Frank Lee , Dipankar Pramanik
发明人： Xi-Wei Lin , Jyh-Chwen Frank Lee , Dipankar Pramanik
IPC分类号： G06F17/50
CPC分类号： G06F17/50 , G06F17/5068 , H01L27/0207
摘要： A system and method are provided for laying out an integrated circuit design into a plurality of circuit layout cells having gaps therebetween, and inserting into each given one of at least a subset of the gaps, a corresponding filler cell selected from a predefined database in dependence upon a desired effect on a performance parameter of at least one circuit cell adjacent to the given gap. The circuit layout cells may be arranged in rows, and in some embodiments the selection of an appropriate filler cell for a given gap depends upon effects desired on a performance parameter of both circuit cells adjacent to the given gap. The predefined filler cells can include, for example, dummy diffusion regions, dummy poly lines, N-well boundary shifts and etch stop layer boundary shifts. In an embodiment, circuit layout cells can be moved in order to accommodate a selected filler cell.
摘要翻译：提供了一种系统和方法，用于将集成电路设计布置成具有间隙的多个电路布局单元，并且将至少一个子空间中的每个给定的一个插入到依赖于预定数据库的相应填充单元对所述给定间隙相邻的至少一个电路单元的性能参数产生期望的影响。电路布局单元可以排成行，并且在一些实施例中，用于给定间隙的适当填充单元的选择取决于与给定间隙相邻的两个电路单元的性能参数所期望的效果。预定义的填充单元可以包括例如虚拟扩散区域，虚拟多线，N阱边界位移和蚀刻停止层边界移位。在一个实施例中，可以移动电路布局单元以便容纳选定的填充单元。

15. 发明申请

US20080297237A1 METHOD FOR COMPENSATION OF PROCESS-INDUCED PERFORMANCE VARIATION IN A MOSFET INTEGRATED CIRCUIT 有权
标题翻译： MOSFET集成电路中过程诱导性能变化补偿的方法
公开(公告)号：US20080297237A1
公开(公告)日：2008-12-04
申请号：US11757338
申请日：2007-06-01
申请人： Victor Moroz , Dipankar Pramanik , Kishore Singhal , Xi-Wei Lin
发明人： Victor Moroz , Dipankar Pramanik , Kishore Singhal , Xi-Wei Lin
IPC分类号： G05F3/02
CPC分类号： G06F17/5068 , G06F17/5036
摘要： An automated method for compensating for process-induced variations in threshold voltage and drive current in a MOSFET integrated circuit. The method's first step is selecting a transistor for analysis from the array. The method loops among the transistors of the array as desired. Next the design of the selected transistor is analyzed, including the steps of determining threshold voltage variations induced by layout neighborhood; determining drive current variations induced by layout neighborhood. The method then proceeds by attempting to compensate for any determined variations by varying the length of the transistor gate. The method can further include the step of identifying any shortcoming in compensation by varying contact spacing.
摘要翻译：用于补偿MOSFET集成电路中阈值电压和驱动电流的过程引起的变化的自动化方法。该方法的第一步是从阵列中选择一个用于分析的晶体管。该方法根据需要在阵列的晶体管之间循环。接下来分析所选择的晶体管的设计，包括确定由布局邻域引起的阈值电压变化的步骤; 确定由布局邻域引起的驱动电流变化。该方法然后通过改变晶体管栅极的长度来尝试补偿任何确定的变化。该方法还可以包括通过改变接触间距来识别补偿中的任何缺点的步骤。

16. 发明申请

US20080066023A1 METHOD AND APPARATUS FOR FAST IDENTIFICATION OF HIGH STRESS REGIONS IN INTEGRATED CIRCUIT STRUCTURE 有权
标题翻译：集成电路结构中高应力区域快速识别的方法与装置
公开(公告)号：US20080066023A1
公开(公告)日：2008-03-13
申请号：US11530372
申请日：2006-09-08
申请人： Xiaopeng Xu , Dipankar Pramanik
发明人： Xiaopeng Xu , Dipankar Pramanik
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5018
摘要： Roughly described, high-stress volumetric regions of an integrated circuit structure are predicted by first scanning one or more layout layers to identify planar regions of high 2-dimensional stress, and then performing the much more expensive 3-dimensional stress analysis only on volumetric regions corresponding to those planar regions that were found to have high 2-dimensional stress. A windowing method can be used for the 2-dimensional scan, optionally with an overlap region extending slightly into adjacent windows. Very narrow features arising at the edges of an analysis window can be relocated to the edge of the analysis window in order to avoid numerical artifacts.
摘要翻译：粗略描述，通过首先扫描一个或多个布局层以识别高二维应力的平面区域，然后仅对体积区域执行更昂贵的三维应力分析来预测集成电路结构的高应力体积区域对应于被发现具有高二维应力的那些平面区域。可以使用开窗方法进行二维扫描，可选地具有稍微延伸到相邻窗口中的重叠区域。在分析窗口边缘出现的非常窄的特征可以重新定位到分析窗口的边缘，以避免数字瑕疵。

17. 发明申请

US20070202652A1 Elevation of transistor channels to reduce impact of shallow trench isolation on transistor performance 有权
标题翻译：提高晶体管通道，减少浅沟槽隔离对晶体管性能的影响
公开(公告)号：US20070202652A1
公开(公告)日：2007-08-30
申请号：US11364391
申请日：2006-02-27
申请人： Victor Moroz , Dipankar Pramanik , Xi-Wei Lin
发明人： Victor Moroz , Dipankar Pramanik , Xi-Wei Lin
IPC分类号： H01L21/336
CPC分类号： H01L21/823807 , H01L21/823878 , H01L29/7846
摘要： Roughly described, transistor channel regions are elevated over the level of certain adjacent STI regions. Preferably the STI regions that are transversely adjacent to the diffusion regions are suppressed, as are STI regions that are longitudinally adjacent to N-channel diffusion regions. Preferably STI regions that are longitudinally adjacent to P-channel diffusions are not suppressed; preferably they have an elevation that is at least as high as that of the diffusion regions.
摘要翻译：粗略描述，晶体管沟道区域在某些相邻STI区域的水平上升高。优选地，与扩散区横向相邻的STI区域被抑制，与N沟道扩散区域纵向相邻的STI区也是如此。优选地，与P沟道扩散纵向相邻的STI区域不被抑制; 优选地，它们具有至少与扩散区域相同的高度。

18. 发明授权

US5496774A Method improving integrated circuit planarization during etchback 失效
公开(公告)号：US5496774A
公开(公告)日：1996-03-05
申请号：US363062
申请日：1994-12-21
申请人： Dipankar Pramanik , Vivek Jain , Milind G. Weling
发明人： Dipankar Pramanik , Vivek Jain , Milind G. Weling
IPC分类号： H01L21/768 , H01L21/44
CPC分类号： H01L21/76819
摘要： An integrated circuit fabrication method begins with semiconductor devices formed on a substrate. A patterned metal layer is deposited on the substrate to connect the semiconductor devices. A nitride layer is deposited over the metal layer and substrate. The nitride layer topography comprises hills located over metal regions and valleys located over non-metal regions. Spin-on-glass (SOG) is deposited over the nitride layer, thereby filling the valleys and covering the hills. The SOG layer and the nitride layer hills are etched back at substantially the same etch rate, using plasma etching, to form a planar surface. An oxide layer is then deposited over the planar surface to encapsulate the semiconductor devices, metal layer, nitride layer and SOG layer. Vias may then be etched through the oxide layer and the nitride layer to expose portions of the underlying metal layer and facilitate upper layer metal connections thereto. A second metal layer is deposited on the oxide layer and the fabrication process continues until the integrated circuit is complete.

19. 发明授权

US5374833A Structure for suppression of field inversion caused by charge build-up in the dielectric 失效
标题翻译：用于抑制由电介质中的电荷积聚引起的场反转的结构
公开(公告)号：US5374833A
公开(公告)日：1994-12-20
申请号：US775085
申请日：1991-10-11
申请人： Subhash R. Nariani , Vivek Jain , Dipankar Pramanik , Kuang-Yeh Chang
发明人： Subhash R. Nariani , Vivek Jain , Dipankar Pramanik , Kuang-Yeh Chang
IPC分类号： H01L21/76 , H01L21/314 , H01L21/316 , H01L23/29 , H01L23/532 , H01L27/115 , H02L45/00
CPC分类号： H01L23/291 , H01L21/314 , H01L23/298 , H01L23/5329 , H01L27/115 , H01L2924/0002 , Y10S438/91 , Y10S438/958
摘要： The invention relates to an integrated circuit including one or more amorphous silicon layers for neutralizing charges which occur in various dielectric layers during fabrication. The amorphous silicon layers include dangling silicon bonds which neutralize charges which would otherwise cause isolation breakdown, impair integrated circuit performance and increase manufacturing costs.
摘要翻译：本发明涉及一种集成电路，其包括用于中和在制造期间在各种介电层中发生的电荷的一个或多个非晶硅层。非晶硅层包括悬挂硅键，其中和电荷，否则将导致隔离击穿，损害集成电路性能并增加制造成本。

20. 发明授权

US08881073B1 Analysis of stress impact on transistor performance 有权
公开(公告)号：US08881073B1
公开(公告)日：2014-11-04
申请号：US13850133
申请日：2013-03-25
申请人： Victor Moroz , Dipankar Pramanik
发明人： Victor Moroz , Dipankar Pramanik
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5036 , G06F17/5022 , G06F17/5081
摘要： Roughly described, a method for approximating stress-induced mobility enhancement in a channel region in an integrated circuit layout, including approximating the stress at each of a plurality of sample points in the channel, converting the stress approximation at each of the sample points to a respective mobility enhancement value, and averaging the mobility enhancement values at all the sample points. The method enables integrated circuit stress analysis that takes into account stresses contributed by multiple stress generation mechanisms, stresses having vector components other than along the length of the channel, and stress contributions (including mitigations) due to the presence of other structures in the neighborhood of the channel region under study, other than the nearest STI interfaces. The method also enables stress analysis of large layout regions and even full-chip layouts, without incurring the computation costs of a full TCAD simulation.

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