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    • 14. 发明申请
    • ULTRA-WIDEBAND VARIABLE-PHASE RING-OSCILLATOR ARRAYS, ARCHITECTURES, AND RELATED METHODS
    • 超宽带可变振荡器振荡器阵列,结构和相关方法
    • US20080297414A1
    • 2008-12-04
    • US12131805
    • 2008-06-02
    • Harish KrishnaswamyHossein Hashemi
    • Harish KrishnaswamyHossein Hashemi
    • H01Q3/00H03L7/00
    • H01Q3/28H01Q3/36H03L7/087H03L7/0891H03L7/0995
    • Variable phase ring oscillators are described that provide a linear phase progression between adjacent elements in an antenna array by providing a symmetric ring configuration of tuned amplifiers and a single phase shifter. The ring topology is coupled to a single PLL that allows for direct modulation and demodulation of arbitrary waveforms without using RF up/down converting mixers. The PLL distributes the transmit waveforms to all antenna elements in the transmit mode and combines the received waveforms in the receive mode without any complicated power distribution network. Ultra-wideband architectures and methods are described that utilize a first reference signal source, a VPRO, and a second reference signal source. Related methods are controlling an array and beam steering are also described.
    • 描述了可变相位振荡器,其通过提供调谐放大器和单个移相器的对称环配置来在天线阵列中的相邻元件之间提供线性相位进程。 环形拓扑耦合到单个PLL,允许直接调制和解调任意波形,而无需使用RF上/下转换混频器。 PLL将发射波形分配给发射模式下的所有天线元件,并将接收的波形组合在接收模式中,无需任何复杂的配电网络。 描述了利用第一参考信号源,VPRO和第二参考信号源的超宽带架构和方法。 还描述了相关方法控制阵列和波束转向。
    • 19. 发明申请
    • CIRCUITS AND METHODS FOR WIRELESS TRANSMITTERS
    • 无线发射机的电路和方法
    • US20160099820A1
    • 2016-04-07
    • US14873177
    • 2015-10-01
    • Anandaroop ChakrabartiHarish Krishnaswamy
    • Anandaroop ChakrabartiHarish Krishnaswamy
    • H04L25/03H03K3/013H03G3/30
    • H03M1/66H03G3/001H03G3/3036H03M1/745H03M1/78H04L25/03878H04L27/00
    • Circuits comprising: digital-to-amplitude converter (DAC), comprising: binary weighted switching transistors (BWSTs), each having gate coupled to amplitude control bit ACB, and wherein the drain of each of the BWSTs are connected together and wherein the source of each of the BWSTs are connected together; transistor M1 having gate coupled to input signal and first bias voltage BV1 and source coupled to the drains of the BWSTs; transistor M2 having gate coupled to BV2 and source coupled to the drain of M1; transistor M3 having gate coupled to BV3 and source coupled to the drain of M2; transistor having gate coupled to BV4, source coupled to the drain of M3; and inverter having input coupled to another ACB and having output coupled to the output of the DAC and the drain of M4.
    • 电路包括:数字到幅度转换器(DAC),包括:二进制加权开关晶体管(BWST),每个具有耦合到幅度控制位ACB的栅极,并且其中每个BWST的漏极连接在一起,并且其中源 每个BWST都连接在一起; 晶体管M1具有耦合到输入信号的栅极和第一偏置电压BV1,并且源极耦合到BWST的漏极; 晶体管M2具有耦合到BV2的栅极并且耦合到M1的漏极的源极; 具有耦合到BV3的栅极和耦合到M2的漏极的源极的晶体管M3; 晶体管具有耦合到BV4的栅极,源极耦合到M3的漏极; 以及反相器具有耦合到另一个ACB并具有耦合到DAC的输出和M4的漏极的输出的输入。