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    • 11. 发明授权
    • Digital duty cycle correction circuit and method for multi-phase clock
    • 数字占空比校正电路及多相时钟方法
    • US06958639B2
    • 2005-10-25
    • US10774398
    • 2004-02-10
    • Hong June ParkYoung Chan JangSeung Jun Bae
    • Hong June ParkYoung Chan JangSeung Jun Bae
    • H03K5/00H03K3/017H03K5/156
    • H03K5/1565
    • Provided is a digital duty cycle correction circuit and method for a multi-phase clock, in which duty cycle correction information of an input clock signal is stored in a power save state of a system by adopting a digital correction method in a duty cycle correction method for a multi-phase clock and phase information of the input clock signal is held constant during duty cycle correction of the input clock signal by correcting duty cycles of the input clock signal by changing the falling edge of the clock without changing the rising edge of the input clock signal during duty cycle correction of the input clock signal, thereby correcting the multi-phase clock. To this end, the digital duty cycle correction circuit includes a clock delay means that takes the form of a shunt capacitor-inverter, a clock generation means including a clock rising edge generation circuit and a clock falling edge generation circuit, and a digital duty cycle detection means including integrators, a comparator, and a counter/register.
    • 提供了一种用于多相时钟的数字占空比校正电路和方法,其中输入时钟信号的占空比校正信息在占空比校正方法中采用数字校正方法存储在系统的省电状态 对于多相时钟,输入时钟信号的相位信息在输入时钟信号的占空比校正期间通过在不改变时钟信号的上升沿的情况下改变时钟信号的下降沿来校正输入时钟信号的占空比来保持恒定 在输入时钟信号的占空比校正期间输入时钟信号,从而校正多相时钟。 为此,数字占空比校正电路包括采用并联电容器 - 反相器形式的时钟延迟装置,包括时钟上升沿产生电路和时钟下降沿产生电路的时钟产生装置和数字占空比 检测装置包括积分器,比较器和计数器/寄存器。