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11. 发明授权

US07454590B2 Multithreaded processor having a source processor core to subsequently delay continued processing of demap operation until responses are received from each of remaining processor cores 有权
标题翻译：具有源处理器核心的多线程处理器随后延迟解映射操作的持续处理，直到从每个剩余处理器核心接收到响应
公开(公告)号：US07454590B2
公开(公告)日：2008-11-18
申请号：US11222614
申请日：2005-09-09
申请人： Paul J. Jordan , Manish K. Shah , Gregory F. Grohoski
发明人： Paul J. Jordan , Manish K. Shah , Gregory F. Grohoski
IPC分类号： G06F12/08
CPC分类号： G06F12/1027 , G06F2212/682 , G06F2212/683
摘要： In one embodiment, a processor comprises a plurality of processor cores and an interconnect to which the plurality of processor cores are coupled. Each of the plurality of processor cores comprises at least one translation lookaside buffer (TLB). A first processor core is configured to broadcast a demap command on the interconnect responsive to executing a demap operation. The demap command identifies one or more translations to be invalidated in the TLBs, and remaining processor cores are configured to invalidate the translations in the respective TLBs. The remaining processor cores transmit a response to the first processor core, and the first processor core is configured to delay continued processing subsequent to the demap operation until the responses are received from each of the remaining processor cores.
摘要翻译：在一个实施例中，处理器包括多个处理器核和多个处理器核耦合到的互连。多个处理器核心中的每一个包括至少一个平移后备缓冲器（TLB）。第一处理器核心被配置为响应于执行解映射操作而在互连上广播解映射命令。解映射命令标识在TLB中将被无效的一个或多个翻译，并且剩余的处理器核被配置为使相应TLB中的翻译无效。剩余的处理器核心向第一处理器核心发送响应，并且第一处理器核心被配置为延迟解映射操作之后的持续处理，直到从每个其余处理器核心接收到响应。

12. 发明授权

US07383415B2 Hardware demapping of TLBs shared by multiple threads 有权
标题翻译：由多个线程共享的TLB的硬件解映射
公开(公告)号：US07383415B2
公开(公告)日：2008-06-03
申请号：US11222577
申请日：2005-09-09
申请人： Paul J. Jordan , Manish K. Shah , Gregory F. Grohoski
发明人： Paul J. Jordan , Manish K. Shah , Gregory F. Grohoski
IPC分类号： G06F12/08
CPC分类号： G06F12/1054 , G06F12/1027 , G06F12/109 , G06F2212/656 , G06F2212/682 , G06F2212/683
摘要： In one embodiment, a processor comprising at least one translation lookaside buffer (TLB) and a control unit coupled to the TLB. The control unit is configured to track whether or not at least one update to the TLB is pending for at least one of a plurality of strands. Each strand comprises hardware to support a different thread of a plurality of concurrently activateable threads in the processor. The strands share the TLB, and the control unit is configured to delay a demap operation issued from one of the estrands responsive to the pending update, if any.
摘要翻译：在一个实施例中，处理器包括至少一个翻译后备缓冲器（TLB）和耦合到该TLB的控制单元。控制单元被配置为跟踪针对多个线段中的至少一个的至少一个对TLB的更新是否待决。每条链包括用于支持处理器中多个可同时激活的线程的不同线程的硬件。链路共享TLB，并且控制单元被配置为响应于待决更新（如果有的话）延迟从一个estrand发出的解映射操作。

13. 发明授权

US08190864B1 APIC implementation for a highly-threaded x86 processor 有权
标题翻译：高性能x86处理器的APIC实现
公开(公告)号：US08190864B1
公开(公告)日：2012-05-29
申请号：US11924491
申请日：2007-10-25
申请人： Paul J. Jordan , Gregory F. Grohoski
发明人： Paul J. Jordan , Gregory F. Grohoski
IPC分类号： G06F9/00
CPC分类号： G06F9/4818
摘要： Advanced programmable interrupt control for a multithreaded multicore processor that supports software compatible with x86 processors. Embodiments provide interrupt control for increased threads with minimal additional hardware by including in each processor core, a core advanced interrupt controller (core APIC) configured to determine a lowest priority thread of its corresponding processor core. Each core APIC reports its lowest priority thread level as a core priority to an input/output APIC. The I/O APIC routes interrupt requests to the core APIC with the lowest core priority. The selected core APIC then routes the interrupt request to the corresponding lowest priority thread. Each core APIC detects changes in priority levels of its corresponding processor core threads, and notifies the I/O APIC of any change to the corresponding core priority. Each core APIC may notify the I/O APIC as the core priority changes, or when the I/O APIC requests status from each core APIC.
摘要翻译：用于支持与x86处理器兼容的软件的多线程多核处理器的高级可编程中断控制。实施例通过在每个处理器核心中包括被配置为确定其对应的处理器核心的最低优先级线程的核心高级中断控制器（核心APIC）来提供具有最小附加硬件的增加的线程的中断控制。每个核心APIC报告其最低优先级线程级别作为输入/输出APIC的核心优先级。 I / O APIC将核心优先级最低的核心APIC路由中断请求。所选的核心APIC然后将中断请求路由到相应的最低优先级线程。每个核心APIC检测其对应的处理器核心线程的优先级别的变化，并将I / O APIC通知相应的核心优先级的任何更改。当核心优先级改变时，或者当I / O APIC从每个核心APIC请求状态时，每个核心APIC可以通知I / O APIC。

14. 发明授权

US07392399B2 Methods and systems for efficiently integrating a cryptographic co-processor 有权
标题翻译：用于有效集成加密协处理器的方法和系统
公开(公告)号：US07392399B2
公开(公告)日：2008-06-24
申请号：US10430614
申请日：2003-05-05
申请人： Gregory F. Grohoski , Paul J. Jordan , Michael K. Wong , Leslie D. Kohn
发明人： Gregory F. Grohoski , Paul J. Jordan , Michael K. Wong , Leslie D. Kohn
IPC分类号： G06F11/30 , G06F12/14 , H04L9/32
CPC分类号： H04L63/0485 , G06F9/3879 , G06F21/72 , H04L63/164 , H04L63/166
摘要： A method and system of processing a cryptographic packet includes receiving a first cryptographic packet in a host CPU. A first set of data required to execute the first cryptographic packet is identified. The first cryptographic packet and the required first set of data is transferred to a cryptographic co-processor. The first cryptographic packet is executed in the cryptographic co-processor. The host CPU is notified that the execution of the first cryptographic packet is complete. The executed first cryptographic packet is received in the host CPU.
摘要翻译：处理加密分组的方法和系统包括在主机CPU中接收第一密码分组。识别执行第一密码分组所需的第一组数据。第一密码分组和所需的第一组数据被传送到密码协处理器。第一密码分组在密码协处理器中执行。通知主机CPU完成第一密码分组的执行。在主机CPU中接收执行的第一密码分组。

15. 发明授权

US07370243B1 Precise error handling in a fine grain multithreaded multicore processor 有权
标题翻译：精细多线程多核处理器中的精确错误处理
公开(公告)号：US07370243B1
公开(公告)日：2008-05-06
申请号：US10881111
申请日：2004-06-30
申请人： Gregory F. Grohoski , Ricky C. Hetherington , Paul J. Jordan , Robert M. Maier
发明人： Gregory F. Grohoski , Ricky C. Hetherington , Paul J. Jordan , Robert M. Maier
IPC分类号： G06F11/00
CPC分类号： G06F11/0772 , G06F9/3851 , G06F9/3865 , G06F9/3891 , G06F11/0721 , G06F11/0724 , G06F11/0781
摘要： A method and mechanism for error recovery in a processor. A multithreaded processor is configured to utilize software for hardware detected machine errors. Rather than correcting and clearing the detected errors, hardware is configured to report the errors precisely. Both program-related exceptions and hardware errors are detected and, without being corrected by the hardware, flow down the pipeline to a trap unit where they are prioritized and handled via software. The processor assigns each instruction a thread ID and error information as it follows the pipeline. The trap unit records the error by using the thread ID of the instruction and the pipelined error information in order to determine which ESR receives the information and what to store in the ESR. A trap handling routine is then initiated to facilitate error recovery.
摘要翻译：一种处理器中错误恢复的方法和机制。多线程处理器配置为利用软件检测到机器错误。硬件不是纠正和清除检测到的错误，而是配置为精确地报告错误。检测到与程序相关的异常和硬件错误，并且在不被硬件校正的情况下，将流水线下流到陷阱单元，并通过软件进行优先处理。处理器为每个指令分配线程ID和错误信息，因为它遵循流水线。陷阱单元通过使用指令的线程ID和流水线错误信息记录错误，以确定哪个ESR接收信息以及在ESR中存储的内容。然后启动陷阱处理例程以促进错误恢复。

16. 发明授权

US08654970B2 Apparatus and method for implementing instruction support for the data encryption standard (DES) algorithm 有权
标题翻译：用于实现数据加密标准（DES）算法的指令支持的装置和方法
公开(公告)号：US08654970B2
公开(公告)日：2014-02-18
申请号：US12414755
申请日：2009-03-31
申请人： Christopher H. Olson , Gregory F. Grohoski , Lawrence A. Spracklen
发明人： Christopher H. Olson , Gregory F. Grohoski , Lawrence A. Spracklen
IPC分类号： H04K1/00 , H04L9/00
CPC分类号： G06F21/72 , G06F9/30007 , H04L9/0625 , H04L2209/122 , H04L2209/125 , H04L2209/24
摘要： A processor including instruction support for implementing the Data Encryption Standard (DES) block cipher algorithm may issue, for execution, programmer-selectable instructions from a defined instruction set architecture (ISA). The processor may include a cryptographic unit that may receive instructions for execution. The instructions include one or more DES instructions defined within the ISA. In addition, the DES instructions may be executable by the cryptographic unit to implement portions of an DES cipher that is compliant with Federal Information Processing Standards Publication 46-3 (FIPS 46-3). In response to receiving a DES key expansion instruction defined within the ISA, the cryptographic unit may generate one or more expanded cipher keys of the DES cipher key schedule from an input key.
摘要翻译：包括用于实现数据加密标准（DES）块密码算法的指令支持的处理器可以从定义的指令集体系结构（ISA）发出执行编程器可选择的指令。处理器可以包括可以接收执行指令的密码单元。指令包括在ISA内定义的一个或多个DES指令。此外，DES指令可以由加密单元执行，以实现符合联邦信息处理标准出版物46-3（FIPS 46-3）的DES密码的部分。响应于接收到在ISA内定义的DES密钥扩展指令，密码单元可以从输入密钥生成DES密码密钥调度的一个或多个扩展密码密钥。

17. 发明授权

US08417961B2 Apparatus and method for implementing instruction support for performing a cyclic redundancy check (CRC) 有权
标题翻译：用于执行用于执行循环冗余校验（CRC）的指令支持的装置和方法
公开(公告)号：US08417961B2
公开(公告)日：2013-04-09
申请号：US12725243
申请日：2010-03-16
申请人： Christopher H. Olson , Gregory F. Grohoski , Lawrence A. Spracklen
发明人： Christopher H. Olson , Gregory F. Grohoski , Lawrence A. Spracklen
IPC分类号： G06F11/30
CPC分类号： G06F9/3861 , G06F9/30007 , G06F9/30018 , G06F9/3851 , G06F9/3885 , G06F11/1004 , G06F21/72 , H03M13/09 , H03M13/096 , H03M13/158 , H04L1/0041 , H04L1/0061 , H04L9/0631
摘要： Techniques relating to a processor including instruction support for implementing a cyclic redundancy check (CRC) operation. The processor may issue, for execution, programmer-selectable instructions from a defined instruction set architecture (ISA). The processor may include a cryptographic unit configured to receive instructions that include a first instance of a cyclic redundancy check (CRC) instruction defined within the ISA, where the first instance of the CRC instruction is executable by the cryptographic unit to perform a first CRC operation on a set of data that produces a checksum value. In one embodiment, the cryptographic unit is configured to generate the checksum value using a generator polynomial of 0x11EDC6F41. In some embodiments, the first instance of the CRC instruction specifies an initial value to be used in performing the first CRC operation, the set of data, and a storage location in which the cryptographic unit is configured to store the checksum value produced by the first CRC operation.
摘要翻译：涉及包括执行循环冗余校验（CRC）操作的指令支持的处理器的技术。处理器可以从定义的指令集体系结构（ISA）发出执行编程器可选择的指令。处理器可以包括被配置为接收包括在ISA内定义的循环冗余校验（CRC）指令的第一实例的指令的加密单元，其中CRC指令的第一实例可由密码单元执行以执行第一CRC操作在产生校验和值的一组数据上。在一个实施例中，密码单元被配置为使用生成器多项式0x11EDC6F41生成校验和值。在一些实施例中，CRC指令的第一实例指定用于执行第一CRC操作，数据集合以及存储位置的初始值，其中密码单元被配置为存储由第一个CRC操作产生的校验和值 CRC操作。

18. 发明授权

US08356185B2 Apparatus and method for local operand bypassing for cryptographic instructions 有权
标题翻译：用于加密指令的本地操作数旁路的装置和方法
公开(公告)号：US08356185B2
公开(公告)日：2013-01-15
申请号：US12575832
申请日：2009-10-08
申请人： Christopher H. Olson , Gregory F. Grohoski , Robert T. Golla
发明人： Christopher H. Olson , Gregory F. Grohoski , Robert T. Golla
IPC分类号： G06F9/312 , G06F21/00
CPC分类号： G09C1/00 , G06F9/30007 , G06F9/3826 , G06F9/3873 , G06F21/72 , H04L9/0637 , H04L2209/12 , H04L2209/125 , H04L2209/24
摘要： A processor may include a hardware instruction fetch unit configured to issue instructions for execution, and a hardware functional unit configured to receive instructions for execution, where the instructions include cryptographic instruction(s) and non-cryptographic instruction(s). The functional unit may include a cryptographic execution pipeline configured to execute the cryptographic instructions with a corresponding cryptographic execution latency, and a non-cryptographic execution pipeline configured to execute the non-cryptographic instructions with a corresponding non-cryptographic execution latency that is longer than the cryptographic execution latency. The functional unit may further include a local bypass network configured to bypass results produced by the cryptographic execution pipeline to dependent cryptographic instructions executing within the cryptographic execution pipeline, such that each instruction within a sequence of dependent cryptographic instructions is executable with the cryptographic execution latency, and where the results of the cryptographic execution pipeline are not bypassed to any other functional unit within the processor.
摘要翻译：处理器可以包括被配置为发出用于执行的指令的硬件指令获取单元和被配置为接收用于执行的指令的硬件功能单元，其中所述指令包括加密指令和非加密指令。功能单元可以包括被配置为执行具有相应的加密执行等待时间的加密指令的密码执行流水线，以及配置成执行非加密指令的非加密执行流水线，该非加密执行流水线的长度大于加密执行延迟。功能单元还可以包括局部旁路网络，其被配置为将由密码执行流水线产生的结果旁路到在密码执行流水线内执行的依赖密码指令，使得依赖密码指令序列内的每个指令都可以用密码执行等待时间执行，并且其中加密执行流水线的结果不被旁路到处理器内的任何其他功能单元。

19. 发明申请

US20100250964A1 APPARATUS AND METHOD FOR IMPLEMENTING INSTRUCTION SUPPORT FOR THE CAMELLIA CIPHER ALGORITHM 有权
标题翻译：用于实施CAMELLIA CIPHER算法的指导性支持的装置和方法
公开(公告)号：US20100250964A1
公开(公告)日：2010-09-30
申请号：US12414831
申请日：2009-03-31
申请人： Christopher H. Olson , Gregory F. Grohoski , Lawrence A. Spracklen
发明人： Christopher H. Olson , Gregory F. Grohoski , Lawrence A. Spracklen
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F9/30003 , G06F9/30007 , G06F9/30018 , G06F9/30167 , G06F9/382 , G06F9/3851 , G06F9/3877 , H04L9/0625 , H04L2209/122 , H04L2209/125 , H04L2209/24
摘要： A processor including instruction support for implementing the Camellia block cipher algorithm may issue, for execution, programmer-selectable instructions from a defined instruction set architecture (ISA). The processor may include a cryptographic unit that may receive instructions for execution. The instructions include one or more Camellia instructions defined within the ISA. In addition, the Camellia instructions may be executable by the cryptographic unit to implement portions of a Camellia cipher that is compliant with Internet Engineering Task Force (IETF) Request For Comments (RFC) 3713. In response to receiving a Camellia F( )-operation instruction defined within the ISA, the cryptographic unit may perform an F( ) operation, as defined by the Camellia cipher, upon a data input operand and a subkey operand, in which the data input operand and subkey operand may be specified by the Camellia F( )-operation instruction.
摘要翻译：包括用于实现Camellia块密码算法的指令支持的处理器可以从定义的指令集体系结构（ISA）发出用于执行编程器可选择指令的执行。处理器可以包括可以接收执行指令的密码单元。说明书包括在ISA内定义的一个或多个Camellia指令。另外，山茶花指令可以由加密单元执行，以实现符合因特网工程任务组（IETF）请求注释（RFC）3713的Camellia密码的部分。响应于接收到Camellia F（）操作在ISA内定义的指令中，加密单元可以在数据输入操作数和子键操作数上执行由Camellia密码定义的F（）操作，其中数据输入操作数和子键操作数可以由Camellia F （）操作指令。

20. 发明授权

US07684563B1 Apparatus and method for implementing a unified hash algorithm pipeline 有权
标题翻译：用于实现统一哈希算法流水线的装置和方法
公开(公告)号：US07684563B1
公开(公告)日：2010-03-23
申请号：US10968428
申请日：2004-10-19
申请人： Christopher H. Olson , Leonard D. Rarick , Gregory F. Grohoski
发明人： Christopher H. Olson , Leonard D. Rarick , Gregory F. Grohoski
IPC分类号： H04K1/00 , H04L9/00 , H04L9/28
CPC分类号： H04L9/16 , G06F9/3895 , H04L9/0643 , H04L2209/125 , H04L2209/38
摘要： An apparatus and method for implementing a unified hash algorithm pipeline. In one embodiment, a cryptographic unit may include hash logic configured to compute a hash value of a data block according to a hash algorithm, where the hash algorithm is dynamically selectable from a plurality of hash algorithms, and where the hash logic comprises a plurality of pipeline stages each configured to compute a portion of the hash algorithm. The cryptographic unit may further include a word buffer configured to store the data block during computing by the hash logic.
摘要翻译：一种用于实现统一哈希算法流水线的装置和方法。在一个实施例中，密码单元可以包括哈希逻辑，其被配置为根据散列算法计算数据块的哈希值，其中散列算法可以从多个散列算法动态地选择，并且其中散列逻辑包括多个流水线级分别被配置为计算散列算法的一部分。加密单元还可以包括字缓冲器，其被配置为在由哈希逻辑计算期间存储数据块。

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