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11. 发明申请

US20120212853A1 Method and Apparatus to Position a Head Module Comprising Servo Elements and Plurality of Data Elements 有权
标题翻译：用于定位包括伺服元件和多个数据元素的头模块的方法和装置
公开(公告)号：US20120212853A1
公开(公告)日：2012-08-23
申请号：US13460614
申请日：2012-04-30
申请人： Nhan Xuan Bui , Giovanni Cherubini , Robert Allen Hutchins , Jens Jelitto , Kazuhiro Tsuruta
发明人： Nhan Xuan Bui , Giovanni Cherubini , Robert Allen Hutchins , Jens Jelitto , Kazuhiro Tsuruta
IPC分类号： G11B21/02
CPC分类号： G11B5/5552
摘要： A method to position a head module, where the head module comprises at least one servo element and a plurality of data elements, where the servo element and each of the plurality of data elements can detect a servo signal, wherein the method includes moving a sequential information storage medium having a servo band encoded therein across the head module and detecting the servo band using the at least one servo element or any one of the plurality of data elements.
摘要翻译：一种定位头模块的方法，其中头模块包括至少一个伺服元件和多个数据元件，其中伺服元件和多个数据元素中的每一个可以检测伺服信号，其中该方法包括移动顺序信息存储介质，其中跨越所述头模块编码了伺服频带，并且使用所述至少一个伺服单元或所述多个数据单元中的任何一个来检测所述伺服频带。

12. 发明授权

US08054568B2 Synchronization of symmetric timing based servo bursts 有权
标题翻译：基于对称定时的伺服脉冲串同步
公开(公告)号：US08054568B2
公开(公告)日：2011-11-08
申请号：US12712039
申请日：2010-02-24
申请人： Giovanni Cherubini , Robert Allen Hutchins , Jens Jelitto , Mark Alfred Lantz
发明人： Giovanni Cherubini , Robert Allen Hutchins , Jens Jelitto , Mark Alfred Lantz
IPC分类号： G11B5/09 , G11B5/584
CPC分类号： G11B5/584 , G11B5/09
摘要： Timing based servo bursts of servo frames, in which the frames are arranged to be symmetric with the same number of servo stripes in each burst of a frame, are synchronized by shifting selected bits. For example, servo frames are arranged with four servo bursts with an equal number of servo stripes in each burst, the servo frames comprising two symmetric sub-frames, each sub-frame comprising two bursts of servo stripes that are parallel to each other within a burst, and the bursts are non-parallel with respect to each other; each servo burst is arranged to comprise at least one reference servo stripe; and each servo burst is arranged to comprise at least one shifted servo stripe, wherein the shift is in the same longitudinal direction with respect to at least one reference servo stripe for each burst of a frame and the opposite longitudinal direction for bursts of sequentially adjacent frames.
摘要翻译：伺服帧的基于时序的伺服脉冲串通过移位所选位来同步，其中帧被布置为在帧的每个突发中具有相同数目的伺服条带对称。例如，伺服帧被布置成具有在每个突发中具有相等数量的伺服条带的四个伺服脉冲串，伺服帧包括两个对称子帧，每个子帧包括在一个内部的彼此平行的两个脉冲串的伺服条带突发，并且突发是相互不平行的; 每个伺服脉冲串被布置成包括至少一个参考伺服条纹; 并且每个伺服脉冲串被布置成包括至少一个移位的伺服条带，其中相对于帧的每个脉冲串相对于至少一个参考伺服条带的移位在相同的纵向方向上，并且相反的纵向方向用于顺序相邻帧的突发。

13. 发明申请

US20090174964A1 SERVO CHANNEL FOR TAPE DRIVE SYSTEMS 有权
标题翻译：用于磁带驱动系统的伺服通道
公开(公告)号：US20090174964A1
公开(公告)日：2009-07-09
申请号：US11969184
申请日：2008-01-03
申请人： Giovanni Cherubini , Roy Daron Cideciyan , Evangelos S. Eleftheriou , Robert Allen Hutchins , Jens Jelitto
发明人： Giovanni Cherubini , Roy Daron Cideciyan , Evangelos S. Eleftheriou , Robert Allen Hutchins , Jens Jelitto
IPC分类号： G11B5/584
CPC分类号： G11B5/584
摘要： Provided are techniques for synchronous servo channel for a data tape drive. A servo reader is configured to read servo bursts from a data tape. An anti-aliasing filter is operable to output a bandlimited signal and is coupled to receive a servo channel signal comprising servo bursts from the servo reader. An analog-to-digital converter (ADC) is operable to output signal samples and is coupled to receive the bandlimited signal from the anti-aliasing filter. An interpolation and control unit is operable to output interpolated signal samples and control signals, has a first input coupled to receive the signal samples from the ADC, and has a second input coupled to receive the correlation signal samples from the dibit correlator. A dibit correlator is operable to output correlation signal samples and is coupled to receive the interpolated signal samples and control signals from the interpolation and control unit.
摘要翻译：提供了用于数据磁带驱动器的同步伺服通道的技术。伺服读取器被配置为从数据磁带读取伺服脉冲串。抗混叠滤波器可操作以输出带限信号，并且耦合以接收包括来自伺服读取器的伺服脉冲串的伺服信道信号。模数转换器（ADC）可操作以输出信号采样并被耦合以从抗混叠滤波器接收带限信号。内插和控制单元可操作以输出内插信号样本和控制信号，具有耦合以从ADC接收信号样本的第一输入，并具有耦合以从双位相关器接收相关信号样本的第二输入。双向相关器可操作以输出相关信号样本，并被耦合以从内插和控制单元接收内插的信号样本和控制信号。

14. 发明授权

US07605992B2 Robust LPOS detection with predictor and bit verifier 失效
标题翻译：具有预测器和位验证器的鲁棒LPOS检测
公开(公告)号：US07605992B2
公开(公告)日：2009-10-20
申请号：US12020961
申请日：2008-01-28
申请人： Nhan Xuan Bui , Robert Allen Hutchins , Melanie Jean Sandberg , Kazuhiro Tsuruta
发明人： Nhan Xuan Bui , Robert Allen Hutchins , Melanie Jean Sandberg , Kazuhiro Tsuruta
IPC分类号： G11B5/09
CPC分类号： G11B5/584 , G11B5/00813
摘要： A tape drive system which includes the ability to reliably reproduce LPOS information even if both of the servo channels of the tape drive system could not detect the LPOS information due to defects. The system recognizes that an LPOS sequence is sequentially incremented by one if a tape is moving in a forward direction and decremented by one if the tape is moving in a backward direction. This sequential property of the LPOS information lends itself to LPOS prediction, where the LPOS prediction is the previous LPOS value plus one if the tape is moving forward and the previous LPOS value minus one if the tape is moving backward. Even if the LPOS words from the two servo channels are both bad, but not all of the bits in the LPOS word are bad. The system uses the remaining good bits from the two servo channels to verify all of the bits of the LPOS prediction word.
摘要翻译：即使磁带驱动系统的两个伺服通道都由于缺陷而无法检测到LPOS信息，也能够可靠地再现LPOS信息的磁带驱动系统。如果磁带正向移动，则系统识别LPOS序列依次增加1，如果磁带沿向后方向移动，则LPOS序列递减1。 LPOS信息的这种顺序属性适用于LPOS预测，其中LPOS预测是先前的LPOS值，如果磁带正向前移动，则前一LPOS值减去1，如果磁带向后移动，则前一LPOS值减1。即使来自两个伺服通道的LPOS字都是坏的，但LPOS字中的所有位都不好。该系统使用来自两个伺服通道的剩余良好位来验证LPOS预测字的所有位。

15. 发明申请

US20090190250A1 Robust LPOS Detection With Predictor and Bit Verifier 失效
标题翻译：使用预测器和位验证器进行强大的LPOS检测
公开(公告)号：US20090190250A1
公开(公告)日：2009-07-30
申请号：US12020961
申请日：2008-01-28
申请人： Nhan Xuan Bui , Robert Allen Hutchins , Melanie Jean Sandberg , Kazuhiro Tsuruta
发明人： Nhan Xuan Bui , Robert Allen Hutchins , Melanie Jean Sandberg , Kazuhiro Tsuruta
IPC分类号： G11B5/584
CPC分类号： G11B5/584 , G11B5/00813
摘要： A tape drive system which includes the ability to reliably reproduce LPOS information even if both of the servo channels of the tape drive system could not detect the LPOS information due to defects. The system recognizes that an LPOS sequence is sequentially incremented by one if a tape is moving in a forward direction and decremented by one if the tape is moving in a backward direction. This sequential property of the LPOS information lends itself to LPOS prediction, where the LPOS prediction is the previous LPOS value plus one if the tape is moving forward and the previous LPOS value minus one if the tape is moving backward. Even if the LPOS words from the two servo channels are both bad, but not all of the bits in the LPOS word are bad. The system uses the remaining good bits from the two servo channels to verify all of the bits of the LPOS prediction word.
摘要翻译：即使磁带驱动系统的两个伺服通道都由于缺陷而无法检测到LPOS信息，也能够可靠地再现LPOS信息的磁带驱动系统。如果磁带正向移动，则系统识别LPOS序列依次增加1，如果磁带沿向后方向移动，则LPOS序列递减1。 LPOS信息的这种顺序属性适用于LPOS预测，其中LPOS预测是先前的LPOS值，如果磁带正向前移动，则前一LPOS值减去1，如果磁带向后移动，则前一LPOS值减1。即使来自两个伺服通道的LPOS字都是坏的，但LPOS字中的所有位都不好。该系统使用来自两个伺服通道的剩余良好位来验证LPOS预测字的所有位。

16. 发明授权

US07777980B2 Multi-channel data detection phase locked loop error combination logic 失效
标题翻译：多通道数据检测锁相环路错误组合逻辑
公开(公告)号：US07777980B2
公开(公告)日：2010-08-17
申请号：US11870853
申请日：2007-10-11
申请人： Robert Allen Hutchins , Jens Jelitto , Sedat Oelcer
发明人： Robert Allen Hutchins , Jens Jelitto , Sedat Oelcer
IPC分类号： G11B5/09
CPC分类号： G11B20/10009 , G11B20/10037 , G11B20/10425
摘要： Phase-error combination for a multi-channel data detection system with a phase locked loop for each channel, comprises receiving phase error information with respect to each channel; combination logic configured to combine the received phase error information and generate a combined phase error; and a phase-error output configured to apply the combined phase error to at least one channel phase locked loop. Additionally, error signal combination comprises receiving error information of a signal relevant to a phase locked loop with respect to each channel; combination logic configured to combine the received error signal information and generate a combined error signal, weighting the received error signal information from each channel, for example with reliability information. An error compensation output is configured to apply the combined, weighted error signal to at least one channel phase locked loop.
摘要翻译：具有用于每个通道的锁相环的多通道数据检测系统的相位误差组合包括接收关于每个通道的相位误差信息; 组合逻辑，被配置为组合所接收的相位误差信息并产生组合的相位误差; 以及被配置为将组合的相位误差应用于至少一个通道锁相环的相位误差输出。另外，误差信号组合包括相对于每个信道接收与锁相环相关的信号的误差信息; 组合逻辑，其被配置为组合所接收的误差信号信息并产生组合误差信号，例如对可靠性信息加权来自每个信道的接收到的误差信号信息。误差补偿输出被配置为将组合的加权误差信号应用于至少一个通道锁相环。

17. 发明申请

US20090097606A1 METHODS FOR MULTI-CHANNEL DATA DETECTION PHASE LOCKED LOOP FREQUENCY ERROR COMBINATION 失效
标题翻译：多通道数据检测方法相位锁定环路频率误差组合
公开(公告)号：US20090097606A1
公开(公告)日：2009-04-16
申请号：US11870934
申请日：2007-10-11
申请人： Robert Allen Hutchins , Jens Jelitto , Sedat Oelcer
发明人： Robert Allen Hutchins , Jens Jelitto , Sedat Oelcer
IPC分类号： H03D3/24
CPC分类号： H04L7/0029 , H03L7/07 , H03L7/087 , H03L7/091 , H04L7/0025 , H04L7/0062 , H04L7/0083
摘要： Frequency error combination for a multi-channel data detection system with a phase locked loop for each channel, comprises receiving frequency error information of a signal relevant to a phase locked loop with respect to each channel; combining the received error signal information and generating a combined error signal, weighting the received error signal information from each channel, for example with reliability information. The combined frequency error signal is applied to at least one channel phase locked loop.
摘要翻译：针对每个通道具有锁相环的多通道数据检测系统的频率误差组合包括相对于每个通道接收与锁相环相关的信号的频率误差信息; 组合接收到的误差信号信息并产生组合误差信号，例如用可靠性信息对来自每个信道的接收到的误差信号进行加权。组合的频率误差信号被施加到至少一个通道锁相环。

18. 发明申请

US20090097536A1 MULTI-CHANNEL DATA DETECTION PHASE LOCKED LOOP FREQUENCY ERROR COMBINATION LOGIC 失效
标题翻译：多通道数据检测相位锁定频率错误组合逻辑
公开(公告)号：US20090097536A1
公开(公告)日：2009-04-16
申请号：US11870921
申请日：2007-10-11
申请人： Robert Allen Hutchins , Jens Jelitto , Sedat Oelcer
发明人： Robert Allen Hutchins , Jens Jelitto , Sedat Oelcer
IPC分类号： H04Q1/20
CPC分类号： G11B20/10009 , G11B20/10037 , G11B20/10425
摘要： Frequency error combination for a multi-channel data detection system with a phase locked loop for each channel, comprises receiving frequency error information with respect to each channel; combination logic configured to combine the received frequency error information and generate a combined phase error, weighting the received frequency error information from each channel; and a frequency error output configured to apply the combined frequency error to at least one channel phase locked loop.
摘要翻译：针对每个通道的具有锁相环的多通道数据检测系统的频率误差组合包括接收关于每个通道的频率误差信息; 组合逻辑，其被配置为组合所接收的频率误差信息并产生组合的相位误差，从每个信道对所接收的频率误差信息进行加权; 以及频率误差输出，被配置为将组合的频率误差应用于至少一个通道锁相环。

19. 发明授权

US07760821B2 Oversampled channel response identification 失效
标题翻译：过采样通道响应标识
公开(公告)号：US07760821B2
公开(公告)日：2010-07-20
申请号：US11558949
申请日：2006-11-13
申请人： Giovanni Cherubini , Evangelos S. Eleftheriou , Robert Allen Hutchins , Glen Alan Jaquette , Sedat Oelcer
发明人： Giovanni Cherubini , Evangelos S. Eleftheriou , Robert Allen Hutchins , Glen Alan Jaquette , Sedat Oelcer
IPC分类号： H04L27/06
CPC分类号： G11B20/10009 , G11B20/10046 , G11B20/10212 , H04B1/7085 , H04J2013/0037 , H04L25/0212 , H04L25/03038
摘要： Methods, apparatus and computer programs are provided for multiplication-free identification of the impulse response of an oversampled data channel. An input comprising a pseudo-random binary sequence of L symbols is supplied to the channel at a symbol rate of 1/T. A channel output is produced by sampling a channel output signal corresponding to the input with a sampling interval TS=(q/p)T, where q and p are relative prime integers with q
摘要翻译：提供了方法，装置和计算机程序，用于对过采样数据信道的脉冲响应进行无乘法识别。将包含L个符号的伪随机二进制序列的输入以符号率1 / T提供给信道。通过以采样间隔TS =（q / p）T对与输入相对应的信道输出信号进行采样来产生信道输出，其中q和p是具有q

20. 发明授权

US08019034B2 Common state-space multi-channel digital sample timing phase control of multiple read channels for correlated signals 失效
标题翻译：用于相关信号的多个读通道的通用状态空间多通道数字采样定时相位控制
公开(公告)号：US08019034B2
公开(公告)日：2011-09-13
申请号：US11870765
申请日：2007-10-11
申请人： Robert Allen Hutchins , Jens Jelitto , Sedat Oelcer
发明人： Robert Allen Hutchins , Jens Jelitto , Sedat Oelcer
IPC分类号： H04L7/00
CPC分类号： H03L7/0994 , G11B20/10037 , G11B20/1403 , G11B20/20 , H03L7/07 , H03L7/093
摘要： Common sample timing control for sample timing of multiple read channels, wherein the signal clocking of the signals received by the multiple read channels are correlated, for example from parallel tracks of magnetic tape that have been written simultaneously. In one embodiment, a common sample timing control comprises multiple phase error inputs, each indicating phase error of one of the read channels. Logic responsive to the multiple phase error inputs is configured to weight and crosscouple the phase error indication of each phase error input with the phase error indication of each other phase error input, and to apply gain related to the variance of noise of the phase error indications. Feedback logic is responsive to the crosscoupling and is configured to provide a sample timing phase estimate for each read channel.
摘要翻译：用于多个读取通道的采样定时的公共采样定时控制，其中由多个读取通道接收的信号的信号时钟与例如已经被同时写入的磁带的平行磁道相关。在一个实施例中，公共采样定时控制包括多个相位误差输入，每个相位误差输入指示一个读取通道的相位误差。响应于多个相位误差输入的逻辑被配置为对每个相位误差输入的相位误差指示进行加权和交叉耦合，并且将每个相位误差输入的相位误差指示与相位误差指示的噪声方差相关联。反馈逻辑响应于交叉耦合，并且被配置为为每个读取通道提供采样定时相位估计。

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