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11. 发明授权

US07171487B2 Method and system for application specific packet forwarding 失效
标题翻译：应用程序特定数据包转发的方法和系统
公开(公告)号：US07171487B2
公开(公告)日：2007-01-30
申请号：US09960237
申请日：2001-09-21
申请人： Andreas Herkersdorf , Sean G. Rooney
发明人： Andreas Herkersdorf , Sean G. Rooney
IPC分类号： G06F15/173
CPC分类号： H04L47/32 , A63F2300/409 , H04L29/06 , H04L47/10 , H04L47/19 , H04L67/38
摘要： The present invention provides a method and system handling information exchange through networks 102 to 110 for interactive information exchange, especially for interactive Internet based game show. At least one server 120 and a plurality of client machines 130 to 146 are connected through the networks 102 to 110. First, the server 120 receives subscription messages from a subset of said client machines 130 to 146. By receiving the subscription messages from the client machines 130 to 146 the provider of the particular program knows which users want to participate in the program. In response, the server 120 composes a request message offering predetermined response options, whereby corresponding response messages are returned through said networks 102 to 110 in one or more packets. In parallel, packet forwarding rules are set up in said networks 102 to 110 specifying a particular treatment for said returned packets dependent on said predetermined response options. Finally, the server sends the request message to the subset of client machines.
摘要翻译：本发明提供了一种通过网络102至110处理信息交换的方法和系统，用于交互式信息交换，特别是用于基于互动的基于互联网的游戏节目。至少一个服务器120和多个客户端机器130至146通过网络102至110连接。首先，服务器120从所述客户端机器130至146的子集接收订阅消息。通过从客户端接收订阅消息机器130至146，特定程序的提供者知道哪些用户想要参与该程序。作为响应，服务器120组成提供预定响应选项的请求消息，由此在一个或多个分组中通过所述网络102至110返回对应的响应消息。并行地，在所述网络102至110中建立分组转发规则，根据所述预定响应选项指定针对所述返回分组的特定处理。最后，服务器将请求消息发送到客户机的子集。

12. 发明申请

US20060285551A1 STM-1 TO STM-64 SDH/SONET FRAMER WITH DATA MULTIPLEXING FROM A SERIES OF CONFIGURABLE I/O PORTS 有权
标题翻译： STM-1到STM-64 SDH / SONET框架，具有从一系列可配置I / O端口进行数据多路复用
公开(公告)号：US20060285551A1
公开(公告)日：2006-12-21
申请号：US11467848
申请日：2006-08-28
申请人： Kenneth Barker , Rolf Clauberg , Jean Calvignac , Andreas Herkersdorf , Fabrice Verplanken , David Webb
发明人： Kenneth Barker , Rolf Clauberg , Jean Calvignac , Andreas Herkersdorf , Fabrice Verplanken , David Webb
IPC分类号： H04J3/22
CPC分类号： H04J3/1611 , H04J3/0685 , H04J3/22 , H04J2203/0089
摘要： The present invention relates to a device for combining at least two data signals having an input data rate into a single data stream having an output data rate being higher than the input data rate for transmission on a shared medium or vice versa, particularly, to a single SDH/SONET framer capable of handling a large range of SDH/SONET frames from STM-i to STM-j with an aggregated total capacity corresponding to an STM-j frame where i and j are integers in the range from 1 to 64 or higher according to the STM-N definition of the SDH/SONET standards. More over, the present invention can also be extended to work with STS-1 as lowest range. STS-1 exists in SONET only not SDH and corresponds to a data rate of 51.5 Mb/s a third of the 156 Mb/s of STM-1. The device according to the present invention comprises at least two ports for receiving and/or sending said at least two data signals, a port snning unit for extracting data from the data signals received by said ports and/or synthesizing data to be transmitted via the ports, respectively, whereby said port scanning unit is configured to extract data from ports providing data streams having at least two different input data rates and/or to synthesize data to be transmitted via the ports taking data streams having at least two different data rates.
摘要翻译：本发明涉及一种用于将具有输入数据速率的至少两个数据信号组合成具有高于用于在共享介质上传输的输入数据速率的输出数据速率的单个数据流的装置，反之亦然，特别涉及一种单个SDH / SONET成帧器能够处理从STM-i到STM-j的大范围的SDH / SONET帧，具有对应于STM-j帧的聚合总容量，其中i和j是从1到64的整数或根据SDH / SONET标准的STM-N定义更高。更进一步地，本发明也可以扩展到使用STS-1作为最低范围。 STS-1仅存在于SONET中而不是SDH，对应于156Mb / s的STM-1的三分之一的51.5Mb / s的数据速率。根据本发明的装置包括用于接收和/或发送所述至少两个数据信号的至少两个端口，用于从由所述端口接收的数据信号中提取数据和/或合成要通过所述端口发送的数据的端口捕捉单元其中所述端口扫描单元被配置为从提供具有至少两个不同输入数据速率的数据流的端口提取数据和/或合成要通过端口发送的数据，该数据流具有至少两个不同数据速率的数据流。

13. 发明申请

US20060265372A1 LOOKUPS BY COLLISIONLESS DIRECT TABLES AND CAMS 有权
标题翻译：无连续直接表和CAMS的查询
公开(公告)号：US20060265372A1
公开(公告)日：2006-11-23
申请号：US11462071
申请日：2006-08-03
申请人： Gordon Davis , Andreas Herkersdorf , Clark Jeffries , Mark Rinaldi
发明人： Gordon Davis , Andreas Herkersdorf , Clark Jeffries , Mark Rinaldi
IPC分类号： G06F7/00
CPC分类号： H04L49/3009 , H04L45/745 , H04L45/7453 , H04L49/351
摘要： A structure and technique for preventing collisions using a hash table in conjunction with a CAM to identify and prevent a collisions of binary keys. A portion of the hash value of a binary key, which does not collide with a portion of the hash value of any other reference binary key, is used as an entry in the hash table. If two or more binary keys have identical values of the portions of the hash values, each of these binary keys are stored in their entirety, in the CAM. The key in the CAM provides a pointer to a data structure where the action associated with that binary key is stored. If the binary key is not found in the CAM, the binary key is hashed, and a specific entry in the hash table is selected using a portion of this hash value.
摘要翻译：一种用于使用散列表与CAM结合来防止冲突的结构和技术，以识别和防止二进制键的冲突。不与任何其他参考二进制密钥的散列值的一部分相冲突的二进制密钥的散列值的一部分被用作散列表中的条目。如果两个或更多个二进制密钥具有相同的哈希值部分的值，则这些二进制密钥中的每一个都将全部存储在CAM中。 CAM中的关键字提供了指向数据结构的指针，其中存储与该二进制密钥相关联的动作。如果在CAM中没有找到二进制密钥，则二进制密钥被散列，并且使用该哈希值的一部分来选择散列表中的特定条目。

14. 发明申请

US20050097305A1 Method and apparatus for using FPGA technology with a microprocessor for reconfigurable, instruction level hardware acceleration 有权
标题翻译：使用FPGA技术与微处理器进行可重配置，指令级硬件加速的方法和装置
公开(公告)号：US20050097305A1
公开(公告)日：2005-05-05
申请号：US10696865
申请日：2003-10-30
申请人： Andreas Doering , Silvio Dragone , Andreas Herkersdorf , Richard Hofmann , Charles Kuhlmann
发明人： Andreas Doering , Silvio Dragone , Andreas Herkersdorf , Richard Hofmann , Charles Kuhlmann
IPC分类号： G06F9/00 , G06F9/318 , G06F9/38 , G06F15/78
CPC分类号： G06F9/3877 , G06F9/30181 , G06F9/3897 , G06F15/7867
摘要： A method for dynamically programming Field Programmable Gate Arrays (FPGA) in a coprocessor, the coprocessor coupled to a processor, includes: beginning an execution of an application by the processor; receiving an instruction from the processor to the coprocessor to perform a function for the application; determining that the FPGA in the coprocessor is not programmed with logic for the function; fetching a configuration bit stream for the function; and programming the FPGA with the configuration bit stream. In this manner, the FPGA are programmable “on the fly”, i.e., dynamically during the execution of an application. The hardware acceleration and resource sharing advantages provided by the FPGA can be utilized more often by the application. Logic flexibility and space savings on the chip comprising the coprocessor and processor are provided as well.
摘要翻译：一种用于在协处理器中动态编程现场可编程门阵列（FPGA）的方法，所述协处理器耦合到处理器，包括：开始处理器执行应用程序; 从所述处理器接收到所述协处理器的指令以执行所述应用的功能; 确定协处理器中的FPGA不是用该功能的逻辑编程的; 获取功能的配置位流; 并使用配置位流对FPGA进行编程。以这种方式，FPGA可以“即时”编程，即在执行应用期间动态地编程。应用程序可以更频繁地利用FPGA提供的硬件加速和资源共享优势。还提供了包括协处理器和处理器的芯片上的逻辑灵活性和空间节省。

15. 发明授权

US06556593B1 Digital cross connect and add/drop multiplexing device for SDH or SONET signals 失效
标题翻译：用于SDH或SONET信号的数字交叉连接和分插复用器件
公开(公告)号：US06556593B1
公开(公告)日：2003-04-29
申请号：US09117054
申请日：1998-07-21
申请人： Andreas Herkersdorf , Wolfram Lemppenau , Harmen R. van As
发明人： Andreas Herkersdorf , Wolfram Lemppenau , Harmen R. van As
IPC分类号： H04J304
CPC分类号： G11B20/1202 , G11B27/107 , G11B27/3027 , G11B27/322 , G11B2220/93 , H04J3/0614 , H04J3/085 , H04J2203/0012 , Y10S370/907
摘要： In a communication network for transferring signals, e.g. according to the SONET or SDH standards, interconnecting node devices are provided consisting of parallel processing modules (9-T, 9-R). A plurality of processing modules with first and second interfaces rearrange/insert/extract tributary signals and configurable multiplexing/de-multiplexing components enable each processing module to access any portion of an arbitrarily preselected tributary signal. In a SONET/SDH system, signals between SONET/SDH frames are rearranged on incoming (20) and outgoing (26) main lines=Digital Cross-Connect, or tributary signals are transferred between frames and local lines (16-i-T, 16-i-R)=Add/Drop Function. The system provides configurable multiplexing/de-multiplexing components (22-i, 24-i, 28-i, 30-i) which allow the processing modules to have access to any tributary signals in said frames, thus enabling digital cross-connect and add/drop operations without completely demultiplexing or disassembling frames. In a preferred embodiment, the configurable multiplexing/demultiplexing component includes a pipeline arrangement (22-i, 24-i) connected to all processing modules (9-T, 9-R).
摘要翻译：在用于传送信号的通信网络中，例如，根据SONET或SDH标准，提供由并行处理模块（9-T，9-R）组成的互连节点设备。具有第一和第二接口的多个处理模块重新排列/插入/提取支路信号和可配置的复用/解复用部件使得每个处理模块能够访问任意预选的支路信号的任何部分。在SONET / SDH系统中，SONET / SDH帧之间的信号在进入（20）和输出（26）主线=数字交叉连接时重新排列，或者支路信号在帧和本地线路之间传输（16-iT，16- iR）=加/减功能。该系统提供可配置的多路复用/解复用组件（22-i，24-i，28-i，30-i），其允许处理模块访问所述帧中的任何支路信号，从而实现数字交叉连接和没有完全解复用或拆卸帧的添加/删除操作。在优选实施例中，可配置多路复用/多路分解组件包括连接到所有处理模块（9-T，9-R）的流水线装置（22-i，24-i）。

16. 发明申请

US20080270754A1 USING FIELD PROGRAMMABLE GATE ARRAY (FPGA) TECHNOLOGY WITH A MICROPROCESSOR FOR RECONFIGURABLE, INSTRUCTION LEVEL HARDWARE ACCELERATION 有权
标题翻译：使用现场可编程门阵列（FPGA）技术与微处理器进行可重新配置，指示级硬件加速
公开(公告)号：US20080270754A1
公开(公告)日：2008-10-30
申请号：US12167202
申请日：2008-07-02
申请人： Andreas C. DOERING , Silvio Dragone , Andreas Herkersdorf , Richard G. Hofmann , Charles E. Kuhlmann
发明人： Andreas C. DOERING , Silvio Dragone , Andreas Herkersdorf , Richard G. Hofmann , Charles E. Kuhlmann
IPC分类号： G06F15/76 , G06F9/30
CPC分类号： G06F9/3877 , G06F9/30181 , G06F9/3897 , G06F15/7867
摘要： A method for dynamically programming Field Programmable Gate Arrays (FPGAs) in a coprocessor, the coprocessor coupled to a processor, includes: beginning an execution of an application by the processor; receiving an instruction from the processor to the coprocessor to perform a function for the application; determining that the FPGA in the coprocessor is not programmed with logic for the function; fetching a configuration bit stream for the function; and programming the FPGA with the configuration bit stream. In this manner, the FPGA are programmable “on the fly”, i.e., dynamically during the execution of an application. The hardware acceleration and resource sharing advantages provided by the FPGA can be utilized more often by the application. Logic flexibility and space savings on the chip comprising the coprocessor and processor are provided as well.
摘要翻译：一种用于在协处理器中动态编程现场可编程门阵列（FPGA）的方法，所述协处理器耦合到处理器，所述协处理器包括：由处理器开始执行应用程序; 从所述处理器接收到所述协处理器的指令以执行所述应用的功能; 确定协处理器中的FPGA不是用该功能的逻辑编程的; 获取功能的配置位流; 并使用配置位流对FPGA进行编程。以这种方式，FPGA可以“即时”编程，即在执行应用期间动态地编程。应用程序可以更频繁地利用FPGA提供的硬件加速和资源共享优势。还提供了包括协处理器和处理器的芯片上的逻辑灵活性和空间节省。

17. 发明申请

US20080098015A1 LOOKUPS BY COLLISIONLESS DIRECT TABLES AND CAMS 有权
标题翻译：无连续直接表和CAMS的查询
公开(公告)号：US20080098015A1
公开(公告)日：2008-04-24
申请号：US11962558
申请日：2007-12-21
申请人： Gordon Davis , Andreas Herkersdorf , Clark Jeffries , Mark Rinaldi
发明人： Gordon Davis , Andreas Herkersdorf , Clark Jeffries , Mark Rinaldi
IPC分类号： G06F17/30
CPC分类号： H04L49/3009 , H04L45/745 , H04L45/7453 , H04L49/351
摘要： A structure and technique for preventing collisions using a hash table in conjunction with a CAM to identify and prevent collisions of binary keys. A portion of the hash value of a binary key, which does not collide with a portion of the hash value of any other reference binary key, is used as an entry in the hash table. If two or more binary keys have identical values of the portions of the hash values, each of these binary keys are stored in their entirety, in the CAM. The key in the CAM provides a pointer to a data structure where the action associated with that binary key is stored. If the binary key is not found in the CAM, the binary key is hashed, and a specific entry in the hash table is selected using a portion of this hash value.
摘要翻译：一种用于使用散列表与CAM结合来防止冲突的结构和技术，以识别和防止二进制键的冲突。不与任何其他参考二进制密钥的散列值的一部分相冲突的二进制密钥的散列值的一部分被用作散列表中的条目。如果两个或更多个二进制密钥具有相同的哈希值部分的值，则这些二进制密钥中的每一个都将全部存储在CAM中。 CAM中的关键字提供了指向数据结构的指针，其中存储与该二进制密钥相关联的动作。如果在CAM中没有找到二进制密钥，则二进制密钥被散列，并且使用该哈希值的一部分来选择散列表中的特定条目。

18. 发明申请

US20080028140A1 LOOKUPS BY COLLISIONLESS DIRECT TABLES AND CAMS 有权
标题翻译：无连续直接表和CAMS的查询
公开(公告)号：US20080028140A1
公开(公告)日：2008-01-31
申请号：US11867963
申请日：2007-10-05
申请人： Gordon Davis , Andreas Herkersdorf , Clark Jeffries , Mark Rinaldi
发明人： Gordon Davis , Andreas Herkersdorf , Clark Jeffries , Mark Rinaldi
IPC分类号： G06F12/00
CPC分类号： H04L49/3009 , H04L45/745 , H04L45/7453 , H04L49/351
摘要： A structure and technique for preventing collisions using a hash table in conjunction with a CAM to identify and prevent collision of binary keys. A portion of the hash value of a binary key, which does not collide with a portion of the hash value of any other reference binary key, is used as an entry in the hash table. If two or more binary keys have identical values of the portions of the hash values, each of these binary keys are stored in their entirety, in the CAM. The key in the CAM provides a pointer to a data structure where the action associated with that binary key is stored. If the binary key is not found in the CAM, the binary key is hashed, and a specific entry in the hash table is selected using a portion of this hash value.
摘要翻译：一种用于使用散列表与CAM结合来防止冲突的结构和技术，以识别和防止二进制密钥的冲突。不与任何其他参考二进制密钥的散列值的一部分相冲突的二进制密钥的散列值的一部分被用作散列表中的条目。如果两个或更多个二进制密钥具有相同的哈希值部分的值，则这些二进制密钥中的每一个都将全部存储在CAM中。 CAM中的关键字提供了指向数据结构的指针，其中存储与该二进制密钥相关联的动作。如果在CAM中没有找到二进制密钥，则二进制密钥被散列，并且使用该哈希值的一部分来选择散列表中的特定条目。

19. 发明申请

US20050125797A1 Resource management for a system-on-chip (SoC) 审中-公开
标题翻译：片上系统（SoC）的资源管理
公开(公告)号：US20050125797A1
公开(公告)日：2005-06-09
申请号：US11005955
申请日：2004-12-07
申请人： Maria Gabrani , Andreas Doering , Patricia Saqmeister , Peter Buchmann , Andreas Herkersdorf
发明人： Maria Gabrani , Andreas Doering , Patricia Saqmeister , Peter Buchmann , Andreas Herkersdorf
IPC分类号： G06F9/46
CPC分类号： G06F9/505 , G06F2209/5019 , G06F2209/5022
摘要： Provides evaluation and management of system resources in a data processing system, particularly in a SoC device and for optimizing the operation of the system wherein the system having a plurality of components each operable to process dedicated tasks in the data processing system, wherein each of the components has its associated current resource usages depending on the currently processed task and/or its future resource usage depending on the tasks to be processed next, wherein the resource usage indicates the type of resources and the amount of resources used, wherein the processing of the task of at least one of the components can be modified to adapt the resource usage of this or other component. A method including: determining operating states; estimating current and future resource usage; if necessary adapting task processing according to a predefined scheme to reduce the-resource usage.
摘要翻译：提供在数据处理系统中的系统资源的评估和管理，特别是在SoC设备中并用于优化系统的操作的系统资源，其中系统具有多个组件，每个组件可操作以处理数据处理系统中的专用任务，其中组件具有取决于当前处理的任务和/或其将来的资源使用的相关联的当前资源使用，这取决于接下来要处理的任务，其中资源使用指示资源的类型和所使用的资源的数量，其中处理可以修改至少一个组件的任务以适应该组件或其他组件的资源使用。一种方法，包括：确定运行状态; 估计当前和未来的资源使用情况; 如果必要，根据预定义的方案适应任务处理以减少资源使用。

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