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11. 发明申请

US20140059324A1 System Core for Transferring Data Between an External Device and Memory 审中-公开
标题翻译：用于在外部设备和内存之间传输数据的系统核心
公开(公告)号：US20140059324A1
公开(公告)日：2014-02-27
申请号：US13771390
申请日：2013-02-20
申请人： Gerald George Pechanek , David Strube , Edwin Franklin Barry , Charles W. Kurak, JR. , Carl Donald Busboom , Dale Edward Schneider , Nikos P. Pitsianis , Grayson Morris , Edward A. Wolff , Patrick R. Marchand , Ricardo Rodriguez , Marco Jacobs
发明人： Gerald George Pechanek , David Strube , Edwin Franklin Barry , Charles W. Kurak, JR. , Carl Donald Busboom , Dale Edward Schneider , Nikos P. Pitsianis , Grayson Morris , Edward A. Wolff , Patrick R. Marchand , Ricardo Rodriguez , Marco Jacobs
IPC分类号： G06F15/82
CPC分类号： G06F15/82 , G06F9/30145 , G06F11/263 , Y10S707/99943
摘要： Details of a highly cost effective and efficient implementation of a manifold array (ManArray) architecture and instruction syntax for use therewith are described herein. Various aspects of this approach include the regularity of the syntax, the relative ease with which the instruction set can be represented in database form, the ready ability with which tools can be created, the ready generation of self-checking codes and parameterized test cases. Parameterizations can be fairly easily mapped and system maintenance is significantly simplified.
摘要翻译：这里描述了使用歧管阵列（ManArray）架构和指令语法的高成本有效和高效的实现的细节。该方法的各个方面包括语法的规律性，指示集可以以数据库形式表示的相对容易程度，可以创建工具的就绪能力，即时生成自检代码和参数化测试用例。可以很容易地映射参数化，并显着简化系统维护。

12. 发明申请

US20080133892A1 Methods and Apparatus for Initiating and Resynchronizing Multi-Cycle SIMD Instructions 失效
标题翻译：用于启动和重新同步多周期SIMD指令的方法和装置
公开(公告)号：US20080133892A1
公开(公告)日：2008-06-05
申请号：US11778303
申请日：2007-07-16
申请人： Gerald G. Pechanek , David Carl Strube , Edward A. Wolff , Edwin Frank Barry , Grayson Morris , Carl Donald Busboom , Dale Edward Schneider
发明人： Gerald G. Pechanek , David Carl Strube , Edward A. Wolff , Edwin Frank Barry , Grayson Morris , Carl Donald Busboom , Dale Edward Schneider
IPC分类号： G06F9/30
CPC分类号： G06F9/3885 , G06F9/30014 , G06F9/30032 , G06F9/30036 , G06F9/30065 , G06F9/30149 , G06F9/325 , G06F9/3836 , G06F9/3853 , G06F9/3857 , G06F9/3859 , G06F9/3887
摘要： Techniques for adding more complex instructions and their attendant multi-cycle execution units with a single instruction multiple data stream (SIMD) very long instruction word (VLIW) processing framework are described. In one aspect, an initiation mechanism also acts as a resynchronization mechanism to read the results of multi-cycle execution. This multi-purpose mechanism operates with a short instruction word (SIW) issue of the multi-cycle instruction, in a sequence processor (SP) alone, with a VLIW, and across all processing elements (PEs) individually or as an array of PEs. A number of advantageous floating point instructions are also described.
摘要翻译：描述了使用单指令多数据流（SIMD）非常长的指令字（VLIW）处理框架来添加更复杂指令的技术及其伴随的多周期执行单元。在一个方面，启动机制还充当重新同步机制以读取多周期执行的结果。该多用途机构以单循环指令的短指令字（SIW）问题，单独的序列处理器（SP），VLIW以及跨所有处理元件（PE）单独地或作为PE阵列来操作。还描述了许多有利的浮点指令。

13. 发明授权

US06622234B1 Methods and apparatus for initiating and resynchronizing multi-cycle SIMD instructions 有权
标题翻译：用于启动和重新同步多周期SIMD指令的方法和装置
公开(公告)号：US06622234B1
公开(公告)日：2003-09-16
申请号：US09598564
申请日：2000-06-21
申请人： Gerald G. Pechanek , David Carl Strube , Edward A. Wolff , Edwin Frank Barry , Grayson Morris , Carl Donald Busboom , Dale Edward Schneider
发明人： Gerald G. Pechanek , David Carl Strube , Edward A. Wolff , Edwin Frank Barry , Grayson Morris , Carl Donald Busboom , Dale Edward Schneider
IPC分类号： G06F938
CPC分类号： G06F9/3885 , G06F9/30014 , G06F9/30032 , G06F9/30036 , G06F9/30065 , G06F9/30149 , G06F9/325 , G06F9/3836 , G06F9/3853 , G06F9/3857 , G06F9/3859 , G06F9/3887
摘要： Techniques for adding more complex instructions and their attendant multi-cycle execution units with a single instruction multiple data, stream (SIMD) very long instruction word (VLIW) processing framework are described. In one aspect, an initiation mechanism also acts as a resynchronization mechanism to read the results of multi-cycle execution. This multi-purpose mechanism operates with a short instruction word (SIW) issue of the multi-cycle instruction, in a sequence processor (SP) alone, with a VLIW, and across all processing elements (PEs) individually or as an array of PEs. A number of advantageous floating point instructions are also described.
摘要翻译：描述了使用单个指令多个数据流（SIMD）非常长的指令字（VLIW）处理框架来添加更复杂的指令及其伴随的多周期执行单元的技术。在一个方面，启动机制还充当重新同步机制以读取多周期执行的结果。该多用途机构以单循环指令的短指令字（SIW）问题，单独的序列处理器（SP），VLIW以及跨所有处理元件（PE）单独地或作为PE阵列来操作。还描述了许多有利的浮点指令。

14. 发明授权

US06366997B1 Methods and apparatus for manarray PE-PE switch control 有权
标题翻译：用于管理PE-PE开关控制的方法和装置
公开(公告)号：US06366997B1
公开(公告)日：2002-04-02
申请号：US09649647
申请日：2000-08-29
申请人： Edwin F. Barry , Gerald G. Pechanek , Thomas L. Drabenstott , Edward A. Wolff , Nikos P. Pitsianis , Grayson Morris
发明人： Edwin F. Barry , Gerald G. Pechanek , Thomas L. Drabenstott , Edward A. Wolff , Nikos P. Pitsianis , Grayson Morris
IPC分类号： G06F1576
CPC分类号： G06F15/17381 , H04L49/1553 , H04L49/201 , H04L49/3009 , H04L49/45
摘要： Processing element to processing element switch connection control is described using a receive model that precludes communication hazards from occurring in a synchronous MIMD mode of operation. Such control allows different communication topologies and various processing effects such as an array transpose, hypercomplement or the like to be efficiently achieved utilizing architectures, such as the manifold array processing architecture. An encoded instruction method reduces the amount of state information and setup burden on the programmer taking advantage of the recognition that the majority of algorithms will use only a small fraction of all possible mux settings available. Thus, by means of transforming the PE identification based upon a communication path specified by a PE communication instruction an efficient switch control mechanism can be used. This control mechanism allows PE register broadcast operations as well as the standard mesh and hypercube communication paths over the same interconnection network. PE to PE communication instructions PEXCHG, SPRECV and SPSEND are also defined and implemented.
摘要翻译：使用接收模型描述处理元件切换连接控制的处理元件，该接收模型排除在同步MIMD操作模式中发生通信危险。这样的控制允许利用诸如歧管阵列处理架构的架构有效地实现不同的通信拓扑和各种处理效果，例如阵列转置，超补充等。编码指令方法通过利用大多数算法仅使用所有可能的多路复用器设置的一小部分的识别来减少程序员的状态信息和设置负担的量。因此，通过基于由PE通信指令指定的通信路径变换PE标识，可以使用有效的开关控制机构。该控制机制允许PE寄存器广播操作以及相同互连网络上的标准网格和超立方体通信路径。 PE到PE通信指令PEXCHG，SPRECV和SPSEND也被定义和实现。

15. 发明授权

US6167501A Methods and apparatus for manarray PE-PE switch control 有权
公开(公告)号：US6167501A
公开(公告)日：2000-12-26
申请号：US169256
申请日：1998-10-09
申请人： Edwin F. Barry , Gerald G. Pechanek , Thomas L. Drabenstott , Edward A. Wolff , Nikos P. Pitsianis , Grayson Morris
发明人： Edwin F. Barry , Gerald G. Pechanek , Thomas L. Drabenstott , Edward A. Wolff , Nikos P. Pitsianis , Grayson Morris
IPC分类号： G06F15/16 , G06F15/173 , G06F15/80 , H04L12/56
CPC分类号： G06F15/17381 , H04L49/1553 , H04L49/201 , H04L49/3009 , H04L49/45
摘要： Processing element to processing element switch connection control is described using a receive model that precludes communication hazards from occurring in a synchronous MIMD mode of operation. Such control allows different communication topologies and various processing effects such as an array transpose, hypercomplement or the like to be efficiently achieved utilizing architectures, such as the manifold array processing architecture. An encoded instruction method reduces the amount of state information and setup burden on the programmer taking advantage of the recognition that the majority of algorithms will use only a small fraction of all possible mux settings available. Thus, by means of transforming the PE identification based upon a communication path specified by a PE communication instruction an efficient switch control mechanism can be used. This control mechanism allows PE register broadcast operations as well as the standard mesh and hypercube communication paths over the same interconnection network. PE to PE communication instructions PEXCHG, SPRECV and SPSEND are also defined and implemented.

16. 发明授权

US06795909B2 Methods and apparatus for ManArray PE-PE switch control 有权
标题翻译： ManArray PE-PE开关控制的方法和装置
公开(公告)号：US06795909B2
公开(公告)日：2004-09-21
申请号：US10114646
申请日：2002-04-01
申请人： Edwin F. Barry , Gerald G. Pechanek , Thomas L. Drabenstott , Edward A. Wolff , Nikos P. Pitsianis , Grayson Morris
发明人： Edwin F. Barry , Gerald G. Pechanek , Thomas L. Drabenstott , Edward A. Wolff , Nikos P. Pitsianis , Grayson Morris
IPC分类号： G06F1517
CPC分类号： G06F15/17381 , H04L49/1553 , H04L49/201 , H04L49/3009 , H04L49/45
摘要： Processing element to processing element switch connection control is described using a receive model that precludes communication hazards from occurring in a synchronous MIMD mode of operation. Such control allows different communication topologies and various processing effects such as an array transpose, hypercomplement or the like to be efficiently achieved utilizing architectures, such as the manifold array processing architecture. An encoded instruction method reduces the amount of state information and setup burden on the programmer taking advantage of the recognition that the majority of algorithms will use only a small fraction of all possible mux settings available. Thus, by means of transforming the PE identification based upon a communication path specified by a PE communication instruction an efficient switch control mechanism can be used. This control mechanism allows PE register broadcast operations as well as the standard mesh and hypercube communication paths over the same interconnection network. PE to PE communication instructions PEXCHG, SPRECV and SPSEND are also defined and implemented.
摘要翻译：使用接收模型描述处理元件切换连接控制的处理元件，该接收模型排除在同步MIMD操作模式中发生通信危险。这样的控制允许利用诸如歧管阵列处理架构的架构有效地实现不同的通信拓扑和各种处理效果，例如阵列转置，超补充等。编码指令方法通过利用大多数算法仅使用所有可能的多路复用器设置的一小部分的识别来减少程序员的状态信息和设置负担的量。因此，通过基于由PE通信指令指定的通信路径变换PE标识，可以使用有效的开关控制机构。该控制机制允许PE寄存器广播操作以及相同互连网络上的标准网格和超立方体通信路径。 PE到PE通信指令PEXCHG，SPRECV和SPSEND也被定义和实现。

17. 发明授权

US07257696B2 Methods and apparatus for initiating and resynchronizing multi-cycle SIMD instructions 有权
标题翻译：用于启动和重新同步多周期SIMD指令的方法和装置
公开(公告)号：US07257696B2
公开(公告)日：2007-08-14
申请号：US10641441
申请日：2003-08-15
申请人： Gerald George Pechanek , David Strube , Edward A. Wolff , Edwin Franklin Barry , Grayson Morris , Carl Donald Busboom , Dale Edward Schneider
发明人： Gerald George Pechanek , David Strube , Edward A. Wolff , Edwin Franklin Barry , Grayson Morris , Carl Donald Busboom , Dale Edward Schneider
IPC分类号： G06F9/302
CPC分类号： G06F9/3885 , G06F9/30014 , G06F9/30032 , G06F9/30036 , G06F9/30065 , G06F9/30149 , G06F9/325 , G06F9/3836 , G06F9/3853 , G06F9/3857 , G06F9/3859 , G06F9/3887
摘要： Techniques for adding more complex instructions and their attendant multi-cycle execution units with a single instruction multiple data stream (SIMD) very long instruction word (VLIW) processing framework are described. In one aspect, an initiation mechanism also acts as a resynchronization mechanism to read the results of multi-cycle execution. This multi-purpose mechanism operates with a short instruction word (SIW) issue of the multi-cycle instruction, in a sequence processor (SP) alone, with a VLIW, and across all processing elements (PEs) individually or as an array of PEs. A number of advantageous floating point instructions are also described.
摘要翻译：描述了使用单指令多数据流（SIMD）非常长的指令字（VLIW）处理框架来添加更复杂指令的技术及其伴随的多周期执行单元。在一个方面，启动机制还充当重新同步机制以读取多周期执行的结果。该多用途机构以单循环指令的短指令字（SIW）问题，单独的序列处理器（SP），VLIW以及跨所有处理元件（PE）单独地或作为PE阵列来操作。还描述了许多有利的浮点指令。

18. 发明授权

US07506137B2 Methods and apparatus for initiating and resynchronizing multi-cycle SIMD instructions 失效
标题翻译：用于启动和重新同步多周期SIMD指令的方法和装置
公开(公告)号：US07506137B2
公开(公告)日：2009-03-17
申请号：US11778303
申请日：2007-07-16
申请人： Gerald George Pechanek , David Strube , Edward A. Wolff , Edwin Franklin Barry , Grayson Morris , Carl Donald Busboom , Dale Edward Schneider
发明人： Gerald George Pechanek , David Strube , Edward A. Wolff , Edwin Franklin Barry , Grayson Morris , Carl Donald Busboom , Dale Edward Schneider
IPC分类号： G06F9/302
CPC分类号： G06F9/3885 , G06F9/30014 , G06F9/30032 , G06F9/30036 , G06F9/30065 , G06F9/30149 , G06F9/325 , G06F9/3836 , G06F9/3853 , G06F9/3857 , G06F9/3859 , G06F9/3887
摘要： Techniques for adding more complex instructions and their attendant multi-cycle execution units with a single instruction multiple data stream (SIMD) very long instruction word (VLIW) processing framework are described. In one aspect, an initiation mechanism also acts as a resynchronization mechanism to read the results of multi-cycle execution. This multi-purpose mechanism operates with a short instruction word (SIW) issue of the multi-cycle instruction, in a sequence processor (SP) alone, with a VLIW, and across all processing elements (PEs) individually or as an array of PEs. A number of advantageous floating point instructions are also described.
摘要翻译：描述了使用单指令多数据流（SIMD）非常长的指令字（VLIW）处理框架来添加更复杂指令的技术及其伴随的多周期执行单元。在一个方面，启动机制还充当重新同步机制以读取多周期执行的结果。该多用途机构以单循环指令的短指令字（SIW）问题，单独的序列处理器（SP），VLIW以及跨所有处理元件（PE）单独地或作为PE阵列来操作。还描述了许多有利的浮点指令。

19. 发明授权

US06845445B2 Methods and apparatus for power control in a scalable array of processor elements 失效
公开(公告)号：US06845445B2
公开(公告)日：2005-01-18
申请号：US09853989
申请日：2001-05-11
申请人： Patrick R. Marchand , Gerald G. Pechanek , Edward A. Wolff
发明人： Patrick R. Marchand , Gerald G. Pechanek , Edward A. Wolff
IPC分类号： G06F1/32 , G06F9/30 , G06F9/38 , G06F13/00
CPC分类号： G06F9/3891 , G06F1/3203 , G06F9/30036 , G06F9/30101 , G06F9/3853 , G06F9/3885
摘要： Low power architecture features and techniques are provided in a scalable array indirect VLIW processor. These features and techniques include power control of a reconfigurable register file, conditional power control of multi-cycle operations and indirect VLIW utilization, and power control of VLIW-based vector processing using the ManArray register file indexing mechanism. These techniques are applicable to all processing elements (PEs) and the array controller sequence processor (SP) to provide substantial power savings.

20. 发明授权

US06965991B1 Methods and apparatus for power control in a scalable array of processor elements 失效
标题翻译：处理器元件可扩展阵列中功率控制的方法和装置
公开(公告)号：US06965991B1
公开(公告)日：2005-11-15
申请号：US11032799
申请日：2005-01-11
申请人： Patrick R. Marchand , Gerald G. Pechanek , Edward A. Wolff
发明人： Patrick R. Marchand , Gerald G. Pechanek , Edward A. Wolff
IPC分类号： G06F1/08 , G06F1/32 , G06F9/30 , G06F9/38
CPC分类号： G06F1/3203 , G06F1/3237 , G06F9/30036 , G06F9/30101 , G06F9/3853 , G06F9/3885 , G06F9/3891 , Y02D10/128
摘要： A reconfigurable register file system is described. The reconfigurable register file system includes an instruction register for storing an instruction specifying an operational requirement, a reconfigurable register file comprising an odd register file having at least one data read port, and an even register file having at least one data read port. The reconfigurable register file system may further suitably include an execution unit connected to the data read ports of the odd and even register files and port usage control logic connected to the instruction register and the reconfigurable register file to control the odd register file and the even register file port address input so that data read port lines change only as needed to support the operational requirement specified by the instruction. The port usage control logic may further include a gating circuit connected to the reconfigurable register files and a clock input, the gating circuit being operable for gating the clock off so no change of state of the reconfigurable register files occurs for each cycle when change is not necessary and gating the clock on so new data is clocked into the reconfigurable register files for each cycle when change is desired.
摘要翻译：描述可重新配置的寄存器文件系统。可重构寄存器文件系统包括用于存储指定操作要求的指令的指令寄存器，包括具有至少一个数据读取端口的奇数寄存器文件的可重新配置寄存器文件以及具有至少一个数据读取端口的偶数寄存器文件。可重配置寄存器文件系统可以进一步适当地包括连接到奇偶寄存器文件的数据读端口的执行单元和连接到指令寄存器和可重配置寄存器堆的端口使用控制逻辑，以控制奇数寄存器堆和偶寄存器文件端口地址输入，使得数据读取端口线仅在需要时更改以支持指令指定的操作要求。端口使用控制逻辑还可以包括连接到可重新配置的寄存器文件和时钟输入的选通电路，门控电路可操作以关闭时钟，因此当不是变化时，每个周期不会发生可重新配置的寄存器文件的状态改变必要和选通时钟，因此，当需要更改时，每个周期将新数据记录到可重新配置的寄存器文件中。

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