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11. 发明授权

US07477717B2 Input receiver circuit 有权
标题翻译：输入接收电路
公开(公告)号：US07477717B2
公开(公告)日：2009-01-13
申请号：US10831001
申请日：2004-04-23
申请人： Maksim Kuzmenka , Hermann Ruckerbauer
发明人： Maksim Kuzmenka , Hermann Ruckerbauer
IPC分类号： H03M9/00
CPC分类号： H03M9/00
摘要： An input receiver circuit is provided for receiving a noisy high-speed input signal and for generating a plurality of output signals that can be processed at a low acquisition speed compared to the speed of the high-speed input signal. The input receiver circuit includes an input for receiving the high-speed input signal (data), a plurality of integration elements and a switch for connecting the input to one of the plurality of integration elements for integrating the high-speed input signal. The input receiver circuit further includes a plurality of means for receiving one of the integrated high-speed input signals at a time and for outputting one of the plurality of output signals at a time, and a controller for controlling the switch.
摘要翻译：提供输入接收器电路，用于接收噪声高速输入信号并产生与高速输入信号的速度相比可以以低采集速度处理的多个输出信号。输入接收电路包括用于接收高速输入信号（数据）的输入端，多个积分元件和用于将输入连接到多个积分元件中的一个用于积分高速输入信号的开关。输入接收电路还包括多个用于一次接收集成高速输入信号之一并用于一次输出多个输出信号中的一个的装置，以及用于控制开关的控制器。

12. 发明申请

US20060248260A1 Circuit system 审中-公开
标题翻译：电路系统
公开(公告)号：US20060248260A1
公开(公告)日：2006-11-02
申请号：US11392217
申请日：2006-03-29
申请人： Maksim Kuzmenka , Simon Muff , Hermann Ruckerbauer
发明人： Maksim Kuzmenka , Simon Muff , Hermann Ruckerbauer
IPC分类号： G06F12/02
CPC分类号： H03K19/018514 , H03K19/0175 , H03K19/01812
摘要： A circuit system includes a means for controlling a first and a second memory unit by means of a differential control signal. The differential control signal includes a first control signal and a second control signal, which is inverted to the first control signal. Further, the circuit system comprises a differential control signal line, which includes a first signal line for routing the first control signal and a second signal line for routing the second control signal. The first switching unit is connected via the first signal line and the second circuit unit is connected via the second signal line to the means for controlling.
摘要翻译：电路系统包括用于通过差分控制信号控制第一和第二存储器单元的装置。差分控制信号包括第一控制信号和第二控制信号，其被反转到第一控制信号。此外，电路系统包括差分控制信号线，其包括用于路由第一控制信号的第一信号线和用于路由第二控制信号的第二信号线。第一开关单元经由第一信号线连接，第二电路单元经由第二信号线连接到控制装置。

13. 发明授权

US07061784B2 Semiconductor memory module 失效
标题翻译：半导体存储器模块
公开(公告)号：US07061784B2
公开(公告)日：2006-06-13
申请号：US10886814
申请日：2004-07-08
申请人： Andreas Jakobs , Hermann Ruckerbauer , Maksim Kuzmenka
发明人： Andreas Jakobs , Hermann Ruckerbauer , Maksim Kuzmenka
IPC分类号： G11C5/06
CPC分类号： G11C11/4093 , G11C5/063 , G11C7/10
摘要： The invention relates to a semiconductor memory module having at least one memory chip and a buffer chip, which drives clock, address and command signals to the memory chip and drives data signals to, and receives them from, the memory chip via a module-internal clock, address, command and data bus. The buffer chip forms an interface to an external memory main bus. The data bus lines and/or the clock, command and address bus lines are respectively connected to the buffer chip at their two ends and are capable of being driven by the buffer chip from these two ends. Control means are being provided and set up in such a manner that they respectively match the directions of propagation of the data signals and of the clock, command and address signals on the corresponding bus lines during writing and reading.
摘要翻译：本发明涉及一种具有至少一个存储器芯片和缓冲芯片的半导体存储器模块，其将时钟，地址和命令信号驱动到存储器芯片，并且经由模块内部驱动数据信号并从存储器芯片接收它们时钟，地址，命令和数据总线。缓冲芯片形成与外部存储器主总线的接口。数据总线和/或时钟，命令和地址总线分别在两端分别连接到缓冲芯片，并且能够被这两端的缓冲芯片驱动。正在提供和设置控制装置，使得它们在写入和读取期间它们分别匹配数据信号的传播方向以及相应总线上的时钟，命令和地址信号。

14. 发明授权

US06840808B2 Connector for a plurality of switching assemblies with compatible interfaces 有权
标题翻译：具有兼容接口的多个开关组件的连接器
公开(公告)号：US06840808B2
公开(公告)日：2005-01-11
申请号：US10610241
申请日：2003-06-30
申请人： Hermann Ruckerbauer , Maksim Kuzmenka
发明人： Hermann Ruckerbauer , Maksim Kuzmenka
IPC分类号： H01R12/16 , H01R12/18 , H01R12/22 , H01R13/66 , H01R13/68 , H01R24/00
CPC分类号： H01R12/52 , H01R12/716
摘要： A connector is described for fixing a plurality of switching assemblies on a substrate. The connector is also for making contact with the plurality of switching assemblies, which have compatible interfaces. The connector has a plurality of receptacle devices with contact elements and internal contact connections between corresponding contact elements, as a result of which, the length of the connections between the switching assemblies is reduced, signal propagation times are shortened and a higher clock rate for operating the switching assemblies is made possible.
摘要翻译：描述了用于将多个开关组件固定在基板上的连接器。连接器还用于与具有兼容接口的多个开关组件接触。连接器具有多个具有接触元件的插座装置和相应的接触元件之间的内部接触连接，其结果是，开关组件之间的连接长度减小，信号传播时间缩短，操作时钟频率更高开关组件成为可能。

15. 发明授权

US06918778B2 Configuration, plug-in mount and contact element for fixing and contacting switching assemblies on a substrate 失效
标题翻译：配置，插件安装和接触元件，用于固定和接触基板上的开关组件
公开(公告)号：US06918778B2
公开(公告)日：2005-07-19
申请号：US10609871
申请日：2003-06-30
申请人： Hermann Ruckerbauer , Maksim Kuzmenka
发明人： Hermann Ruckerbauer , Maksim Kuzmenka
IPC分类号： H01R12/18 , H01R12/16 , H01R12/22 , H05K1/11 , H01R13/15
CPC分类号： H01R12/85 , H01R12/87 , H01R12/88 , H01R13/658
摘要： Contact elements of a plug-in mount are connected in an electrically conducting manner to conductive contact zones on a surface of a substrate after the plug-in mount has been loaded with a switching assembly and are electrically isolated from the signal lines in the unloaded state. Therefore, higher clock rates for the signals transmitted on the signal lines are made possible in not completely expanded systems having empty mounting locations.
摘要翻译：插入式安装座的接触元件在插入式安装件已经装载有开关组件之后以导电方式连接到衬底表面上的导电接触区域，并且在无负载状态下与信号线电隔离。因此，在不具有空的安装位置的完全扩展的系统中，可以在信号线上传输的信号的较高的时钟速率成为可能。

16. 发明申请

US20050078532A1 Semiconductor memory module 失效
公开(公告)号：US20050078532A1
公开(公告)日：2005-04-14
申请号：US10909205
申请日：2004-07-30
申请人： Hermann Ruckerbauer , Maksim Kuzmenka , Andreas Jakobs
发明人： Hermann Ruckerbauer , Maksim Kuzmenka , Andreas Jakobs
IPC分类号： G11C5/06 , G11C7/22 , G11C11/4076 , G11C7/00
CPC分类号： G11C7/222 , G11C5/063 , G11C7/22 , G11C11/4076
摘要： The invention relates to a semiconductor memory module having a plurality of memory chips and at least one buffer chip, which drives clock signals and command and address signals to the memory chips and also drives data signals to, and receives them from, the memory chips via a module-internal clock, address, command and data signal bus. The buffer chip forms an interface to an external memory main bus and the memory chips are arranged in at least one row. The memory chips have separate writing and reading clock signal inputs for receiving the clock signals and the clock signal lines are routed in at least one loop, via the memory chips, from the buffer chip to the end of each row and from there back to the buffer chip

17. 发明申请

US20050036349A1 Semiconductor memory module 有权
标题翻译：半导体存储器模块
公开(公告)号：US20050036349A1
公开(公告)日：2005-02-17
申请号：US10890934
申请日：2004-07-14
申请人： Andreas Jakobs , Hermann Ruckerbauer , Maksim Kuzmenka
发明人： Andreas Jakobs , Hermann Ruckerbauer , Maksim Kuzmenka
IPC分类号： G11C5/06 , G11C5/02
CPC分类号： G11C29/028 , G11C5/063 , G11C29/50012
摘要： The invention relates to a semiconductor memory module having a plurality of memory chips arranged next to one another in a row. The memory module has a module-internal clock, command/address and data bus which transfers clock signal, command and address signals and also data signals from a memory controller device to the memory chips and data signals from the memory chips to the memory controller device. The memory module has respective clock, command/address and data signal lines. The clock signal lines comprise two differential clock signal lines which, at their end opposite to the memory controller device are either open or connected to one another by a short-circuiting bridge. The memory chips, during a write operation, synchronize the write data with the clock signal running from the memory controller device to the end of the clock signal line and, during a read operation, output the read data synchronously with the clock signal reflected from the open or short-circuited end of the clock signal lines.
摘要翻译：本发明涉及一种半导体存储器模块，该半导体存储器模块具有彼此排成一列的多个存储器芯片。存储器模块具有模块内部时钟，命令/地址和数据总线，其将时钟信号，命令和地址信号以及数据信号从存储器控制器设备传送到存储器芯片，并将数据信号从存储器芯片传送到存储器控制器设备。存储器模块具有各自的时钟，命令/地址和数据信号线。时钟信号线包括两个差分时钟信号线，它们在其与存储器控制器装置相对的端部通过短路桥断开或彼此连接。在写入操作期间，存储器芯片将写入数据与从存储器控制器设备运行到时钟信号线的时钟信号同步，并且在读取操作期间，与从该存储器控制器设备反射的时钟信号同步地输出读取数据开路或短路的时钟信号线。

18. 发明申请

US20050024963A1 Semiconductor memory module 失效
标题翻译：半导体存储器模块
公开(公告)号：US20050024963A1
公开(公告)日：2005-02-03
申请号：US10886814
申请日：2004-07-08
申请人： Andreas Jakobs , Hermann Ruckerbauer , Maksim Kuzmenka
发明人： Andreas Jakobs , Hermann Ruckerbauer , Maksim Kuzmenka
IPC分类号： G11C5/06 , G11C7/10 , G11C11/4093 , G11C7/00
CPC分类号： G11C11/4093 , G11C5/063 , G11C7/10
摘要： The invention relates to a semiconductor memory module having at least one memory chip and a buffer chip, which drives clock, address and command signals to the memory chip and drives data signals to, and receives them from, the memory chip via a module-internal clock, address, command and data bus. The buffer chip forms an interface to an external memory main bus. The data bus lines and/or the clock, command and address bus lines are respectively connected to the buffer chip at their two ends and are capable of being driven by the buffer chip from these two ends. Control means are being provided and set up in such a manner that they respectively match the directions of propagation of the data signals and of the clock, command and address signals on the corresponding bus lines during writing and reading.
摘要翻译：本发明涉及一种具有至少一个存储器芯片和缓冲芯片的半导体存储器模块，其将时钟，地址和命令信号驱动到存储器芯片，并且经由模块内部驱动数据信号并从存储器芯片接收它们时钟，地址，命令和数据总线。缓冲芯片形成与外部存储器主总线的接口。数据总线和/或时钟，命令和地址总线分别在两端分别连接到缓冲芯片，并且能够被这两端的缓冲芯片驱动。正在提供和设置控制装置，使得它们在写入和读取期间它们分别匹配数据信号的传播方向以及相应总线上的时钟，命令和地址信号。

19. 发明申请

US20130155752A1 WIRING CONFIGURATION OF A BUS SYSTEM AND POWER WIRES IN A MEMORY CHIP 有权
标题翻译：总线系统配线和内存芯片中的电源线
公开(公告)号：US20130155752A1
公开(公告)日：2013-06-20
申请号：US13327057
申请日：2011-12-15
申请人： Maksim Kuzmenka , Dirk Scheideler , Kai Schiller
发明人： Maksim Kuzmenka , Dirk Scheideler , Kai Schiller
IPC分类号： G11C5/06 , H05K7/02
CPC分类号： G11C7/20 , G11C5/025 , G11C5/04 , G11C5/063 , G11C5/148 , G11C7/18 , G11C11/4097 , H03K19/1776
摘要： Devices and circuits for wiring configurations of a bus system and power supply wires in a memory chip with improved power efficiencies. For example, the effective resistance on the power supply wires can be reduced by utilizing non-active bus wires as additional power wires connected in parallel with the other supply wires. Further, these non-active bus wires can reduce or prevent parasitic couplings and cross-talk effects between neighboring sensitive wires, thereby improving the performance of the chip.
摘要翻译：用于布置总线系统配置的设备和电路以及提供功率效率的存储芯片中的电源线。例如，可以通过利用非有源总线作为与其它电源线并联连接的附加电源线来减小电源线上的有效电阻。此外，这些非有源母线可以减少或防止相邻敏感线之间的寄生耦合和串扰效应，从而提高芯片的性能。

20. 发明授权

US07525357B2 Circuit and method for adjusting a voltage drop 有权
标题翻译：用于调节电压降的电路和方法
公开(公告)号：US07525357B2
公开(公告)日：2009-04-28
申请号：US11638324
申请日：2006-12-13
申请人： Maksim Kuzmenka
发明人： Maksim Kuzmenka
IPC分类号： H03K3/017
CPC分类号： H04L25/0278
摘要： An integrated circuit includes a circuit for adjusting a voltage drop. The circuit includes a reference voltage node, an output node and a driver circuit coupled between the reference voltage node and the output node. The driver circuit includes an impedance causing a current flow through the driver circuit when a reference voltage is applied to the reference voltage node. A current source is coupled to the driver circuit to impress an adjustment current based on a control current such that the current flow through the driver circuit is adjusted to yield a desired voltage drop across the driver circuit.
摘要翻译：集成电路包括用于调整电压降的电路。电路包括参考电压节点，输出节点和耦合在参考电压节点和输出节点之间的驱动器电路。当参考电压施加到参考电压节点时，驱动器电路包括引起电流流过驱动器电路的阻抗。电流源耦合到驱动器电路，以基于控制电流来压制调节电流，使得调节通过驱动器电路的电流以产生跨越驱动器电路的期望电压降。

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