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11. 发明授权

US08725975B2 Progressive memory initialization with waitpoints 有权
标题翻译：具有等待点的逐行内存初始化
公开(公告)号：US08725975B2
公开(公告)日：2014-05-13
申请号：US11619294
申请日：2007-01-03
申请人： William C. Moyer
发明人： William C. Moyer
IPC分类号： G06F3/06
CPC分类号： G06F3/061 , G06F3/0632 , G06F3/0673 , G06F11/1008
摘要： A method includes initializing a counter value of a hardware counter. The method further includes iteratively adjusting the counter value and storing an initialization value to a memory location using a memory address based on the counter value. The method also includes generating an interrupt request based on a comparison of the counter value to a waitpoint value concurrent with iteratively adjusting and storing. A memory device includes a memory array and an initialization module. The initialization module includes a counter, a register to store a waitpoint value, write logic configured to write an initialization value to a memory location of the memory array associated with a memory address that is based on a counter value of the counter, and interrupt logic configured to generate an interrupt request based on a comparison of the counter value of the counter to the waitpoint value.
摘要翻译：一种方法包括初始化硬件计数器的计数器值。该方法还包括迭代地调整计数器值，并且使用基于计数器值的存储器地址将初始化值存储到存储器位置。该方法还包括基于通过迭代调整和存储同时计算值与等待点值的比较来产生中断请求。存储器件包括存储器阵列和初始化模块。初始化模块包括计数器，用于存储等待点值的寄存器，被配置为将初始化值写入与基于计数器的计数器值的存储器地址相关联的存储器阵列的存储器位置的写入逻辑，以及中断逻辑被配置为基于计数器的计数器值与等待点值的比较来生成中断请求。

12. 发明申请

US20140052931A1 Data Type Dependent Memory Scrubbing 有权
标题翻译：数据类型依赖内存清理
公开(公告)号：US20140052931A1
公开(公告)日：2014-02-20
申请号：US13588243
申请日：2012-08-17
申请人： Ravindraraj Ramaraju , William C. Moyer , Andrew C. Russell
发明人： Ravindraraj Ramaraju , William C. Moyer , Andrew C. Russell
IPC分类号： G06F12/08
CPC分类号： G06F12/0895 , G06F11/106 , G06F11/1064 , Y02D10/13
摘要： A method for controlling a memory scrubbing rate based on content of the status bit of a tag array of a cache memory. More specifically, the tag array of a cache memory is scrubbed at smaller interval than the scrubbing rate of the storage arrays of the cache. This increased scrubbing rate is in appreciation for the importance of maintaining integrity of tag data. Based on the content of the status bit of the tag array which indicates modified, the corresponding data entry in the cache storage array is scrubbed accordingly. If the modified bit is set, then the entry in the storage array is scrubbed after processing the tag entry. If the modified bit is not set, then the storage array is scrubbed at a predetermined scrubbing interval.
摘要翻译：一种用于基于高速缓冲存储器的标签阵列的状态位的内容来控制存储器擦除速率的方法。更具体地说，高速缓冲存储器的标签阵列以比缓存的存储阵列的擦除速率更小的间隔进行擦除。对于保持标签数据完整性的重要性，这种提高的清洗率是值得赞赏的。基于指示被修改的标签阵列的状态位的内容，相应地擦除缓存存储阵列中的相应数据条目。如果修改的位被设置，则在处理标签条目之后擦除存储阵列中的条目。如果未设置修改的位，则以预定的擦洗间隔擦除存储阵列。

13. 发明授权

US08639895B2 Systems and methods for memory region descriptor attribute override 有权
标题翻译：内存区域描述符属性覆盖的系统和方法
公开(公告)号：US08639895B2
公开(公告)日：2014-01-28
申请号：US13182734
申请日：2011-07-14
申请人： William C. Moyer
发明人： William C. Moyer
IPC分类号： G06F12/14
CPC分类号： G06F12/1441 , G06F12/0888 , G06F12/10
摘要： A memory protection unit (MPU) is configured to store a plurality of region descriptor entries, each region descriptor entry defining an address region of a memory, an attribute corresponding to the region, and an attribute override control corresponding to the attribute. A memory access request to a memory address is received and determined to be within a first address region defined by a first region descriptor entry and within a second address region defined by a second region descriptor entry. When the attribute override control of the first region descriptor entry indicates that override is to be performed, the value of the attribute of the first region descriptor entry is applied for the memory access. When the attribute override control of the second region descriptor entry indicates that override is to be performed, the value of the attribute of the second region descriptor entry is applied for the memory access.
摘要翻译：存储器保护单元（MPU）被配置为存储多个区域描述符条目，定义存储器的地址区域的每个区域描述符条目，对应于该区域的属性以及与该属性相对应的属性覆盖控制。对存储器地址的存储器访问请求被接收并被确定为在由第一区域描述符条目定义的第一地址区域内以及由第二区域描述符条目定义的第二地址区域内。当第一区域描述符条目的属性重写控制指示要执行覆盖时，第一区域描述符条目的属性值被应用于存储器访问。当第二区域描述符条目的属性覆盖控制指示要执行覆盖时，将应用第二区域描述符条目的属性的值用于存储器访问。

14. 发明授权

US08635497B2 Data processing system having a sequence processing unit and method of operation 有权
标题翻译：数据处理系统具有序列处理单元和操作方法
公开(公告)号：US08635497B2
公开(公告)日：2014-01-21
申请号：US13170286
申请日：2011-06-28
申请人： Gary L. Miller , Mark Maiolani , William C. Moyer
发明人： Gary L. Miller , Mark Maiolani , William C. Moyer
IPC分类号： G06F11/00
CPC分类号： G06F11/364 , G06F11/3471 , G06F11/348 , G06F11/349 , G06F2201/88
摘要： A system includes one or more processors; one or more trace debug circuits configured to monitor one or more of instruction, data, and watchpoint buses of the one or more processors, and record information determined from said monitoring; and a sequence processing unit configured to provide a control signal to a trace debug circuit of the one or more trace debug circuits, wherein in response to the control signal, the trace debug circuit controls one or more of said monitoring and recording, and a system on a chip comprises the one or more processors, the one or more trace debug circuits, and the sequence processing unit.
摘要翻译：系统包括一个或多个处理器; 一个或多个跟踪调试电路，被配置为监视所述一个或多个处理器的指令，数据和观察点总线中的一个或多个，并且记录从所述监视确定的信息; 以及序列处理单元，被配置为向所述一个或多个跟踪调试电路的跟踪调试电路提供控制信号，其中响应于所述控制信号，所述跟踪调试电路控制所述监视和记录中的一个或多个，以及系统在芯片上包括一个或多个处理器，一个或多个跟踪调试电路和序列处理单元。

15. 发明授权

US08624627B1 Method and device for low power control 有权
标题翻译：低功耗控制方法和装置
公开(公告)号：US08624627B1
公开(公告)日：2014-01-07
申请号：US13538200
申请日：2012-06-29
申请人： Anis M. Jarrar , William C. Moyer , Jim C. Nash
发明人： Anis M. Jarrar , William C. Moyer , Jim C. Nash
IPC分类号： H01L25/00
CPC分类号： G06F1/3287 , G06F1/3228 , Y02D10/171
摘要： The present application discloses an integrated circuit having a power controller that can manage power modes of a system when the system is in a low power mode. According to an embodiment, a power controller is built into an input/output (I/O) region of and integrated circuit die, wherein the I/O region is outside the main logic area of the die. The same supply voltage that powers the I/O region of the device can power the power controller. The power controller can operate to transition the integrated circuit die between power modes by transitioning logic modules of the integrated circuit between power states without intervention by the logic modules.
摘要翻译：本申请公开了一种具有功率控制器的集成电路，其能够在系统处于低功率模式时管理系统的功率模式。根据实施例，功率控制器内置在集成电路管芯的输入/输出（I / O）区域中，其中I / O区域在管芯的主逻辑区域之外。为器件的I / O区域供电的相同电源电压可为电源控制器供电。功率控制器可以通过在功率状态之间转换集成电路的逻辑模块而不用逻辑模块进行干预来操作以在功率模式之间转换集成电路管芯。

16. 发明申请

US20140002132A1 METHOD AND DEVICE FOR LOW POWER CONTROL 有权
标题翻译：低功率控制的方法和装置
公开(公告)号：US20140002132A1
公开(公告)日：2014-01-02
申请号：US13538200
申请日：2012-06-29
申请人： Anis M. Jarrar , William C. Moyer , Jim C. Nash
发明人： Anis M. Jarrar , William C. Moyer , Jim C. Nash
IPC分类号： H03K19/0175
CPC分类号： G06F1/3287 , G06F1/3228 , Y02D10/171
摘要： The present application discloses an integrated circuit having a power controller that can manage power modes of a system when the system is in a low power mode. According to an embodiment, a power controller is built into an input/output (I/O) region of and integrated circuit die, wherein the I/O region is outside the main logic area of the die. The same supply voltage that powers the I/O region of the device can power the power controller. The power controller can operate to transition the integrated circuit die between power modes by transitioning logic modules of the integrated circuit between power states without intervention by the logic modules.
摘要翻译：本申请公开了一种具有功率控制器的集成电路，其能够在系统处于低功率模式时管理系统的功率模式。根据实施例，功率控制器内置在集成电路管芯的输入/输出（I / O）区域中，其中I / O区域在管芯的主逻辑区域之外。为器件的I / O区域供电的相同电源电压可为电源控制器供电。功率控制器可以通过在功率状态之间转换集成电路的逻辑模块而不用逻辑模块进行干预来操作以在功率模式之间转换集成电路管芯。

17. 发明授权

US08572345B2 Memory management unit (MMU) having region descriptor globalization controls and method of operation 有权
标题翻译：具有区域描述符全球化控制的内存管理单元（MMU）和操作方法
公开(公告)号：US08572345B2
公开(公告)日：2013-10-29
申请号：US13234305
申请日：2011-09-16
申请人： William C. Moyer
发明人： William C. Moyer
IPC分类号： G06F12/00
CPC分类号： G06F12/1483
摘要： Embodiments of computer processing systems and methods are provided that include a memory protection unit (MPU), and a plurality of region descriptors associated with the MPU. The region descriptors include address range and translation identifier values for a respective region of memory. Control logic determines whether a translation identifier control indicator is in a first state, and if the translation identifier control indicator is in the first state, the control logic allows a first process being executed by the processing system to access a memory region allocated to a second process being executed by the processing system.
摘要翻译：提供了包括存储器保护单元（MPU）和与MPU相关联的多个区域描述符的计算机处理系统和方法的实施例。区域描述符包括存储器的相应区域的地址范围和翻译标识符值。控制逻辑确定翻译标识符控制指示符是否处于第一状态，并且如果转换标识符控制指示符处于第一状态，则控制逻辑允许由处理系统执行的第一进程访问分配给第二状态的存储器区域处理由处理系统执行。

18. 发明授权

US08566836B2 Multi-core system on chip 有权
标题翻译：多芯片系统芯片
公开(公告)号：US08566836B2
公开(公告)日：2013-10-22
申请号：US12618311
申请日：2009-11-13
申请人： Ravindraraj Ramaraju , David R. Bearden , William C. Moyer
发明人： Ravindraraj Ramaraju , David R. Bearden , William C. Moyer
IPC分类号： G06F9/46 , G06F7/38
CPC分类号： G06F9/5044 , Y02D10/22
摘要： A multi-core system on a chip (200) is described in which a speed information for each core (210, 220, 230, 240), such as the maximum operation speed (Fmax), is extracted and stored in a storage device, such as a device control registry (215), where it may be accessed and used by the operating system when allocating workload among the cores by selecting the fasted core (e.g, 210) to run any applications or tasks that can not be executed on a plurality of cores.
摘要翻译：描述了一种芯片上的多核系统（200），其中提取每个核心（210,220,230,240）的速度信息（如最大运行速度（Fmax））并将其存储在存储装置中，例如设备控制注册表（215），其中当通过选择禁止的核心（例如，210）来运行任何不能执行的应用程序或任务时，操作系统可以在操作系统之间分配工作负载时，访问和使用它们多个核心。

19. 发明授权

US08566672B2 Selective checkbit modification for error correction 有权
标题翻译：用于纠错的选择性校验码修改
公开(公告)号：US08566672B2
公开(公告)日：2013-10-22
申请号：US13053962
申请日：2011-03-22
申请人： William C. Moyer , Joseph C. Circello
发明人： William C. Moyer , Joseph C. Circello
IPC分类号： G11C29/00
CPC分类号： G06F11/1016 , G11C29/52 , G11C2029/0411
摘要： Error correction code (ECC) checkbits are generated for each write access to a memory address based on both the data to be written (the write data) and the memory address. The ECC checkbits are stored with the data and, in response to a read access at the memory address, are employed to check for errors in both the address and the data provided in response to the read access (the read data). The ECC checkbit generation process can result, for particular memory addresses, in checkbits that can incorrectly indicate whether errors are present in the read data. Accordingly, the checkbits can be selectively inverted based on the memory address so that the checkbit pattern will not result in an incorrect error detection or correction.
摘要翻译：基于要写入的数据（写入数据）和存储器地址的每次对存储器地址的写入生成纠错码（ECC）校验码。 ECC校验位与数据一起存储，并且响应于在存储器地址处的读取访问来检查响应于读取访问（读取数据）提供的地址和数据中的错误。对于特定的存储器地址，ECC校验位生成过程可能导致错误地指示读取数据中是否存在错误的校验位。因此，可以基于存储器地址选择性地反转校验位，使得校验位模式不会导致不正确的错误检测或校正。

20. 发明授权

US08504777B2 Data processor for processing decorated instructions with cache bypass 有权
标题翻译：用于处理具有缓存旁路的装饰指令的数据处理器
公开(公告)号：US08504777B2
公开(公告)日：2013-08-06
申请号：US12886641
申请日：2010-09-21
申请人： William C. Moyer
发明人： William C. Moyer
IPC分类号： G06F13/20
CPC分类号： G06F9/3004 , G06F9/30047 , G06F9/3834 , G06F12/0888
摘要： A method includes determining if a data processing instruction is a decorated access instruction with cache bypass, and determining if the data processing instruction generates a cache hit to a cache. When the data processing instruction is determined to be a decorated access instruction with cache bypass and the data processing instruction is determined to generate a cache hit, the method further includes invalidating a cache entry of the cache associated with the cache hit; and performing by a memory controller of the memory, a decoration operation specified by the data processor instruction on a location in the memory designated by a target address of the data processor instruction, wherein the performing the decorated access includes the memory controller performing a read of a value of the location in memory, modifying the value to generate a modified value, and writing the modified value to the location.
摘要翻译：一种方法包括确定数据处理指令是否是具有高速缓存旁路的装饰访问指令，以及确定数据处理指令是否生成对高速缓存的缓存命中。当数据处理指令被确定为具有缓存旁路的装饰访问指令并且确定数据处理指令以产生高速缓存命中时，该方法还包括使与高速缓存命中相关联的缓存的高速缓存条目无效; 以及由存储器的存储器控制器执行由数据处理器指令指定的由数据处理器指令的目标地址指定的存储器中的位置的装饰操作，其中，执行装饰访问包括存储器控制器执行读取存储器中位置的值，修改值以生成修改值，并将修改后的值写入位置。

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