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11. 发明申请

US20060186530A1 Memory device power distribution in memory assemblies 审中-公开
标题翻译：存储器件中的存储器件功率分配
公开(公告)号：US20060186530A1
公开(公告)日：2006-08-24
申请号：US11403774
申请日：2006-04-13
申请人： Frankie Roohparvar
发明人： Frankie Roohparvar
IPC分类号： H01L23/52
CPC分类号： G11C5/025 , G11C5/14 , H01L23/4951 , H01L23/50 , H01L2924/0002 , H01L2924/00
摘要： A memory assembly has a memory package with a plurality of interconnect pins having a plurality of first power input pins located on a first side of the memory package, the first power input pins independent of each other. A lead-over-chip leadframe has a plurality of leads coupled to the plurality of interconnect pins in a one-to-one relationship. A memory chip is coupled to the plurality of leads and has substrate with a memory device fabricated thereon and a plurality of first power input chip bond pads fabricated thereon and coupled to the memory device. Each first power input chip bond pad is further coupled to one of the first power input pins through one of the leads.
摘要翻译：存储器组件具有存储器封装，其具有多个互连引脚，其具有位于存储器封装的第一侧上的多个第一电源输入引脚，第一电源输入引脚彼此独立。引线框架引线框架具有以一对一关系耦合到多个互连引脚的多个引线。存储器芯片耦合到多个引线并且具有在其上制造的存储器件的衬底和在其上制造并耦合到存储器件的多个第一功率输入芯片接合焊盘。每个第一功率输入芯片接合焊盘还通过一个引线耦合到第一电源输入引脚之一。

12. 发明申请

US20060034126A1 Preconditioning of defective and redundant columns in a memory device 有权
公开(公告)号：US20060034126A1
公开(公告)日：2006-02-16
申请号：US11255646
申请日：2005-10-21
申请人： Frankie Roohparvar
发明人： Frankie Roohparvar
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： G11C16/107 , G11C16/16 , G11C16/3404 , G11C29/82
摘要： A redundant column is mapped to a defective or over-erased column in the memory array. When an erase command occurs, both the redundant column and the defective or over-erased column are preconditioned by preprogramming them. The defective or over-erased column is preprogrammed and verified a predetermined number of times or until the verification passes. The redundant and defective or over-erased columns are then erased with the rest of the memory block.

13. 发明申请

US20060002190A1 Reduction of adjacent floating gate data pattern sensitivity 有权
公开(公告)号：US20060002190A1
公开(公告)日：2006-01-05
申请号：US10881636
申请日：2004-06-30
申请人： Frankie Roohparvar
发明人： Frankie Roohparvar
IPC分类号： G11C11/34
CPC分类号： G11C16/3418
摘要： The method for programming non-volatile memory cells erases the memory cells to be programmed. The memory cells are then programmed to a reduced floating gate voltage that takes into account capacitive coupling between the floating gates of adjacent memory cells. In one embodiment, the programming method programs and verifies a first memory cell to the reduced floating gate voltage, programs and verifies an adjacent memory cell to the reduced floating gate voltage, and verifies the first memory cell to an increased floating gate voltage that is greater than the reduced floating gate voltage.

14. 发明申请

US20050276119A1 Memory block erasing in a flash memory device 有权
公开(公告)号：US20050276119A1
公开(公告)日：2005-12-15
申请号：US11210083
申请日：2005-08-23
申请人： Ebrahim Abedifard , Frankie Roohparvar
发明人： Ebrahim Abedifard , Frankie Roohparvar
IPC分类号： G11C11/34 , G11C16/04 , G11C16/16 , G11C16/34
CPC分类号： G11C16/345 , G11C16/16 , G11C16/3404 , G11C16/3409 , G11C16/344
摘要： An erase pulse is applied to the memory block to be erased. An erase verification operation is performed to verify that each memory cell of the memory block is erased. If a memory cell has a current less than a first sense amplifier current reference level, additional erase pulses are applied to that cell until either the erase current is in the range of 30-40 μA or a maximum quantity of erase pulses have been applied. A leakage check is performed to determine if any cells have been overerased. If a cell has an erase current greater than or equal to a second sense amplifier current reference level, soft programming pulses are applied to the cell until either its erase current is less than the second reference level or a maximum quantity of soft program pulses have been applied.

15. 发明申请

US20050259506A1 Synchronous flash memory 审中-公开
标题翻译：同步闪存
公开(公告)号：US20050259506A1
公开(公告)日：2005-11-24
申请号：US11174761
申请日：2005-07-05
申请人： Frankie Roohparvar
发明人： Frankie Roohparvar
IPC分类号： G06F13/16 , G11C7/10 , G11C8/18 , G11C16/10 , G11C8/00
CPC分类号： G06F13/1668 , G11C7/10 , G11C8/18 , G11C16/10 , G11C2207/105
摘要： A computer system comprises a memory controller and a synchronous non-volatile memory device coupled to the memory controller via a main memory bus. The synchronous non-volatile memory device has external interconnects arranged in a manner that corresponds to interconnects of a synchronous dynamic random access memory device. The synchronous flash memory device, however, comprises a reset connection, and a Vccp power supply connection correspond to first and second no-connect (NC) interconnect pins of the synchronous dynamic random access memory. In one embodiment, the synchronous non-volatile memory device has a command interface comprising a write enable connection (WE#) to receive a write enable signal, a column address strobe connection (CAS#) to receive a column address strobe signal, a row address strobe connection (RAS#) to receive a row address strobe signal, and a chip select connection (CS#) to receive a chip select signal.
摘要翻译：计算机系统包括存储器控制器和经由主存储器总线耦合到存储器控制器的同步非易失性存储器件。同步非易失性存储器件具有以对应于同步动态随机存取存储器件的互连的方式布置的外部互连。然而，同步闪速存储器件包括复位连接，并且Vccp电源连接对应于同步动态随机存取存储器的第一和第二非连接（NC）互连引脚。在一个实施例中，同步非易失性存储器件具有命令接口，其包括用于接收写使能信号的写使能连接（WE＃），用于接收列地址选通信号的列地址选通连接（CAS＃），行地址选通信号地址选通连接（RAS＃）以接收行地址选通信号，以及芯片选择连接（CS＃）以接收片选信号。

16. 发明申请

US20050141282A1 Preconditioning global bitlines 有权
公开(公告)号：US20050141282A1
公开(公告)日：2005-06-30
申请号：US11062661
申请日：2005-02-22
申请人： Ebrahim Abedifard , Frankie Roohparvar
发明人： Ebrahim Abedifard , Frankie Roohparvar
IPC分类号： G11C7/12 , G11C7/18 , G11C16/24 , G11C11/34
CPC分类号： G11C7/12 , G11C7/18 , G11C16/24
摘要： A method and apparatus for discharging global bitlines in a flash memory to a voltage sufficiently low to avoid drain disturb for non-selected cells in a programming operation. A discharge device allows discharge of global bitlines coupled to local bitlines before a programming operation.

17. 发明申请

US20050028054A1 Memory with element redundancy 失效
公开(公告)号：US20050028054A1
公开(公告)日：2005-02-03
申请号：US10932968
申请日：2004-09-02
申请人： Frankie Roohparvar
发明人： Frankie Roohparvar
IPC分类号： G11C29/00 , G11C29/46 , G11C11/34 , G11C16/06
CPC分类号： G11C29/82 , G11C29/46
摘要： A memory device to perform an erase operation algorithm that specifically deals with different types of defects in a memory array. The memory array of one embodiment of the present invention has primary and redundant elements. A register is used for each redundant element to store the address of a defective primary element and an error code that indicates the type of defect in the defective primary element. Control circuitry is used to control memory operations to the memory array. The control circuitry performs an erase operation algorithm that is specific to an error code when a defective primary element is addressed during an erase operation.

18. 发明申请

US20050024980A1 Synchronous flash memory with non-volatile mode register 有权
标题翻译：具有非易失性模式寄存器的同步闪存
公开(公告)号：US20050024980A1
公开(公告)日：2005-02-03
申请号：US10930159
申请日：2004-08-31
申请人： Frankie Roohparvar
发明人： Frankie Roohparvar
IPC分类号： G06F13/16 , G11C7/10 , G11C16/26 , G11C7/00
CPC分类号： G06F13/1694 , G11C7/1045 , G11C7/1072 , G11C16/26
摘要： A synchronous flash memory includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The memory device performs memory access operations using mode data that can be stored in a non-volatile mode register. The mode data can be copied into a volatile mode register. Both the non-volatile and volatile mode register can be edited during operation.
摘要翻译：同步闪速存储器包括非易失性存储器单元阵列。存储器件具有与SDRAM兼容的封装配置。存储器件使用可以存储在非易失性模式寄存器中的模式数据来执行存储器存取操作。模式数据可以复制到易失性模式寄存器。非易失性和易失性模式寄存器都可以在操作过程中进行编辑。

19. 发明授权

US06621751B1 Method and apparatus for programming row redundancy fuses so decoding matches internal pattern of a memory array 有权
标题翻译：用于编程行冗余保险丝的方法和装置，因此解码匹配存储器阵列的内部模式
公开(公告)号：US06621751B1
公开(公告)日：2003-09-16
申请号：US10160063
申请日：2002-06-04
申请人： Ebrahim Abedifard , Frankie Roohparvar
发明人： Ebrahim Abedifard , Frankie Roohparvar
IPC分类号： G11C700
CPC分类号： G11C29/806 , G11C29/24
摘要： A memory device includes circuitry for replacing row pairs of primary memory having odd-even or even-odd addresses with rows of redundant memory having a corresponding odd-even or even-odd address pairing. The replacement memory rows maintain the odd-even address pairing of the primary memory rows being replaced which facilitates memory testing. The memory is loaded with a uniform test pattern, such as a checkerboard. When adjacent row pairs found to be defective are replaced with a corresponding pair of redundant memory rows, the uniform checkerboard pattern is maintained. Consequently, it is not necessary to load the test pattern into the redundant memory rows after replacement, thereby reducing the number of process steps and time required.
摘要翻译：存储器件包括用于用具有奇数或偶数奇偶校验的冗余存储器行替换具有奇偶或偶奇数地址的行存储器对的电路。替换存储器行保持被替换的主存储器行的奇偶数地址配对，这有助于存储器测试。存储器装载有统一的测试图案，例如棋盘。当发现有缺陷的相邻行对被相应的一对冗余存储器行替换时，维持统一的棋盘图案。因此，不需要在更换之后将测试图案加载到冗余存储器行中，从而减少处理步骤的数量和所需的时间。

20. 发明授权

US6052321A Circuit and method for performing test on memory array cells using external sense amplifier reference current 有权
标题翻译：使用外部读出放大器参考电流对存储器阵列单元执行测试的电路和方法
公开(公告)号：US6052321A
公开(公告)日：2000-04-18
申请号：US146295
申请日：1998-09-03
申请人： Frankie Roohparvar
发明人： Frankie Roohparvar
IPC分类号： G11C7/00 , G11C29/00
CPC分类号： G11C7/14 , G11C29/1201 , G11C29/48 , G11C29/50 , G11C29/50004 , G11C16/04
摘要： An integrated memory circuit (chip) and methods for testing the chip. The chip has an array of memory cells, a sense amplifier for reading selected ones of the cells, and a switch having a first state allowing an external device connected to an external pad to sink a reference current from the sense amplifier and a second state disconnecting the pad from the sense amplifier (so that an internally generated reference current can be supplied to the sense amplifier with the switch in the second state). In the first state, the switch preferably is tolerant of a broad and continuous range of voltages on the pad. In some test modes, cells are read using a sense amplifier of the chip while selected voltages are applied to each cell and external equipment sinks reference current flowing from the sense amplifier through an external pad, thus sensing data from each cell with all the timing constraints usually placed on a read of the cell in the normal mode. In one test mode, all wordlines of the array are disabled and a read cycle is performed to measure all columns of the array sequentially while an external reference current flows between external test equipment and a sense amplifier used for performing the read cycle, and the sense amplifier output indicates whether one or more of the columns has leaky cells.
摘要翻译：集成存储器电路（芯片）和芯片测试方法。芯片具有存储单元阵列，用于读取选定单元的读出放大器，以及具有允许连接到外部焊盘的外部设备从读出放大器吸收参考电流的第一状态的开关和第二状态断开来自读出放大器的焊盘（使得内部产生的参考电流可以被提供给具有第二状态的开关的读出放大器）。在第一状态下，开关优选地容忍焊盘上的广泛且连续的电压范围。在一些测试模式下，使用芯片的读出放大器读取单元，同时将选择的电压施加到每个单元，并且外部设备通过外部焊盘吸收从读出放大器流出的参考电流，从而以所有时序约束感测来自每个单元的数据通常放置在正常模式下的单元读取。在一个测试模式中，阵列的所有字线被禁用，并且执行读周期以顺序测量阵列的所有列，而外部参考电流在外部测试设备和用于执行读周期的读出放大器之间流动放大器输出指示一个或多个列是否有泄漏单元。

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