专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US08441381B2 Gate leakage compensation in a current mirror 有权
标题翻译：电流镜中的门漏电补偿
公开(公告)号：US08441381B2
公开(公告)日：2013-05-14
申请号：US13246319
申请日：2011-09-27
申请人： Ovidiu Bajdechi , Tom W. Kwan
发明人： Ovidiu Bajdechi , Tom W. Kwan
IPC分类号： H03M1/00
CPC分类号： G05F3/08 , G05F3/267 , H03M1/0607 , H03M1/66
摘要： A method and apparatus is disclosed to compensate for gate leakage currents of thin oxide devices that have very thin oxide layers in a current mirror of a digital-to-analog converter (DAC). The DAC converts a digital input signal from a digital representation in a digital signaling domain to an analog representation in an analog signaling domain to provide an analog output signal. The DAC uses one or more transistors to convert the digital input signal from the digital representation to the analog representation. These transistors are typically implemented using thin oxide devices that have very thin oxide layers and corresponding gate leakage currents that are associated with these very thin oxide layers. The current-steering DAC provides these gate leakage currents independent of its corresponding reference source without any substantial affect upon its full scale output.
摘要翻译：公开了一种用于补偿在数模转换器（DAC）的电流镜中具有非常薄的氧化物层的薄氧化物器件的栅极泄漏电流的方法和装置。 DAC将数字输入信号从数字信号域中的数字表示转换为模拟信号域中的模拟表示，以提供模拟输出信号。 DAC使用一个或多个晶体管将数字输入信号从数字表示转换为模拟表示。这些晶体管通常使用具有与这些非常薄的氧化物层相关联的非常薄的氧化物层和相应的栅极泄漏电流的薄氧化物器件来实现。电流导向DAC提供独立于其相应参考源的这些栅极泄漏电流，而对其满量程输出没有任何实质影响。

12. 发明授权

US07859338B2 Compact low-power class AB amplifier 有权
标题翻译：紧凑型低功率AB类放大器
公开(公告)号：US07859338B2
公开(公告)日：2010-12-28
申请号：US12177523
申请日：2008-07-22
申请人： Ovidiu Bajdechi , Christopher Michael Ward
发明人： Ovidiu Bajdechi , Christopher Michael Ward
IPC分类号： H03F3/45
CPC分类号： H03F3/45192 , H03F1/0205 , H03F1/083 , H03F3/3023 , H03F3/45183 , H03F2200/153 , H03F2203/30015 , H03F2203/30033 , H03F2203/30084 , H03F2203/30117 , H03F2203/45292 , H03F2203/45626
摘要： A compact low-power class AB power amplifier design is provided. In an embodiment, the amplifier design eliminates an intermediate stage that couples an input stage and a biasing mesh of the amplifier. In another embodiment, the amplifier design reuses a tail current from the input stage to bias the biasing mesh. Accordingly, a much higher power efficiency can be achieved using the proposed amplifier design compared to conventional class AB amplifiers. Further, the proposed amplifier design is extremely compact and occupies a small silicon area.
摘要翻译：提供紧凑型低功耗AB类功率放大器设计。在一个实施例中，放大器设计消除了耦合输入级和放大器的偏置网格的中间级。在另一个实施例中，放大器设计重新使用来自输入级的尾部电流来偏置偏置网。因此，与传统的AB类放大器相比，使用所提出的放大器设计可以实现更高的功率效率。此外，所提出的放大器设计非常紧凑，占用小的硅面积。

13. 发明授权

US07605728B2 Method for calibrating a multi-bit digital-to-analog converter, multi-bit digital-to-analog converter in which this method is applied and converter provided with such a multi-bit digital-to-analog converter 有权
标题翻译：用于校准多位数模转换器的方法，其中应用该方法的多位数模转换器和具有这种多位数模转换器的转换器
公开(公告)号：US07605728B2
公开(公告)日：2009-10-20
申请号：US10571949
申请日：2004-09-13
申请人： Lucien Johannes Breems , Ovidiu Bajdechi
发明人： Lucien Johannes Breems , Ovidiu Bajdechi
IPC分类号： H03M1/10
CPC分类号： H03M1/1004
摘要： In a method for calibrating a multi-bit DAC intended, particularly, for application in high-speed and high-resolution ADCs, such as Σ Δ ADCs, and comprising a number of DAC cells, apart from the number of DAC cells applied in the multi-bit DAC for conversion, an additional DAC cell is provided, which can be interchanged with each of the other DAC cells in order to switch each DAC cell successively from the multi-bit DAC into a calibration circuit to calibrate said DAC cell without interrupting the conversion. The calibration circuit includes means for measuring errors in the DAC cell under calibration and means for correcting said DAC cell.
摘要翻译：在用于校准多位DAC的方法中，特别是用于在高速和高分辨率ADC（例如Sigma Delta ADC）中应用并且包括多个DAC单元的方法，除了在用于转换的多位DAC，提供了另外的DAC单元，其可以与每个其它DAC单元互换，以便将每个DAC单元从多位DAC连续切换到校准电路，以校准所述DAC单元而不中断转换。校准电路包括用于测量校准期间DAC单元中的误差的装置以及用于校正所述DAC单元的装置。

14. 发明申请

US20070176666A1 Level translator for adapting a signal to a voltage level 审中-公开
标题翻译：电平转换器，用于将信号调整到电压电平
公开(公告)号：US20070176666A1
公开(公告)日：2007-08-02
申请号：US11341383
申请日：2006-01-30
申请人： Erol Arslan , Ovidiu Bajdechi
发明人： Erol Arslan , Ovidiu Bajdechi
IPC分类号： H03L5/00
CPC分类号： H03K3/012 , H03K3/35613
摘要： A level translator for translating a digital signal from a first voltage level to another voltage level having a higher voltage assigned to the high state of the signal comprises a latch and a pair of N-MOS transistors being coupled to the latch. This design is improved in that the N-MOS transistors are native thick oxide N-MOS transistors, each having a thin oxide layer N-MOS transistor coupled to native thick oxide transistors for reducing leakage current and improving speed in the transient state.
摘要翻译：用于将数字信号从第一电压电平转换为具有分配给信号的高状态的较高电压的另一电压电平的电平转换器包括锁存器和耦合到锁存器的一对N-MOS晶体管。改进了这种设计，因为N-MOS晶体管是天然厚氧化物N-MOS晶体管，每个都具有耦合到天然厚氧化物晶体管的薄氧化层N-MOS晶体管，用于减少漏电流并改善瞬态状态下的速度。

15. 发明申请

US20070035423A1 Method for calibrating a multi-bit digital-to-analog converter, multi-bit digital-to-analog converter in with this method is applied and converter provided with such a multi-bit digital-to-analog converter 有权
标题翻译：采用这种方法校准多位数模转换器的多位数模转换器的方法被应用，并且转换器提供了这样的多位数模转换器
公开(公告)号：US20070035423A1
公开(公告)日：2007-02-15
申请号：US10571949
申请日：2004-09-13
申请人： Lucien Breems , Ovidiu Bajdechi
发明人： Lucien Breems , Ovidiu Bajdechi
IPC分类号： H03M1/10
CPC分类号： H03M1/1004
摘要： In a method for calibrating a multi-bit DAC intended, particularly, for application in high-speed and high-resolution ADCs, such as Σ Δ ADCs, and comprising a number of DAC cells, apart from the number of DAC cells applied in the multi-bit DAC for conversion, an additional DAC cell is provided, which can be interchanged with each of the other DAC cells in order to switch each DAC cell successively from the multi-bit DAC into a calibration circuit to calibrate said DAC cell without interrupting the conversion. The calibration circuit includes means for measuring errors in the DAC cell under calibration and means for correcting said DAC cell.
摘要翻译：在用于校准多位DAC的方法中，特别是用于在高速和高分辨率ADC（例如Sigma Delta ADC）中应用并且包括多个DAC单元的方法，除了在用于转换的多位DAC，提供了另外的DAC单元，其可以与每个其它DAC单元互换，以便将每个DAC单元从多位DAC连续切换到校准电路，以校准所述DAC单元而不中断转换。校准电路包括用于测量校准期间DAC单元中的误差的装置以及用于校正所述DAC单元的装置。

16. 发明申请

US20130076549A1 GATE LEAKAGE COMPENSATION IN A CURRENT MIRROR 有权
标题翻译：门电流泄漏补偿
公开(公告)号：US20130076549A1
公开(公告)日：2013-03-28
申请号：US13246319
申请日：2011-09-27
申请人： Ovidiu Bajdechi , Tom W. Kwan
发明人： Ovidiu Bajdechi , Tom W. Kwan
IPC分类号： H03M1/66 , G05F1/10
CPC分类号： G05F3/08 , G05F3/267 , H03M1/0607 , H03M1/66
摘要： A method and apparatus is disclosed to compensate for gate leakage currents of thin oxide devices that have very thin oxide layers in a current mirror of a digital-to-analog converter (DAC). The DAC converts a digital input signal from a digital representation in a digital signaling domain to an analog representation in an analog signaling domain to provide an analog output signal. The DAC uses one or more transistors to convert the digital input signal from the digital representation to the analog representation. These transistors are typically implemented using thin oxide devices that have very thin oxide layers and corresponding gate leakage currents that are associated with these very thin oxide layers. The current-steering DAC provides these gate leakage currents independent of its corresponding reference source without any substantial affect upon its full scale output.
摘要翻译：公开了一种用于补偿在数模转换器（DAC）的电流镜中具有非常薄的氧化物层的薄氧化物器件的栅极泄漏电流的方法和装置。 DAC将数字输入信号从数字信号域中的数字表示转换为模拟信号域中的模拟表示，以提供模拟输出信号。 DAC使用一个或多个晶体管将数字输入信号从数字表示转换为模拟表示。这些晶体管通常使用具有与这些非常薄的氧化物层相关联的非常薄的氧化物层和相应的栅极泄漏电流的薄氧化物器件来实现。电流导向DAC提供独立于其相应参考源的这些栅极泄漏电流，而对其满量程输出没有任何实质影响。

17. 发明申请

US20070273444A1 Techniques for enabling a 10BT active output impedance line driver using a low power supply 有权
标题翻译：使用低功率电源实现10BT有源输出阻抗线路驱动器的技术
公开(公告)号：US20070273444A1
公开(公告)日：2007-11-29
申请号：US11798294
申请日：2007-05-11
申请人： Ovidiu Bajdechi , Christopher M. Ward
发明人： Ovidiu Bajdechi , Christopher M. Ward
IPC分类号： H03F3/45
CPC分类号： H03F3/45475 , H03F3/45183 , H03F3/4521 , H03F3/45659 , H03F2200/513 , H03F2203/45066 , H03F2203/45116 , H03F2203/45138 , H03F2203/45236 , H03F2203/45522 , H03F2203/45526
摘要： A line driver for generating 10 BT signals is disclosed. Digital symbols to be transmitted via a 10 BT Ethernet line are converted by a digital-to-analog converter into a corresponding analog voltage signal, which is fed into an active output impedance line driver. The digital-to-analog converter also receives a reference voltage reflecting variations of the supply voltage and adjusts its output signal accordingly to provide a deliberately variable analog voltage signal to the line driver.
摘要翻译：公开了一种用于产生10个BT信号的线路驱动器。要通过10 BT以太网线传输的数字符号由数模转换器转换成相应的模拟电压信号，该信号被馈送到有源输出阻抗线路驱动器。数模转换器还接收反映电源电压变化的参考电压，并相应地调整其输出信号，以向线路驱动器提供故意可变的模拟电压信号。

18. 发明申请

US20070273442A1 High-efficiency class-AB amplifier 有权
标题翻译：高效率AB类放大器
公开(公告)号：US20070273442A1
公开(公告)日：2007-11-29
申请号：US11798293
申请日：2007-05-11
申请人： Ovidiu Bajdechi , Christopher M. Ward , Klaas Bult
发明人： Ovidiu Bajdechi , Christopher M. Ward , Klaas Bult
IPC分类号： H03F3/45
CPC分类号： H03F3/3028 , H03F1/0261 , H03F3/45192 , H03F3/45219 , H03F2203/30033 , H03F2203/30084 , H03F2203/30117 , H03F2203/45244 , H03F2203/45302 , H03F2203/45641 , H03F2203/45732
摘要： A high efficiency class-AB amplifier is disclosed. The amplifier comprises a first input stage and a second input stage, both coupled to a class-AB biasing mesh and an output stage, wherein the outputs of the first and second input stages are directly coupled to the output transistors in the output stage. In one embodiment, a first gate of the first input stage and of the second input stage are coupled together to receive the same input and a second gate of the first input stage and of the second input stage are coupled together to receive the same input. In another embodiment, the first input stage and second input stage may further comprise cascode transistors for coupling the two input stages to the class-AB biasing mesh. In yet another embodiment, a 3V supply is used and 1V transistors are used to improve gain and 3V transistors are used to protect the 1V transistors.
摘要翻译：公开了一种高效率AB类放大器。放大器包括耦合到AB类偏置网格和输出级的第一输入级和第二输入级，其中第一和第二输入级的输出直接耦合到输出级中的输出晶体管。在一个实施例中，第一输入级和第二输入级的第一栅极耦合在一起以接收相同的输入，并且第一输入级和第二输入级的第二栅极耦合在一起以接收相同的输入。在另一个实施例中，第一输入级和第二输入级还可以包括用于将两个输入级耦合到AB类偏置网的共源共栅晶体管。在另一个实施例中，使用3V电源，并且使用1V晶体管来改善增益，并且使用3V晶体管来保护1V晶体管。

19. 发明申请

US20070176664A1 Programmable gain attenuator for track and hold amplifiers 有权
标题翻译：用于跟踪和保持放大器的可编程增益衰减器
公开(公告)号：US20070176664A1
公开(公告)日：2007-08-02
申请号：US11341384
申请日：2006-01-30
申请人： Ovidiu Bajdechi , Franciscus van der Goes
发明人： Ovidiu Bajdechi , Franciscus van der Goes
IPC分类号： H03L5/00
CPC分类号： H03F3/45475 , H03F1/34 , H03F2203/45528 , H03F2203/45534 , H03G1/0088 , H03G3/001
摘要： A programmable gain attenuator (PGA) in particular to be used in a track-and-hold circuit is disclosed. The PGA is located in the feedback path around an operational amplifier. One tap switch is used to connect one PGA section to the output of the operational amplifier. The PGA section is capable of producing a multiplicity of different gain settings by using a multiplicity of secondary resistive devices in a voltage divider, wherein the resistive devices each can be independently coupled to a reference voltage.
摘要翻译：公开了一种特别用于跟踪和保持电路中的可编程增益衰减器（PGA）。 PGA位于运算放大器周围的反馈路径中。一个分接开关用于将一个PGA部分连接到运算放大器的输出。 PGA部分能够通过在分压器中使用多个次级电阻器件来产生多种不同的增益设置，其中每个电阻器件可以独立地耦合到参考电压。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式