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11. 发明申请

US20070103192A1 Bit stream compatible FPGA to MPGA design conversions 有权
标题翻译：位流兼容FPGA到MPGA设计转换
公开(公告)号：US20070103192A1
公开(公告)日：2007-05-10
申请号：US11645313
申请日：2006-12-26
申请人： Raminda Madurawe
发明人： Raminda Madurawe
IPC分类号： H03K19/177
CPC分类号： G06F17/5054 , G06F17/5045 , G06F17/5077 , G06F2217/06 , G11C16/0433 , G11C17/16 , H01L27/1052 , H03K19/17796
摘要： A method of converting designs from a field programmable gate array (FPGA) to a mask programmable gate array (MPGA), comprising: an FPGA comprising a programmable logic block array, and a plurality of programmable interconnect wires, and a bit-stream of memory data to program the FPGA; and an MPGA comprising identical layouts of the programmable logic block array and the plurality of programmable interconnect wires, wherein the bit-stream data is converted to a custom metal pattern to mask program the MPGA.
摘要翻译：一种将设计从现场可编程门阵列（FPGA）转换为掩模可编程门阵列（MPGA）的方法，包括：包括可编程逻辑块阵列和多个可编程互连线以及存储器的比特流的FPGA 数据编程FPGA; 以及MPGA，其包括可编程逻辑块阵列和多个可编程互连线的相同布局，其中将比特流数据转换为定制金属图案以掩盖MPGA的编程。

12. 发明申请

US20060150137A1 Three dimensional integrated circuits 有权
公开(公告)号：US20060150137A1
公开(公告)日：2006-07-06
申请号：US11363304
申请日：2006-02-27
申请人： Raminda Madurawe
发明人： Raminda Madurawe
IPC分类号： G06F17/50
CPC分类号： H03K19/17724 , H01L21/8221 , H01L27/0688 , H03K19/1735 , H03K19/177 , H03K19/17736 , H03K19/17748 , H03K19/17796
摘要： A three-dimensional semiconductor device, comprising: a circuit block located in a first module layer; and a configuration circuit to control the circuit block further comprising a configurable element in a second module layer positioned above the first module layer.

13. 发明申请

US20050121789A1 Programmable structured arrays 有权
标题翻译：可编程结构化阵列
公开(公告)号：US20050121789A1
公开(公告)日：2005-06-09
申请号：US10727170
申请日：2003-12-04
申请人： Raminda Madurawe
发明人： Raminda Madurawe
IPC分类号： H01L23/48 , H01L27/02 , H01L27/105 , H01L27/108 , H01L27/11 , H01L27/118
CPC分类号： H03K19/1735 , H01L23/5252 , H01L27/0207 , H01L27/0688 , H01L27/105 , H01L27/10897 , H01L27/11 , H01L27/1116 , H01L27/11803 , H01L27/11898 , H01L27/1203 , H01L2924/0002 , H03K19/1733 , H03K19/17728 , H03K19/1776 , H01L2924/00
摘要： A programmable wire structure for an integrated circuit, comprising: a programmable switch coupling two nodes, said switch having a first state that connects said two nodes, and said switch having a second state that disconnects said two nodes; and a configuration circuit coupled to said programmable switch, said circuit comprising a means to program said switch between said first and second state; and a first metal layer fabricated above a silicon substrate layer, said switch and said configuration circuit fabricated substantially above said first metal layer. A semiconductor device for integrated circuits with two selectable manufacturing configurations, comprising: a first module layer having an array of structured cells, said module layer having at least one layer of metal; and a second module layer formed substantially above said first module layer comprising two selectable configurations, wherein: in a first selectable configuration a programmable interconnect structure is formed to connect said structured cells, and in a second selectable configuration a customized interconnect structure is formed to connect said structured cells.
摘要翻译：一种用于集成电路的可编程线结构，包括：耦合两个节点的可编程开关，所述开关具有连接所述两个节点的第一状态，并且所述开关具有断开所述两个节点的第二状态; 以及耦合到所述可编程开关的配置电路，所述电路包括在所述第一和第二状态之间对所述开关进行编程的装置; 以及在硅衬底层之上制造的第一金属层，所述开关和所述配置电路基本上在所述第一金属层的上方制成。一种用于具有两个可选制造配置的集成电路的半导体器件，包括：具有结构化单元阵列的第一模块层，所述模块层具有至少一层金属; 以及基本上在所述第一模块层上形成的包括两个可选配置的第二模块层，其中：在第一可选配置中，形成可编程互连结构以连接所述结构化单元，并且在第二可选配置中，形成定制互连结构以连接所述结构化细胞。

14. 发明授权

US5914509A Two-terminal electrically-reprogrammable programmable logic element 失效
标题翻译：两端电可重新编程的可编程逻辑元件
公开(公告)号：US5914509A
公开(公告)日：1999-06-22
申请号：US103969
申请日：1998-06-24
申请人： Dominik Schmidt , Raminda Madurawe
发明人： Dominik Schmidt , Raminda Madurawe
IPC分类号： G11C16/04 , G11C16/10 , G11C16/14 , H01L29/423 , H01L29/788 , H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L29/7883 , G11C16/0416 , G11C16/10 , G11C16/14 , H01L29/42324
摘要： A non-volatile two terminal programmable logic element and associated methods for charging and discharging are disclosed. The logic element includes one input and one output terminal, a first capacitor region, a second capacitor region, and a floating gate (transistor-type) structure. The first capacitor region does not permit tunneling. The second capacitor region permits tunneling between its respective electrodes when a predetermined voltage, substantially higher than the normal operating voltage is applied. The source is connected to the input terminal and one electrode of the first capacitor region. The drain is connected to the output terminal and one electrode of the second capacitor region. The floating gate is connected to the other electrodes of the first and second capacitor regions. A programmable logic device constructed from these elements and associated methods of programming and erasing such a device are also shown.
摘要翻译：公开了一种用于充电和放电的非易失性双端可编程逻辑元件和相关方法。逻辑元件包括一个输入端和一个输出端，第一电容区，第二电容区和浮栅（晶体管型）结构。第一电容器区域不允许隧穿。当施加明显高于正常工作电压的预定电压时，第二电容器区域允许其各自电极之间的隧穿。源极连接到第一电容器区域的输入端子和一个电极。漏极连接到第二电容器区域的输出端子和一个电极。浮置栅极连接到第一和第二电容器区域的其他电极。还示出了由这些元件构成的可编程逻辑器件和编程和擦除这种器件的相关方法。

15. 发明授权

US5548552A Reconfigurable programmable logic device 失效
标题翻译：可重构可编程逻辑器件
公开(公告)号：US5548552A
公开(公告)日：1996-08-20
申请号：US457884
申请日：1995-05-31
申请人： Raminda Madurawe
发明人： Raminda Madurawe
IPC分类号： H03K19/177 , G11C11/34
CPC分类号： H03K19/17756 , H03K19/17704
摘要： The present invention provides a reconfigurable programmable logic device (PLD) that saves its own programmed state without the use of an external memory device or without additional control logic on the PLD. A non-volatile memory cell is incorporated with each SRAM cell in the PLD to form a configuration memory cell. The non-volatile memory cells store the programmed states of the associated SRAM cells even after termination of power to the system. Each non-volatile memory cell then restores the configured state of its associated SRAM cell upon system power-up by "mapping" its contents to the SRAM cell. The non-volatile memory cell may be implemented either by an Erasable Programmable Read Only Memory cell ("EPROM") or an Electrically Erasable Programmable Read Only Memory cell ("EEPROM").
摘要翻译：本发明提供了可重新配置的可编程逻辑器件（PLD），其在不使用外部存储器件的情况下保存其自己的编程状态，或者在PLD上没有附加的控制逻辑。非易失性存储单元与PLD中的每个SRAM单元并入，以形成配置存储单元。非易失性存储器单元即使在终止电力系统之后也存储相关SRAM单元的编程状态。然后，通过将其内容“映射”到SRAM单元，系统上电时，每个非易失性存储单元恢复其关联的SRAM单元的配置状态。非易失性存储单元可以由可擦除可编程只读存储单元（“EPROM”）或电可擦除可编程只读存储单元（“EEPROM”）来实现。

16. 发明申请

US20090167350A1 PROGRAMMABLE LOGIC BASED LATCHES AND SHIFT REGISTERS 有权
标题翻译：可编程逻辑的锁存器和移位寄存器
公开(公告)号：US20090167350A1
公开(公告)日：2009-07-02
申请号：US12119492
申请日：2008-05-12
申请人： Raminda Madurawe , Nij Dorairaj
发明人： Raminda Madurawe , Nij Dorairaj
IPC分类号： H03K19/173
CPC分类号： H03K19/17736 , H03K19/17728
摘要： Disclosed is a programmable logic device adapted to implement a shift register, the device comprising: a logic block comprised of: a latch having an input; and a logic element having an output capable of coupling to an adjacent logic block and the latch input, wherein the output is coupled to the adjacent logic block and decoupled from the latch input; and an interconnect coupled to the latch and adapted to transmit the latch output to an input of the logic element. In the device, the logic element is configured as a route through for the latch output to couple to the adjacent logic block.
摘要翻译：公开了一种适于实现移位寄存器的可编程逻辑器件，该器件包括：逻辑块，包括：具有输入的锁存器; 以及具有能够耦合到相邻逻辑块和所述锁存器输入的输出的逻辑元件，其中所述输出耦合到所述相邻逻辑块并且从所述锁存器输入解耦; 以及耦合到所述锁存器并且适于将所述锁存器输出发送到所述逻辑元件的输入的互连。在器件中，逻辑元件被配置为通过锁存器输出耦合到相邻逻辑块的路由。

17. 发明申请

US20070152708A1 MPGA products based on a prototype FPGA 有权
标题翻译： MPGA产品基于原型FPGA
公开(公告)号：US20070152708A1
公开(公告)日：2007-07-05
申请号：US11712380
申请日：2007-03-01
申请人： Raminda Madurawe , Peter Suaris , Thomas White
发明人： Raminda Madurawe , Peter Suaris , Thomas White
IPC分类号： H03K19/177
CPC分类号： H03K19/17796
摘要： A smaller mask programmable gate array (MPGA) device derived from a larger field programmable gate array (FPGA), comprising: a layout of transistors and a plurality of interconnect layers substantially identical to a smaller region of the FPGA; and input/output pads matching a subset of the input/output pads of the FPGA; wherein, a design that is mapped to said smaller region of the FPGA device using said subset of input/output pads by a user programmable means can be identically mapped to the MPGA by a hard-wire circuit. Such a gate array further comprises a mask programmable metal-circuit in lieu of a user programmable configuration circuit of the FPGA; and a logic block to input/output pad connection in lieu of a logic block to a register at the boundary of said smaller region to an input/output pad connection of the FPGA.
摘要翻译：从较大的现场可编程门阵列（FPGA）导出的较小的掩模可编程门阵列（MPGA）器件，包括：晶体管的布局和与FPGA的较小区域基本相同的多个互连层; 以及与FPGA的输入/输出焊盘的子集匹配的输入/输出焊盘; 其中，使用用户可编程装置的所述输入/输出焊盘子集映射到所述FPGA器件的所述较小区域的设计可以通过硬线电路被相同地映射到MPGA。这种门阵列还包括代替FPGA的用户可编程配置电路的掩模可编程金属电路; 以及逻辑块，以将代替逻辑块的输入/输出焊盘连接输入到所述较小区域的边界处的寄存器到FPGA的输入/输出焊盘连接。

18. 发明申请

US20070152707A1 Integrated circuits with RAM and ROM fabrication options 有权
公开(公告)号：US20070152707A1
公开(公告)日：2007-07-05
申请号：US11707231
申请日：2007-02-16
申请人： Raminda Madurawe
发明人： Raminda Madurawe
IPC分类号： H03K19/173
CPC分类号： H03K19/177 , G11C16/0408
摘要： The present invention relates to electronic integrated circuits (ICs) that retain identical functionality with better performance or lower power dissipation under RAM and hard-wire ROM fabrication options, without the need to alter transistor layout within the IC. An integrated circuit (IC) comprising: a plurality of transistors; and a first selectable fabrication option comprised of a user configurable memory circuit; and a second selectable fabrication option comprised of a hard-wired circuit in lieu of said user configurable memory circuit; wherein, the IC functionality and performance is determined by the configuration memory data in the first fabrication option, and wherein the identical configuration is hard-wired in the second fabrication option without altering the location of transistors within the IC. Such a programmable to hard-wire conversion provides a significant IC cost reduction, performance improvement and power dissipation reduction at minimal NRE cost and improved reliability.

19. 发明申请

US20070035329A1 Look-up table based logic macro-cells 失效
公开(公告)号：US20070035329A1
公开(公告)日：2007-02-15
申请号：US11546681
申请日：2006-10-13
申请人： Raminda Madurawe
发明人： Raminda Madurawe
IPC分类号： H03K19/177
CPC分类号： H03K19/1778 , H03K19/1737 , H03K19/17728 , H03K19/17732
摘要： A programmable look up table (LUT) structure of an integrated circuit, comprising: two or more LUT circuits, each said LUT circuit comprising: one or more inputs; and a plurality of LUT values; and at least one output; and a configurable multiplexer (MUX) circuit comprising: a plurality of inputs; and one or more select signals; and one or more outputs; wherein, the output of each said LUT circuit is directly coupled to a said input of the MUX circuit. Said structure further comprising one or more data storage units, each said data storage units comprising a digital output, wherein one or more of: a said MUX circuit input is directly coupled to a said data storage unit digital output.

20. 发明申请

US20070030027A1 Programmable interconnect structures 失效
公开(公告)号：US20070030027A1
公开(公告)日：2007-02-08
申请号：US11545044
申请日：2006-10-10
申请人： Raminda Madurawe
发明人： Raminda Madurawe
IPC分类号： H03K19/173
CPC分类号： H03K19/1776 , H03K19/17704 , H03K19/17736 , H03K19/1778 , H03K19/17796
摘要： A layout of a programmable interconnect structure, comprising: an active region; and an even plurality of gate regions dividing the active region into a plurality of active stripes, said active stripes arranged into disjoint first, second and third sets; and a plurality of interconnect wires, each interconnect wire coupled to a contact in an active stripe of the first set; and an input wire coupled to a contact in each of the active stripes of said second set; and an output wire coupled to a contact in each of the active stripes of said third set; and a buffer layout comprising one or more buffer gate regions and one or more buffer active regions, wherein the input wire is further coupled to a buffer gate region and the output wire is further coupled to a buffer active region.

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