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11. 发明申请

US20070273433A1 FLOATING VOLTAGE SOURCE 审中-公开
标题翻译：浮动电源
公开(公告)号：US20070273433A1
公开(公告)日：2007-11-29
申请号：US11420050
申请日：2006-05-24
申请人： Jon S. Choy
发明人： Jon S. Choy
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： G05F3/24 , H02M3/07 , H02M2003/071
摘要： A floating voltage source circuit that provides a floating voltage. The floating voltage source circuit includes a feedback current path and a floating voltage current path, where the floating voltage provided by the floating voltage current path is dependent upon a current of the feedback current path. The current through the feedback current path is controlled by the reference voltage.
摘要翻译：提供浮置电压的浮动电压源电路。浮动电压源电路包括反馈电流路径和浮动电压电流路径，其中由浮动电压电流路径提供的浮置电压取决于反馈电流路径的电流。通过反馈电流路径的电流由参考电压控制。

12. 发明申请

US20150371711A1 CONTROL GATE DRIVER FOR USE WITH SPLIT GATE MEMORY CELLS 有权
标题翻译：控制门驱动器用于分离栅格存储器单元
公开(公告)号：US20150371711A1
公开(公告)日：2015-12-24
申请号：US14310585
申请日：2014-06-20
申请人： Jon S. Choy , Anirban Roy
发明人： Jon S. Choy , Anirban Roy
IPC分类号： G11C16/24 , G11C16/34 , G11C16/12 , G11C16/26 , G11C16/22
CPC分类号： G11C16/24 , G11C16/12 , G11C16/225 , G11C16/26 , G11C16/3445 , G11C16/3459
摘要： A circuit for driving a control gate of a split-gate nonvolatile memory cell may include a switched current source; a first transistor having a current electrode coupled to the switched current source and a control electrode coupled to a voltage source; a second transistor having a current electrode coupled to a second node of the switched current source, and a control electrode coupled to a third voltage source; a third transistor having a control electrode coupled to the second transistor, a current electrode coupled to the first transistor and a fourth switched voltage source; and a fourth transistor having a current electrode coupled to the first switched voltage source, a control electrode coupled to the switched current source, and a second current electrode coupled to the second transistor at a driver voltage node, wherein a voltage level at the driver voltage node is operable to drive the control gate.
摘要翻译：用于驱动分闸器非易失性存储单元的控制栅极的电路可以包括开关电流源; 第一晶体管，其具有耦合到所述开关电流源的电流电极和耦合到电压源的控制电极; 第二晶体管，其具有耦合到所述开关电流源的第二节点的电流电极，以及耦合到第三电压源的控制电极; 第三晶体管，其具有耦合到所述第二晶体管的控制电极，耦合到所述第一晶体管的电流电极和第四开关电压源; 以及第四晶体管，其具有耦合到所述第一开关电压源的电流电极，耦合到所述开关电流源的控制电极和在驱动器电压节点处耦合到所述第二晶体管的第二电流电极，其中所述驱动器电压节点可操作以驱动控制门。

13. 发明授权

US09191007B1 Latching level shifter and method of operation 有权
标题翻译：锁定电平转换器及操作方法
公开(公告)号：US09191007B1
公开(公告)日：2015-11-17
申请号：US14310579
申请日：2014-06-20
申请人： Jon S. Choy , David W. Chrudimsky
发明人： Jon S. Choy , David W. Chrudimsky
IPC分类号： H03K19/0175 , H03K19/0185 , H03K3/356
CPC分类号： H03K3/356113 , H03K3/35613 , H03K19/018507 , H03K19/018521 , H03K19/018528
摘要： A latching level shifter coupled to a first power supply voltage is driven by a logic circuit coupled to a second power supply voltage. The latching level shifter is driven in a first mode to store a state based on an input signal received by the logic circuit, the first and second power supply voltages are set at first and second initial voltage levels. The latching level shifter is driven in a second mode subsequent to the first mode, the first power supply voltage is set to an intermediate voltage level. The latching level shifter is driven in a high voltage protection mode to produce an output voltage based on the state, the first power supply voltage is set to a final voltage level that is greater than a final voltage level of the second power supply voltage. The high voltage protection mode is subsequent to the second mode.
摘要翻译：耦合到第一电源电压的锁存电平移位器由耦合到第二电源电压的逻辑电路驱动。闩锁电平移位器在第一模式下被驱动以存储基于由逻辑电路接收的输入信号的状态，第一和第二电源电压被设置在第一和第二初始电压电平。锁存电平移位器在第一模式之后以第二模式被驱动，第一电源电压被设置为中间电压电平。锁存电平移位器在高电压保护模式下被驱动以产生基于状态的输出电压，第一电源电压被设置为大于第二电源电压的最终电压电平的最终电压电平。高电压保护模式在第二模式之后。

14. 发明申请

US20140140161A1 NON-VOLATILE MEMORY ROBUST START-UP USING ANALOG-TO-DIGITAL CONVERTER 有权
标题翻译：非易失性存储器使用模拟数字转换器进行稳定启动
公开(公告)号：US20140140161A1
公开(公告)日：2014-05-22
申请号：US13679515
申请日：2012-11-16
申请人： Richard K. Eguchi , Jon S. Choy
发明人： Richard K. Eguchi , Jon S. Choy
IPC分类号： G11C5/14
CPC分类号： G11C5/145 , G11C5/14 , G11C16/30 , G11C29/021 , G11C29/028 , G11C2029/0409
摘要： In accordance with at least one embodiment, an onboard analog-to-digital converter (ADC) on a system-on-a-chip (SOC) is utilized to determine whether a charge pump output for a non-volatile memory (NVM) is correct or not. The SOC is directed to wait until the output is within an expected range before moving to the next step in a start-up procedure. If the maximum allowed start-up time is exceeded, an error signal is sent to the SOC such that the application can react to it.
摘要翻译：根据至少一个实施例，利用片上系统（SOC）上的车载模拟 - 数字转换器（ADC）来确定非易失性存储器（NVM）的电荷泵输出是否为正确与否在开始启动过程中移动到下一步之前，SOC被指示等待直到输出在预期范围内。如果超过允许的最大启动时间，则向SOC发送错误信号，以使应用程序能够对其做出反应。

15. 发明授权

US07602168B2 Voltage regulator for integrated circuits 有权
标题翻译：用于集成电路的稳压器
公开(公告)号：US07602168B2
公开(公告)日：2009-10-13
申请号：US11849155
申请日：2007-08-31
申请人： Yanzhuo Wang , Jon S. Choy
发明人： Yanzhuo Wang , Jon S. Choy
IPC分类号： G05F1/40 , G05F1/56
CPC分类号： H02M3/07
摘要： A voltage regulator for a charge pump includes a capacitor divider and a reset circuit. The capacitor divider produces, based on an input voltage (VPP), a sample voltage at a sampling node. The sampling node and a reference voltage VREF are connected to respective inputs of a comparator that generates an enable signal for the charge pump. The reset circuit connects to the divider and includes a first transistor connected between the sampling node and a biasing node. During a sampling mode, the reset circuit biases VDS of the first transistor to approximately zero at the regulation point to minimize sub-threshold IDS. During reset intervals, the reset circuit applies VREF to the biasing node. The reset circuit may include a second transistor connected between the biasing node and a known level (e.g., ground) and a biasing transistor connected between the biasing node and VREF.
摘要翻译：用于电荷泵的电压调节器包括电容分压器和复位电路。电容分压器基于输入电压（VPP）产生采样节点处的采样电压。采样节点和参考电压VREF连接到产生用于电荷泵的使能信号的比较器的相应输入端。复位电路连接到分压器并且包括连接在采样节点和偏置节点之间的第一晶体管。在采样模式期间，复位电路在调节点将第一晶体管的VDS偏置为大约零，以使子阈值IDS最小化。在复位间隔期间，复位电路将VREF施加到偏置节点。复位电路可以包括连接在偏置节点和已知电平（例如接地）之间的第二晶体管以及连接在偏置节点和VREF之间的偏置晶体管。

16. 发明申请

US20090059629A1 VOLTAGE REGULATOR FOR INTEGRATED CIRCUITS 有权
标题翻译：用于集成电路的电压调节器
公开(公告)号：US20090059629A1
公开(公告)日：2009-03-05
申请号：US11849155
申请日：2007-08-31
申请人： Yanzhuo Wang , Jon S. Choy
发明人： Yanzhuo Wang , Jon S. Choy
IPC分类号： H02M3/18
CPC分类号： H02M3/07
摘要： A voltage regulator for a charge pump includes a capacitor divider and a reset circuit. The capacitor divider produces, based on an input voltage (VPP), a sample voltage at a sampling node. The sampling node and a reference voltage VREF are connected to respective inputs of a comparator that generates an enable signal for the charge pump. The reset circuit connects to the divider and includes a first transistor connected between the sampling node and a biasing node. During a sampling mode, the reset circuit biases VDS of the first transistor to approximately zero at the regulation point to minimize subthreshold IDS. During reset intervals, the reset circuit applies VREF to the biasing node. The reset circuit may include a second transistor connected between the biasing node and a known level (e.g., ground) and a biasing transistor connected between the biasing node and VREF.
摘要翻译：用于电荷泵的电压调节器包括电容分压器和复位电路。电容分压器基于输入电压（VPP）产生采样节点处的采样电压。采样节点和参考电压VREF连接到产生用于电荷泵的使能信号的比较器的相应输入端。复位电路连接到分压器并且包括连接在采样节点和偏置节点之间的第一晶体管。在采样模式期间，复位电路在调节点将第一晶体管的VDS偏压到零，以使亚阈值IDS最小化。在复位间隔期间，复位电路将VREF施加到偏置节点。复位电路可以包括连接在偏置节点和已知电平（例如接地）之间的第二晶体管以及连接在偏置节点和VREF之间的偏置晶体管。

17. 发明授权

US07471582B2 Memory circuit using a reference for sensing 有权
标题翻译：记忆电路使用参考进行感测
公开(公告)号：US07471582B2
公开(公告)日：2008-12-30
申请号：US11460745
申请日：2006-07-28
申请人： Jon S. Choy , Tahmina Akhter
发明人： Jon S. Choy , Tahmina Akhter
IPC分类号： G11C7/04
CPC分类号： G11C29/02 , G11C7/04 , G11C7/062 , G11C7/14 , G11C16/28 , G11C29/021 , G11C29/026 , G11C29/028 , G11C2207/063
摘要： A memory includes a plurality of memory cells, a sense amplifier coupled to at least one of the plurality of memory cells, a temperature dependent current generator comprising a plurality of selectable temperature dependent current sources for generating a temperature dependent current, a temperature independent current generator comprising a plurality of selectable temperature independent current sources for generating a temperature independent current, and a summer coupled to the temperature dependent current generator and the temperature independent current generator for combining the temperature dependent current and the temperature independent current to generate a reference current for use by the sense amplifier. A temperature coefficient of the reference current is approximately a same as a temperature coefficient of a memory cell current of at least one of the plurality of memory cells.
摘要翻译：存储器包括多个存储器单元，耦合到所述多个存储器单元中的至少一个存储器单元的读出放大器，包括多个可选择的温度相关电流源的温度依赖性电流发生器，用于产生与温度相关的电流，温度无关电流发生器包括用于产生不依赖于温度的电流的多个可选择的温度独立电流源，以及耦合到温度依赖性电流发生器和独立于温度的电流发生器的加法器，用于组合温度依赖电流和与温度无关的电流以产生用于使用的参考电流由感应放大器。基准电流的温度系数与多个存储单元中的至少一个的存储单元电流的温度系数大致相同。

18. 发明授权

US07348829B2 Slew rate control of a charge pump 有权
标题翻译：电荷泵的压摆率控制
公开(公告)号：US07348829B2
公开(公告)日：2008-03-25
申请号：US11388396
申请日：2006-03-24
申请人： Jon S. Choy , Tahmina Akhter
发明人： Jon S. Choy , Tahmina Akhter
IPC分类号： G05F1/10
CPC分类号： H02M3/07
摘要： A charge pump system including a clock circuit and a charge pump circuit is provided. The clock circuit provides a first clock with a frequency based on a memory block select signal indicative of load capacitance of a charge node. The charge pump circuit receives the first clock and charges the charge node at a rate based on the frequency of the first clock and the load capacitance of the charge node. The memory block select signal indicates which of the memory blocks are coupled to the charge node and thus indicates the load capacitance of the charge node. The frequency of the first clock is adjusted based on the load capacitance of the selected block so that the slew rate of the charge node is about the same. Thus, the slew rate of the voltage ramp on the charge node is about the same regardless of the load capacitance.
摘要翻译：提供了包括时钟电路和电荷泵电路的电荷泵系统。时钟电路提供基于表示充电节点的负载电容的存储块选择信号的频率的第一时钟。电荷泵电路接收第一时钟并以基于第一时钟的频率和充电节点的负载电容的速率对充电节点充电。存储器块选择信号指示哪个存储器块耦合到充电节点，并且因此指示充电节点的负载电容。基于所选块的负载电容来调整第一时钟的频率，使得充电节点的转换速率大致相同。因此，无论负载电容如何，充电节点上的电压斜坡的转换速率大致相同。

19. 发明授权

US07272053B2 Integrated circuit having a non-volatile memory with discharge rate control and method therefor 有权
标题翻译：具有放电速率控制的非易失性存储器的集成电路及其方法
公开(公告)号：US07272053B2
公开(公告)日：2007-09-18
申请号：US11120270
申请日：2005-05-02
申请人： Jon S. Choy
发明人： Jon S. Choy
IPC分类号： G11C11/34
CPC分类号： G11C16/0416 , G11C16/14
摘要： An integrated circuit includes a memory (10). The memory (10) includes an array (12) of non-volatile memory cells. Each memory cell (14) of the array (12) includes a plurality of terminals comprising: a control gate, a charge storage region, a source, a drain, a well terminal, and a deep well terminal. Following an erase operation of the array (12), the erase voltages are discharged from each of the memory cells. A discharge rate control circuit (11) controls the discharging of terminals of the memory cell. The discharge rate control circuit (11) includes, for example, a plurality of parallel-connected transistors (112) coupled between the array (12) of non-volatile memory cells and a power supply terminal.
摘要翻译：集成电路包括存储器（10）。存储器（10）包括非易失性存储器单元的阵列（12）。阵列（12）的每个存储单元（14）包括多个端子，包括：控制栅极，电荷存储区域，源极，漏极，阱端子和深阱端子。在阵列（12）的擦除操作之后，擦除电压从每个存储单元放电。放电速率控制电路（11）控制存储单元的端子的放电。放电率控制电路（11）例如包括耦合在非易失性存储单元的阵列（12）和电源端子之间的多个并联的晶体管（112）。

20. 发明授权

US09129700B2 Systems and methods for adaptive soft programming for non-volatile memory using temperature sensor 有权
标题翻译：使用温度传感器对非易失性存储器进行自适应软编程的系统和方法
公开(公告)号：US09129700B2
公开(公告)日：2015-09-08
申请号：US13746841
申请日：2013-01-22
申请人： Jon S. Choy
发明人： Jon S. Choy
IPC分类号： G11C7/04 , G11C16/34 , G11C16/10 , G11C16/04 , G11C29/02 , G11C29/50
CPC分类号： G11C16/345 , G11C7/04 , G11C16/0483 , G11C16/10 , G11C29/021 , G11C29/028 , G11C2029/5002
摘要： Erasing of a non-volatile memory (NVM) having an array of bit cells includes soft programming after an initial erasing of the bit cells. Over-erased bit cells are determined. A temperature is detected. A first soft program gate voltage based on the temperature is provided. Soft programming on the over-erased bit cells using the first soft program gate voltage is performed. Any remaining over-erased bit cells are identified. if there are any remaining over-erased bit cells, soft programming is performed on the remaining over-erased bit cells using a second soft program gate voltage incremented from the first soft program gate voltage.
摘要翻译：擦除具有位单元阵列的非易失性存储器（NVM）包括在比特单元的初始擦除之后的软编程。确定过擦除的位单元。检测到温度。提供了基于温度的第一软程序栅极电压。执行使用第一软程序栅极电压对过擦除位单元进行软编程。识别任何剩余的超擦除位单元。如果存在任何剩余的过擦除位单元，则使用从第一软程序栅极电压增加的第二软程序栅极电压对剩余的过擦除位单元执行软编程。

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