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    • 12. 发明申请
    • DECISION FEEDBACK EQUALIZER AND RECEIVER CIRCUIT
    • 决策反馈均衡器和接收器电路
    • US20170054575A1
    • 2017-02-23
    • US15200626
    • 2016-07-01
    • FUJITSU LIMITED
    • Yasufumi Sakai
    • H04L25/03H04J11/00H04W72/04H04L12/26
    • H04L25/03057H04L25/03006
    • A plurality of comparator circuits output results of comparing a pulse amplitude modulated input signal having four or more values with a plurality of first thresholds. A selection section decides a value of the input signal at certain timing by selecting one of the comparison results on the basis of a result of deciding a value of the input signal at previous timing. A threshold setting section generates the first thresholds from a plurality of third thresholds obtained by adding an offset value based on magnitude of inter-symbol interference corresponding to each value to one of second thresholds whose number is based on the number of values, on the basis of an average value of third thresholds greater than a second threshold or third thresholds smaller than the second threshold and an adjustment value based on the decision result and sets the first thresholds in the comparator circuits.
    • 多个比较器电路输出具有四个或更多个值的脉冲幅度调制输入信号与多个第一阈值的结果。 选择部根据在上一次的时刻判定输入信号的值的结果,通过选择比较结果之一来决定某一定时的输入信号的值。 阈值设定部分根据多个第三阈值生成第一阈值,该多个第三阈值是通过将基于每个值的码元间干扰的大小的偏移值与基于值的数量的第二阈值之一相加而获得的, 具有大于第二阈值的第三阈值或小于第二阈值的第三阈值的平均值,以及基于判定结果的调整值,并且设置比较器电路中的第一阈值。