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11. 发明授权

US06199090B1 Double incrementing, low overhead, adder 失效
标题翻译：双倍递增，低开销，加法器
公开(公告)号：US06199090B1
公开(公告)日：2001-03-06
申请号：US09100499
申请日：1998-06-19
申请人： Sanjay Mansingh , Stephen Clark Purcell
发明人： Sanjay Mansingh , Stephen Clark Purcell
IPC分类号： G06F750
CPC分类号： G06F7/506
摘要： A double incrementing adder includes an AND gate configured to receive bits of the two input values of a common weight (“first weight”). The AND gate has an output terminal configured to carry the AND'ed bit. A three input XOR gate is configured to receive bits of the two input values of a common weight (“second weight”) one bit more significant than the first weight. The three input XOR gate is configured to XOR these values with the AND'ed bit to generate a three input XOR'ed bit.
摘要翻译：双增量加法器包括：与门，其被配置为接收公共权重（“第一权重”）的两个输入值的位。与门具有被配置为携带“与”位的输出端子。三输入XOR门被配置为接收比第一权重更有一位的公共权重（“第二权重”）的两个输入值的位。三个输入XOR门被配置为将这些值与“和”位进行异或运算，以产生三输入异或位。

12. 发明授权

US08327044B2 Transaction ID filtering for buffered programmed input/output (PIO) write acknowledgements 有权
标题翻译：用于缓冲编程输入/输出（PIO）写入确认的事务ID过滤
公开(公告)号：US08327044B2
公开(公告)日：2012-12-04
申请号：US13222531
申请日：2011-08-31
申请人： Sanjay Mansingh
发明人： Sanjay Mansingh
IPC分类号： G06F3/00 , G06F5/00
CPC分类号： G06F13/385
摘要： A PIO transaction unit includes an input buffer, a response buffer, and a control unit. The input buffer may receive and store PIO write operations sent by one or more transactions sources. Each PIO write operation may include a source identifier that identifies the transaction source. The response buffer may store response operations corresponding to respective PIO write operations that are to be transmitted to the transaction source identified by the source identifier. The control unit may store a particular response operation corresponding to the given PIO write operation in the response buffer prior to the given PIO write operation being sent from the input buffer. The control unit may store the particular response operation within the response buffer if the given PIO write operation is bufferable and there is no non-bufferable PIO write operation having a same source identifier stored in the input buffer.
摘要翻译： PIO交易单元包括输入缓冲器，响应缓冲器和控制单元。输入缓冲器可以接收和存储由一个或多个事务源发送的PIO写入操作。每个PIO写操作可以包括标识事务源的源标识符。响应缓冲器可以存储对应于要发送到由源标识符标识的事务源的各个PIO写入操作的响应操作。在从输入缓冲器发送给定的PIO写入操作之前，控制单元可以将对应于给定PIO写入操作的特定响应操作存储在响应缓冲器中。如果给定的PIO写入操作是可缓冲的并且不存在具有存储在输入缓冲器中的相同源标识符的不可缓冲PIO写入操作，则控制单元可以将特定响应操作存储在响应缓冲器内。

13. 发明申请

US20110145450A1 TRANSACTION ID FILTERING FOR BUFFERED PROGRAMMED INPUT/OUTPUT (PIO) WRITE ACKNOWLEDGEMENTS 有权
标题翻译：用于缓冲编程输入/输出（PIO）的事务识别过滤写入确认
公开(公告)号：US20110145450A1
公开(公告)日：2011-06-16
申请号：US12637338
申请日：2009-12-14
申请人： Sanjay Mansingh
发明人： Sanjay Mansingh
IPC分类号： G06F13/12
CPC分类号： G06F13/385
摘要： A PIO transaction unit includes an input buffer, a response buffer, and a control unit. The input buffer may receive and store PIO write operations sent by one or more transactions sources. Each PIO write operation may include a source identifier that identifies the transaction source. The response buffer may store response operations corresponding to respective PIO write operations that are to be transmitted to the transaction source identified by the source identifier. The control unit may store a particular response operation corresponding to the given PIO write operation in the response buffer prior to the given PIO write operation being sent from the input buffer. The control unit may store the particular response operation within the response buffer if the given PIO write operation is bufferable and there is no non-bufferable PIO write operation having a same source identifier stored in the input buffer.
摘要翻译： PIO交易单元包括输入缓冲器，响应缓冲器和控制单元。输入缓冲器可以接收和存储由一个或多个事务源发送的PIO写入操作。每个PIO写操作可以包括标识事务源的源标识符。响应缓冲器可以存储对应于要发送到由源标识符标识的事务源的各个PIO写入操作的响应操作。在从输入缓冲器发送给定的PIO写入操作之前，控制单元可以将对应于给定PIO写入操作的特定响应操作存储在响应缓冲器中。如果给定的PIO写入操作是可缓冲的并且不存在具有存储在输入缓冲器中的相同源标识符的不可缓冲PIO写入操作，则控制单元可以将特定响应操作存储在响应缓冲器内。

14. 发明申请

US20100312971A1 Dynamic Operating Point Modification in an Integrated Circuit 有权
标题翻译：集成电路中的动态工作点修改
公开(公告)号：US20100312971A1
公开(公告)日：2010-12-09
申请号：US12479063
申请日：2009-06-05
申请人： Maziar H. Moallem , Sanjay Mansingh , Richard F. Avra
发明人： Maziar H. Moallem , Sanjay Mansingh , Richard F. Avra
IPC分类号： G06F12/08
CPC分类号： G06F1/3203
摘要： In one embodiment, an integrated circuit includes a processor, an internal memory, and a memory controller coupled to an external memory. The integrated circuit may support two or more modes of operation, with different operating points. To switch from one operating point to another, code executed by the processor may copy switch code from the external memory into the internal memory, and may jump to the switch code. Executing out of the internal memory, the switch code may communicate with the memory controller to cause the external memory to enter into self-refresh mode. The operating point may be altered, and the switch code may reinitialize the memory controller after the integrated circuit has stabilized at the new operating point. After the memory controller's physical interface circuit has relocked, the external memory may exit self-refresh mode.
摘要翻译：在一个实施例中，集成电路包括处理器，内部存储器和耦合到外部存储器的存储器控制器。集成电路可以支持具有不同操作点的两种或更多种操作模式。要从一个工作点切换到另一个工作点，由处理器执行的代码可将外部存储器中的开关代码复制到内部存储器中，并可跳转到开关代码。从内部存储器执行，开关代码可以与存储器控制器通信，以使外部存储器进入自刷新模式。工作点可能会发生变化，并且开关代码可能会在集成电路稳定在新的工作点之后重新初始化存储器控制器。在内存控制器的物理接口电路重新锁定后，外部存储器可能会退出自刷新模式。

15. 发明授权

US06651159B1 Floating point register stack management for CISC 有权
标题翻译： CISC浮点寄存器堆栈管理
公开(公告)号：US06651159B1
公开(公告)日：2003-11-18
申请号：US09449956
申请日：1999-11-29
申请人： Tiruvur R. Ramesh , Sanjay Mansingh , Korbin Van Dyke
发明人： Tiruvur R. Ramesh , Sanjay Mansingh , Korbin Van Dyke
IPC分类号： G06F9455
CPC分类号： G06F9/45533 , G06F9/30105 , G06F9/30112 , G06F9/30123 , G06F9/30134 , G06F9/30174
摘要： A floating point register stack for a processor combines a plurality of two general purpose registers to form a register stack for x86 instructions and leaves the remaining general purpose registers for native instructions of the processor. By mapping x86 sources into the stack of two general purpose registers and operating x86 instructions on the x86 stack, the register stack for the processor is able to support both the processor's native instruction set and the x86 instruction set without increasing the size of the register stack.
摘要翻译：用于处理器的浮点寄存器堆栈组合多个两个通用寄存器以形成用于x86指令的寄存器堆栈，并留下剩余的通用寄存器用于处理器的本机指令。通过将x86源映射到x86堆栈中的两个通用寄存器堆栈和操作x86指令，处理器的寄存器堆栈能够支持处理器的本地指令集和x86指令集，而不增加寄存器堆栈的大小。

16. 发明授权

US06199089B1 Floating point arithmetic logic unit rounding using at least one least significant bit 有权
标题翻译：浮点运算逻辑单元使用至少一个最低有效位进行舍入
公开(公告)号：US06199089B1
公开(公告)日：2001-03-06
申请号：US09156817
申请日：1998-09-18
申请人： Sanjay Mansingh
发明人： Sanjay Mansingh
IPC分类号： G06F738
CPC分类号： G06F7/485 , G06F7/49947
摘要： A floating point unit includes a rounding unit that rounds the two least significant bits of a sum. After a sum of the two mantissas is generated the at least one least significant bit is separated from the sum. When addition is performed, two least significant bits are separated from the sum. A half add unit may be used to generate the sum along with a set of carry data, and thus at least one least significant bit of the carry data is also separated. A rounding unit receives the separated at least one least significant bit of the sum and carry data and produces a carry in bit as well as rounded at least one least significant bit. The sum and carry data are then summed in a later stage of the floating point unit to form both a unincremented sum and an incremented sum, which are stored in a multiplexer. The carry in bit is used to select one of the unincremented sum and incremented sum. The rounded at least one least significant bit produced by the rounding unit is then united with the selected one of the unincremented sum and incremented sum.
摘要翻译：浮点单元包括舍入一个和的两个最低有效位的舍入单元。在生成两个尾数的总和之后，至少一个最低有效位与和分离。当执行加法时，两个最低有效位与和分离。可以使用半加单位与一组进位数据一起生成和，因此进位数据的至少一个最低有效位也被分离。舍入单元接收所述和的分离的至少一个最低有效位并且携带数据并产生位的进位以及舍入至少一个最低有效位。然后将和和进位数据在浮点单元的后期相加，以形成存储在多路复用器中的未增加的和和递增的和。进位位用于选择未增加的和和递增和之一。然后，由舍入单元产生的至少一个最低有效位的舍入与所选择的未增加的和和递增和之一相结合。

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