专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US09661577B2 Power management module and method therefor 有权
公开(公告)号：US09661577B2
公开(公告)日：2017-05-23
申请号：US14505538
申请日：2014-10-03
申请人： Amir David Modan , Ron-Michael Bar , Eran Glickman
发明人： Amir David Modan , Ron-Michael Bar , Eran Glickman
IPC分类号： G08C17/00 , H04W52/02
CPC分类号： H04W52/0258 , H04W52/0235 , H04W52/028 , Y02D70/00
摘要： A power management module comprising a client monitoring component arranged to monitor idle periods for a client component, and derive at least one idle period characteristic value for the client component based at least partly on the monitoring of the idle periods therefore. The power management module further comprises a power mode control component arranged to receive an indication of the client component entering an idle state, cause the client component to be put into a reduced power mode upon expiry of a first period of time, and cause the client component to be brought out of the reduced power mode upon expiry of a second period of time. At least one of the first and second periods of time is configured based at least partly on the idle period characteristic value(s) derived by the client monitoring component for the client component.

12. 发明授权

US08458364B2 Method for receiving and processing frames and a device having frame receiving and processing capabilities 有权
标题翻译：用于接收和处理帧的方法和具有帧接收和处理能力的设备
公开(公告)号：US08458364B2
公开(公告)日：2013-06-04
申请号：US12375795
申请日：2006-08-02
申请人： Yaron Alankry , Eran Glickman , Erez Parnes , Daniel Rozovsky
发明人： Yaron Alankry , Eran Glickman , Erez Parnes , Daniel Rozovsky
IPC分类号： G06F15/16 , G04F1/00
CPC分类号： H04J3/0697 , H04J3/0667
摘要： A device having frame receiving and processing capabilities and a method for receiving and processing frames. The method includes: receiving a frame; associating a frame timestamp with the frame; storing the frame and the associated timestamp at a certain buffer out of a group of buffers; generating a valid timing information frame indicator if the received frame is a valid timing information frame; and storing the valid timing information frame indicator at a certain buffer descriptor associated with the certain buffer.
摘要翻译：具有帧接收和处理能力的设备以及用于接收和处理帧的方法。该方法包括：接收帧; 将帧时间戳与帧相关联; 将帧和相关联的时间戳存储在一组缓冲器之外的某个缓冲器处; 如果接收到的帧是有效的定时信息帧，则生成有效的定时信息帧指示符; 以及将所述有效定时信息帧指示符存储在与所述特定缓冲器相关联的特定缓冲器描述符处。

13. 发明授权

US08452553B2 Device and method for testing a circuit 有权
标题翻译：用于测试电路的装置和方法
公开(公告)号：US08452553B2
公开(公告)日：2013-05-28
申请号：US12516319
申请日：2006-11-30
申请人： Eran Glickman , Yaron Alankry , Erez Arbel-Meirovich , Erez Parnes
发明人： Eran Glickman , Yaron Alankry , Erez Arbel-Meirovich , Erez Parnes
IPC分类号： G01R31/00
CPC分类号： G06F11/2236
摘要： A device and a method. The device includes: (i) a processor, connected to the receiver, (ii) an interface adapted to receive a test vector and to output a test response, the test vector includes a first group of signals that include idle signals and at least one information frame and a second group of signals that include timing signals and data signals; and (iii) a receiver, connected to the interface. The receiver is adapted to receive the first group of signals and filter out the idle signals and at least one instruction frame delimiters to provide at least one instruction. The device is adapted to send the at least one instruction to at least one instruction buffer. The processor is adapted to execute at least one instruction stored in the at least one instruction buffer and to respond to the second group of signals such as to provide test responses.
摘要翻译：一种设备和方法。该设备包括：（i）连接到接收器的处理器，（ii）适于接收测试向量并输出测试响应的接口，测试向量包括第一组信号，包括空闲信号和至少一个信息帧和包括定时信号和数据信号的第二组信号; 和（iii）连接到接口的接收器。接收器适于接收第一组信号并滤除空闲信号和至少一个指令帧分隔符以提供至少一个指令。该设备适于将至少一个指令发送到至少一个指令缓冲器。处理器适于执行存储在至少一个指令缓冲器中的至少一个指令，并且响应于第二组信号，以便提供测试响应。

14. 发明授权

US11126522B2 Method and apparatus for offloading functional data from an interconnect component 有权
公开(公告)号：US11126522B2
公开(公告)日：2021-09-21
申请号：US14897671
申请日：2013-06-18
申请人： Benny Michalovich , Ron Bar , Eran Glickman , Dmitriy Shurin
发明人： Benny Michalovich , Ron Bar , Eran Glickman , Dmitriy Shurin
IPC分类号： G06F11/30 , G06F11/36 , G06F11/22 , G06F13/28
摘要： An interconnect offload component arranged to operate in an offloading mode, and a memory access component for enabling access to a memory element for functional data transmitted over a debug network of a signal processing device. In the offloading mode the interconnect offload component is arranged to receive functional data from an interconnect client component for communication to a destination component, and forward at least a part of the received functional data to a debug network for communication to the destination component via the debug network. The memory access component is arranged to receive a debug format message transmitted over the debug network, extract functional data from the received debug format message, said functional data originating from an interconnect client component for communication to a memory element, and perform a direct memory access to the memory element comprising the extracted functional data.

15. 发明授权

US09780949B2 Data processing device and method for protecting a data processing device against tampering 有权
公开(公告)号：US09780949B2
公开(公告)日：2017-10-03
申请号：US14905207
申请日：2013-07-24
申请人： Eran Glickman , Ron Bar , Benny Michalovich
发明人： Eran Glickman , Ron Bar , Benny Michalovich
IPC分类号： H04L29/06 , H04L9/10 , G06F21/55 , G06F21/86
CPC分类号： H04L9/10 , G06F21/755 , G06F21/86 , H04L2209/12
摘要： A data processing device comprises a protection key unit, a dummy key unit, and a control unit. The protection key unit provides a protection key. The dummy key unit provides a dummy key. The dummy key unit has a set of two or more allowed dummy key values associated with it and is configurable by a user or a host device to set the dummy key to any value selected from said set of allowed dummy key values. The control unit is connected to the dummy key unit and to the protection key unit and arranged to set the protection key to the value of the dummy key in response to a tamper detection signal (fatal_sec_vio) indicating a tamper event. The value of the dummy key may notably be different from zero.A method of protecting a data processing device against tampering is also described.

16. 发明授权

US09626127B2 Integrated circuit device, data storage array system and method therefor 有权
公开(公告)号：US09626127B2
公开(公告)日：2017-04-18
申请号：US13810350
申请日：2010-07-21
申请人： Eran Glickman , Ron Bar , Benny Michalovich
发明人： Eran Glickman , Ron Bar , Benny Michalovich
IPC分类号： G06F12/00 , G06F12/08 , G06F3/06 , G06F11/10
CPC分类号： G06F3/0683 , G06F11/1088
摘要： An integrated circuit device comprises a data storage array controller for providing data storage array functionality for at least one data storage array. The data storage array controller comprises an address window controller arranged to receive at least one data storage device access command, and upon receipt of the at least one data storage device access command the address window controller is arranged to compare a target address of the at least one data storage device access command to an address window for a target storage device of the at least one data storage device access command, and if the target address is outside of the address window for the target storage device, block the at least one data storage device access command.

17. 发明授权

US09529745B2 System on chip and method of operating a system on chip 有权
标题翻译：片上系统和芯片上系统的操作方法
公开(公告)号：US09529745B2
公开(公告)日：2016-12-27
申请号：US14190374
申请日：2014-02-26
申请人： Nir Atzmon , Ron-Michael Bar , Eran Glickman , Benny Michalovich
发明人： Nir Atzmon , Ron-Michael Bar , Eran Glickman , Benny Michalovich
IPC分类号： G06F13/16 , G06F13/38 , G06F13/32
CPC分类号： G06F13/1673 , G06F13/32
摘要： A system on chip, SoC, comprising two or more data sources, a memory unit, a memory control unit, and a processing unit. Each of the data sources is capable of providing a data stream. The memory control unit is arranged to maintain, for each of the data streams, a buffer in the memory unit and to route the respective data stream to the processing unit via the respective buffer. Each of the buffers has buffer characteristics which are variable and which comprise at least the amount of free memory of the respective buffer. The memory control unit is arranged to allocate and de-allocate memory regions to and from each of the buffers in dependence of the buffer characteristics of the respective buffer, thereby allowing for re-allocation of memory of the memory unit among the buffers.A method of operating a system on chip is also described.
摘要翻译：还描述了一种操作片上系统的方法。

18. 发明申请

US20130117506A1 INTEGRATED CIRCUIT DEVICE, DATA STORAGE ARRAY SYSTEM AND METHOD THEREFOR 有权
标题翻译：集成电路设备，数据存储阵列系统及其方法
公开(公告)号：US20130117506A1
公开(公告)日：2013-05-09
申请号：US13810350
申请日：2010-07-21
申请人： Eran Glickman , Ron Bar , Benny Michalovich
发明人： Eran Glickman , Ron Bar , Benny Michalovich
IPC分类号： G06F3/06
CPC分类号： G06F3/0683 , G06F11/1088
摘要： An integrated circuit device comprises a data storage array controller for providing data storage array functionality for at least one data storage array. The data storage array controller comprises an address window controller arranged to receive at least one data storage device access command, and upon receipt of the at least one data storage device access command the address window controller is arranged to compare a target address of the at least one data storage device access command to an address window for a target storage device of the at least one data storage device access command, and if the target address is outside of the address window for the target storage device, block the at least one data storage device access command.
摘要翻译：集成电路装置包括用于为至少一个数据存储阵列提供数据存储阵列功能的数据存储阵列控制器。数据存储阵列控制器包括一个地址窗口控制器，被布置为接收至少一个数据存储设备访问命令，并且在接收到至少一个数据存储设备访问命令时，地址窗口控制器被设置为比较至少一个数据存储设备访问命令到所述至少一个数据存储设备访问命令的目标存储设备的地址窗口，并且如果所述目标地址在所述目标存储设备的地址窗口之外，则阻止所述至少一个数据存储设备访问命令。

19. 发明申请

US20090198926A1 METHOD AND DEVICE FOR SWITCHING DATA 审中-公开
标题翻译：用于切换数据的方法和装置
公开(公告)号：US20090198926A1
公开(公告)日：2009-08-06
申请号：US12301472
申请日：2006-05-29
申请人： Eran Glickman , Yaron Alankry , Avihai Graizei
发明人： Eran Glickman , Yaron Alankry , Avihai Graizei
IPC分类号： G06F12/02 , G06F12/00
CPC分类号： H04J3/1623
摘要： A method, the method includes providing data; retrieving interleaving command information from a two dimensional array of interleaving command information; wherein the two dimensional array includes multiple interleaving command information rows, each row includes interleaving commands associated with multiple TDM time slots; and determining, in response to the retrieved interleaving command information, whether to provide data from a first data source or from a second data source.
摘要翻译：一种方法，所述方法包括提供数据; 从交织命令信息的二维阵列中检索交织命令信息; 其中所述二维阵列包括多个交织命令信息行，每行包括与多个TDM时隙相关联的交织命令; 以及响应于所检索的交织命令信息，确定是从第一数据源还是从第二数据源提供数据。

20. 发明申请

US20080313237A1 Method for High Speed Framing and a Device Having Framing Capabilities 有权
标题翻译：高速帧的方法和具有成帧能力的设备
公开(公告)号：US20080313237A1
公开(公告)日：2008-12-18
申请号：US12160007
申请日：2006-01-04
申请人： Klod Asoline , Eran Glickman , Adi Katz
发明人： Klod Asoline , Eran Glickman , Adi Katz
IPC分类号： G06F17/30
CPC分类号： H04L69/324
摘要： A device having framing capabilities, the device includes at least one memory unit adapted to store data and metadata required for framing the stored data; the device is characterized by including a framer that is connected to a framed data unit and to a data fetch unit; wherein the device is adapted to select between a first operation sequence and a second operation sequence; wherein the first operation sequence comprises a data chunk and metadata fetch operation followed by a data chunk frame operation and wherein the second operation sequence comprises a multiple data chunk fetch operation followed by multiple data chunk frame operations; wherein the data fetch unit and the framer are adapted to execute the selected operation sequence. A method for framing data, the method includes storing data and metadata required for framing the stored data at one or more memory devices. The method is characterized by executing an operation sequence out of a first operation sequence and a second operation sequence; wherein the first operation sequence comprises a data chunk and metadata fetch operation followed by a data chunk frame operation and wherein the second operation sequence comprises a multiple data chunk fetch operation followed by multiple data chunk frame operations.
摘要翻译：一种具有成帧功能的设备，该设备包括至少一个存储器单元，适于存储对存储的数据进行成帧所需的数据和元数据; 该装置的特征在于包括连接到成帧数据单元和数据获取单元的成帧器; 其中所述设备适于在第一操作序列和第二操作序列之间进行选择; 其中所述第一操作序列包括数据块和元数据获取操作，随后是数据块帧操作，并且其中所述第二操作序列包括多数据块提取操作，随后是多个数据块帧操作; 其中所述数据提取单元和所述成帧器适于执行所选择的操作序列。一种用于对数据进行成帧的方法，所述方法包括存储在一个或多个存储器设备上对存储的数据进行成帧所需的数据和元数据。该方法的特征在于执行第一操作序列和第二操作序列中的操作序列; 其中所述第一操作序列包括数据块和元数据获取操作，随后是数据块帧操作，并且其中所述第二操作序列包括多数据块提取操作，随后是多个数据块帧操作。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式